Lecture Slides Post DAC For 8085 Interface

DEVICE TO DEVICE COMMUNICATION
75
BASIC MODES OF COMMUNICATION
 Parallel communication implies sending a whole byte (or more) of data over multiple
parallel wires
 Serial communication implies sending data bit by bit over a single wire
 Asynchronous: Universal asynchronous receiver/transmitter (UART Standard)

 Synchronous: Serial peripheral interface (SPI Standard)
DEVICE TO DEVICE COMMUNICATION
Parallel Communication Serial Communication

SERIAL COMMUNICATION
 Simplex: Data are transmitted only in one direction Transmitter Receiver
 Duplex: Data are transmitted both directions

Transmitter Receiver
 Half Duplex: Data are transmitted both
directions but one way at a time
Receiver Transmitter
 Full Duplex: Data are transmitted both
directions simultaneously
Receiver Transmitter
SERIAL COMMUNICATION: SYNCHRONOUS MODE
Synchronous
Communication
SERIAL COMMUNICATION: SYNCHRONOUS MODE
• In the synchronous mode, the transmitter and receiver share a common clock
• The transmitter typically provides the clock as a separate signal in addition to the
serial data
Clock
Data
1 byte-wide Data 1 byte-wide Data
The Transmitter
 Shifts the data onto the serial line using its The Receiver
own clock  Extracts the data using the clock
provided by the transmitter
 Provides the clock as a separate signal
 Converts the serial data back to the
parallel form
 No start, stop, or parity bits added to data
SERIAL COMMUNICATION: ASYNCHRONOUS MODE
Asynchronous
Communication
 With asynchronous communication, the transmitter and receiver do not share a
common clock
Add: Start, Stop, Parity Bits Remove: Start, Stop, Parity Bits
Transmitter + – Receiver
Data
1 byte-wide Data 1 byte-wide Data
The Transmitter The Receiver
 Shifts the parallel data onto the  Extracts the data using its own clock
serial line using its own clock
 Converts the serial data back to the
 Also adds the start, stop and parallel form after stripping off the
parity check bits start, stop and parity bits
Start Bit Bit time Sec Parity Bit 1 or 2 Stop Bits
Mark (Active low / 0) (Active high / 1)
D0 D1 D2 D3 D4 D5 D6 D7
1 Asynchronous Byte
 Baud rate (B bps): Bit rate of the serial port

 Throughput: Actual data transmitted per sec (total bits transmitted—overhead)
 Example: 115200 baud = 115200 bits/sec
 If using 8-bit data, 1 start, 1 stop, and no parity bits, the effective
throughput is: 115200 * 8 / 10 = 92160 bits/sec
 Frame: 1 asynchronous byte is a packet / frame of bits
 Error Check
 Parity: even or odd parity is indicated by transmitter and checked at
receiver’s end
 Checksum: Sum of all data byte along with its 2’s complement –as last
byte sent by the transmitter and checked at receiver’s end
(result = 0 for no error)
 Error Check
 Cyclic Redundancy:
Transmission Process:
1. Inform the receiver of the beginning and the end of the transmission and error
check
2. Convert a parallel word into stream of serial bits
3. Transmit one bit at a time with appropriate time delay, using one data line of an
output port. The time delay is determined by the speed of the transmission
Reception Process:
1. Recognize the beginning of the transmission

2. Receive serial bits, one at a time, and convert them into parallel byte
3. Check for errors and recognize the end of transmission
 Software controlled asynchronous serial communication

mode
 Hardware controlled asynchronous serial communication

mode
 Output a start bit
 Convert the character to be

sent in a stream of serial
bits with appropriate delay
 Add error check bit
 Output one or two stop bits

SOFTWARE SERIAL COMMUNICATION IN 8085
 Serial Input Data (SID)
 Serial Output Data (SOD)

Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
57. Set Interrupt Mask SIM - 1 1 4 30 No Flag
95
STARTSOD: MVI C, 0BH ;Set up counter C to count eleven bits
XRA A ; Reset carry to 0
NXTBIT: MVI A, 80H ;Set D to 1 in the accumulator
RAR ; Bring carry into D =0 for 1st time and set D to 1
SIM ;Output D =0 to mark the beginning of the frame
CALL BITTIME ; Wait up to bit-time s for bps baud rate
STC ;Set carry to 1 to ensure two stop bits
MOV A,B ;Place the ASCII character to be sent in ACC
RAR ;Place LSB of ASCII character in carry
MOV B,A ;Save the content for next transmit
DCR C ;One bit transmitted, decrease the counter
JNZ NXTBIT ;If all bits are not transmitted continue the loop
RET ;return to main program after transmission is complete 96
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
58. Read Interrupt Mask RIM - 1 1 4 20 No Flag
97
 Recognize start bit (with

half bit delay)
 Read the data each data

bit after every bit time as
per baud rate and count
the number of bits
 Check for errors after last

data bit and wait for one or
two stop bits and continue
STARTSID: RIM ;Read SID line
RAL ; Place D into carry
JC STARTSID ;If D is 1 ⇒ This is not a start bit of a frame so continue read SID
CALL HALFBIT ; If D =0 wait for half bit s for bps baud rate
MVI C, 09H ;Set counter for 9 bits
NXTBIT: CALL BITTIME ; Wait up to bit-time s for bps baud rate
RIM ; Read SID line
RAL ;Place the data bit in carry
DCR C ;One bit is read
JZ BACK ;If all bits are read return to main program
RAR ;Place the carry bit (LSB data is coming first) to D & shift all other
;bit by one position
MOV B, A ;Save data in B
JMP NXTBIT ;Get the next bit 99
BACK: RET ; Return to main program

SERIAL INTERFACE CONTROLLER: 8251
 Data Bus Buffer

 Transmit Buffer
 Receive Buffer
Data, Control words, Command words &

status information passes through the buffers
100
Data Buffer TRANSMITTER

−
Register
⁄
/ =0 0 0 1 0 8251A DATA DATA BUS
OR 0 1 0 0 DATA BUS  8251A DATA
Internal Data Bus

1 0 1 0 STATUS  DATA BUS
Control
Register 1 1 0 0 DATA BUS  CONTROL
/ =1
/ Read/Write 16-Bit X 1 1 0 DATA BUS  3 STATE
Control =0
X X X 1 DATA BUS  3 STATE
Logic
RESET
CLK Status RECEIVER
Register
/ =1
8-Bit
=0
101
Internal Functional Description Typical Specification
Unit/Signal
lines
Data Bus Buffer • Tri-state, bidirectional, & 8-bit
• Transmit & receive data upon CPU instruction
• Separate Command Status, Data-in & Data-out
registers
Reset A high or reset command leads idle mode Minimum clock pulse width 6*Tclk
Clk Generates internal device timing Fclk ≥ 30 Data bit rate
WR CPU writes data or control words with low logic
RD CPU reads data or status information with low logic
C/D Indicates the signals on the data bus is either data 1: Control/Status Word
or control words or status information 0: Data
CS A low on it selects the device
102
Output Receiver TxD
Internal Data Bus

Transmitter
Buffer Register
Data Buffer
Register TxRDY
Transmitter
Control Logic TxE
Internal Unit/Signal lines Functional Description

Transmitter Buffer • Parallel data -> Serial Data
• Inserts the appropriate characters required for communication protocol
• Transmit serial bits at TxD pin on falling edge of TxC
• TxD line will be at tri-state if reset, Tx Enable and CT = 1, or buffer is empty.
TxRDY • Indicate the CPU that transmitter is ready to accept a data character
• It can be used as interrupt to the system
• It is automatically reset by WR signal
TxE • Goes high when no characters to send and resets upon receiving characters from CPU
• Useful when half duplex mode is used
103
TxC • Determine the bit rate (BAUD Rate)
• 1x, ×, × BAUD Rate
Internal Data Bus

Input Receiver RxD
Data Buffer Receiver

Register Buffer
Register
Receiver
Control Logic RxRDY
Internal Unit/Signal lines Functional Description

Receiver Buffer • Serial data -> Parallel Data
• Checks the appropriate characters required for communication protocol
• Receives serial bits at RxD pin on rising edge of RxC
• TxD line will be at tri-state if reset, Tx Enable and CT = 1, or buffer is empty.
RxRDY • Indicate the CPU that data is ready to be read
• It can be used as interrupt to the system
• It is automatically reset by WR signal
RxC • Determine the bit rate (BAUD Rate) 104
• Frequency is 1x, ×, × BAUD Rate
PROGRAMMING 8251 FOR ASYNCHRONOUS SERIAL COMMUNICATION
Initialization of 8251
1. Mode Word: Baud rate, Stop bit, & Error Checking bit information
Control Register (16-bit)
2. Command Word: Enables data transmission and/or reception
3. Status word: Provides information of register status & transmission error Status Register (8-bit)
105
Mode Word:
Baud Rate Factory

00 SYN Mode
01  ASYN X1
ASYN( 00) 10  ASYN X16
11  ASYN X64
Framing Control Parity Control Character Length

00  Not Valid X0  No Parity 00  5 Bits
01  1 Stop Bit 01  Odd Parity 01  6 Bits
10  1 ½ Stop Bits 11  Even Parity 10  7 Bits
11  2 Stop Bits 11  8 Bits
106
Command Word:
EH IR RTS ER SBRK RxE DTR TxEN
Transmit Enable
1 = Enable
0 = Disable
Enable Hunt Mode* Data Terminal Ready

1 = Enable Search for 1 = Enable DTR
Sync Characters
Receive Enable
Internal Reset 1 = Enable
1 = Resets 8251 to 0 = Disable
Mode
Send Break
Request to send Character
1 = Enable RTS 1 = Forces TxD
Error Reset
“Low”
1 = Reset Error Flags
0 = Normal
PE, OE, FE
Operation
* (Has No Effect in Asyc Mode)
Note: Error Reset must be performed whenever RxEnable and
Enter Hunt are programmed. 107
Status Word:
DSR SYNDET/BRKDET FE OE PE TxEMPTY RxRDY TxRDY

Note 1: TxRDY status
Note 1 bit has different
Same Definitions as I/O pins meanings from the
Parity Error TxRDY output pin.
The PE flag is set when a parity error is detected. It is
reset by the ER bit of the Command Instruction. PE does The former is not
not inhibit operation of the 8251A.
conditioned
Overrun Error by and TxEN;
The OE flag is set when the CPU does not read a character
before the next one becomes available. It is reset by the ER
the latter is
bit of the Command Instruction. OE does not inhibit conditioned by both
operation of the 8251A; however, the previously overrun
character is lost. and TxEN.
Data Set Ready: Indicates that the DSR is at
Framing Error (Async only)
i.e. TxRDY status bit
zero level.
The FE flag is set when a valid Stop bit is not detected at = DB Buffer Empty
the end of every character. It is rest by the ER bit of the
Command Instruction. FE does not inhibit the operation of TxRDY pin out = DB
the 8251A.
Buffer Empty ( =
0) (TxEN = 1081)\
109
• A program sequence which initializes the mode register and gives a command to enable the
transmitter and begin an asynchronous transmission of 7-bit characters followed by an even-parity
bit and 2 stop bits is:
MOV A, FAH
OUT FF H
MOV A, 33H
OUT FFH
110
Initialization Instructions
SET UP: MVI A, CAH ;Load the mode word
OUT FFH ;Write mode word in control register
MVI A,11H ;Load the command word to enable transmitter
OUT FFH ;Enable the transmitter
STATUS: IN FFH ;Read status register
ANI 01H ;Mask all bits except
JZ STATUS ;If = 0, the transmitter buffer is full; go back
;and wait
111
Transmission:
LXI SP, STACK JZ STATUS ;Is TxRDY 1?
LXI H, XX70H ;Memory pointer for message
; If not, wait
MOV C, M ;Set up register C as counter
INX H ;Point to next character
MVI A,00H ;Dummy mode word
MOV A,M ;Place character in the
OUT FFH ;Write dummy
accumulator
OUT FFH ; word in See
program
OUT FEH ;Send character to the
OUT FFH ; mode transmitter
description
; register
DCR C ;One character transmitted:
MVI A,40H ;Reset word ; decrement the counter
OUT FFH ;Reset 8251 JNZ STATUS ;If all characters are not yet
MVI A,CAH ;Initialize 8251 ;transmitted, go back and
OUT FFH ;transmit again
MVI A,11H HLT
OUT FFH
STATUS IN FFH 112
ANI 01H ;Check TxRDY

Reception:
Write the code as an assignment to receive
113
SERIAL COMMUNICATION: LOGIC PROTOCOL
SERIAL COMMUNICATION: MAX232
Internal Functional Description Typical Specification

Unit/Signal
lines
DSR Data Set • 1-bit inverting input port (w.r.t. CPU)
Ready • CPU can read its status to know modem condition
DTR Data • 1-bit inverting output port (w.r.t. CPU)
Terminal Ready • CPU can write low to control modem condition
RTS Request To • 1-bit inverting output port (w.r.t. CPU)
Send • CPU can write low to control modem condition
CT Clear To • A low on it enables the device to transmit serial
Send data if Tx enable = 1 in command word
116
PROGRAMMABLE INTERRUPT CONTROLLER
117
PIN OUT & SIGNAL FLOW DIAGRAM
118
INTERRUPT SIGNALS
119
INTERRUPT PRIORITY, VECTOR ADDRESS, SENSITIVITY
Name Priority Address Branched to (1) Type Trigger

When Interrupt Occurs
TRAP 1 24H Rising Edge AND High Level until
Sampled
RST 7.5 2 3CH Rising Edge (Latched)
RST 6.5 3 34H High Level until Sampled
RST 5.5 4 2CH High Level until Sampled
INTR 5 (Note 2) High Level until Sampled
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the CPU when the
120
interrupt is acknowledged.
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Resart
Flags Add. (H)
54. PC points to an address location RST 0 1 3 12 C7 No Flag 0000
in page 0 of memory associated 1 CF 0008
to each of the 8 restart
instruction, after pushing its 2 D7 0010
current content –address of next 3 DF 0018
instruction –on stack. 4 E7 0020
5 EF 0028
6 F7 0030
7 FF 0038
55. Enables interrupts EI - 1 1 4 FB
56. Disables interrupt DI - 1 1 4 F3
121
Opcode Operand Hex Code Resart

Add. (H)
RST 0 C7 0000
1 CF 0008
2 D7 0010
3 DF 0018
4 E7 0020
5 EF 0028
6 F7 0030
7 FF 0038
122
Priority Type Triggering Resart Add.

Method (H)
5 INTR High level See
previous
table for
RST
4 RST 5.5 High level 002C
3 RST 6.5 High level 0034
2 RST 7.5 Rising Edge 003C
1 TRAP Rising Edge 0024
& High level
123
PROGRAMMABLE INTERRUPT CONTROLLER: 8259A
Designed to work with 8080 A, 8085, 8086, 8088.
 Handle eight interrupt inputs. This is equivalent to providing eight interrupt
pins on the processor in place of one INTR/INT pin.
 Vector an interrupt request anywhere in the memory map. However, all the
eight interrupt are spaced at the interval of either four or eight location. This
eliminates the major drawback, 8085 interrupt, in which all interrupts are
vectored to memory location on page 00H.
 Resolve eight levels of interrupt priorities in a variety of modes.

124
 Mask each interrupt request individually.
 Read the status of pending interrupts, in service interrupts, and masked interrupts.
 Be set up to accept either the level triggered or edge triggered interrupt request.
 Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt

inputs.
125
126
127
128
129
8259A: INTERRUPT REGISTERS & PRIORITY RESOLVER
 Interrupt request register (IRR)
 The IRR is used to store all the interrupt levels which are requesting service
 In service register (ISR)

 ISR is used to store all the interrupt levels which are being serviced
 Interrupt mask register (IMR)

 The IMR stores the bits which mask the interrupt lines to be masked. The IMR
operates on the IRR. Masking of a higher priority input will not affect the interrupt
request lines of lower quality
 Priority Resolver
 This logic block determines the priorities of the bits set in the IRR. The highest priority is
selected and strobbed into the corresponding bit of the ISR during INTA pulse
CPU-DEVICE COMMUNICATION MODE
131
Polling Mode Interrupt Driven Mode
8259A: MASTER AND SLAVE CONFIGURATION
• Master: The 8259A connected directly into the CPU (8085, 8086 etc.) INTR pin is
called as master
• Slave: The INT pin from the other 8259A connects into an IR input on the master.
This secondary or cascaded device is called as a slave
8259A: INTERFACE TO STANDARD SYSTEM BUS
8259A: CASCADED MODE
8259A: INTERRUPT SEQUENCE OF OPERATION
1. One or more of the INTERRUPT REQUEST lines (IR7–0) are raised high, setting the
corresponding Interrupt Request Register (IRR) bit(s).
2. The 8259A evaluates these requests –resolves priority, and sends an INT to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority In-Service Register (ISR)
bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL
instruction code (11001101) onto the 8-bit Data Bus through its D7–0 pins.
8259A: INTERRUPT SEQUENCE OF OPERATION
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the
CPU group.
6. These two INTA pulses allow the 8259A to release its pre-programmed subroutine address
onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the
higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the Automatic End of
Interrupt (AEOI) mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the
ISR bit remains set until an appropriate EOI command is issued at the end of the
interrupt sequence. This option is determined by initialization command word (ICW)
8. The program counter points to the memory location specified by the CALL instruction
8259A: PROGRAMMING
 The 8259A is programmed by properly initializing:

• 4 Initialization Command Words (ICW)
• 3 Operation Command Words (OCW). The OCWs can be written into the 8259A
anytime after initialization.
 The initialization procedure may not need to initialize all of them.

8259A: OPERATION SEQUENCE
Not required Always

Operation Command/Operation Address
Sequence Word (Example)
1 ICW1 50H
2 ICW2 51H
3 ICW3 51H
4 ICW4 51H
Any OCW1 51H
Sequence OCW2 50H
OCW3 50H
8259A: INITIALIZATION
ICW1 To initialize
 A single or cascaded 8259s
 Level trigger or edge triggered input
 ICW4 is needed or not
ICW2
 Load the high order byte of the interrupt vector address of all
the interrupts
8259A: INITIALIZATION OF VECTOR ADDRESS
CD H (Hex code of Call instruction)
Lower Byte of Vector Address
Upper Byte of Vector Address

ICW3
 Initialized only when cascaded 8259s are used
 A single 8259 can connect to 8 slaves 8259s providing up
to 64 hardware interrupts
 There are separate ICW3 words for the master and the
slave
ICW4 Initialized for
 80x86 or 8085
 Auto or Normal EOI (End of
Interrupt)
 Buffered or non buffered
 Special or not special fully
nested mode
 If
• Auto EOI: No need for an EOI
instruction used before RETI
in interrupt service routine
• Normal EOI: ICW2 must be
initialized
• Masked mode (cascaded): D4
must be 1
8259A: INTERRUPT MODES
Interrupt Modes Configured by OCWs

1. Fully nested mode (Default mode after ICWs)
2. Rotating priority mode
3. Special mask mode
4. Polled mode
8259A: OPERATION COMMAND
Operation Command/Operation Address

Sequence Word (Example)
1 ICW1 50H
2 ICW2 51H
3 ICW3 51H
4 ICW4 51H
Any OCW1 51H
Sequence OCW2 50H
OCW3 50H
8259A: END OF INTERRUPT (EOI)
 The In Service (IS) bit can be reset either automatically following the trailing edge of the
last in sequence INTA pulse (when AEOI bit in ICW1 is set) or by a command word that
must be issued to the 8259A before returning from a service routine (EOI command).
 An EOI command must be issued twice if in the Cascade mode, once for the master
and once for the corresponding slave.
 There are two forms of EOI command: Specific and Non-Specific.
• In Specific mode fully nested structure is preserved; specific IS bit for the peripheral
device to reset on EOI.
• In non-specific EOI mode the highest IS bit of those that are set, are automatically
reset; in the fully nested mode the highest IS level was necessarily the last level
acknowledged and serviced.
8259A: AUTOMATIC END OF INTERRUPT (EOI)
 If AEOI = 1 in ICW4, then the 8259A will operate in AEOI mode continuously until
reprogrammed by ICW4.
 In this mode the 8259A will automatically perform a non-specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse (third pulse in MCS-80/85, second
in 8086).
 This mode should be used only when a nested multilevel interrupt structure is not
required within a single 8259A.
 The AEOI mode can only be used in a master 8259A and not a slave.
8259A: EXAMPLE
Four sources are connected to IR lines of 8259A: emergency signal, keyboard, A/D converter
and printer. Of these the emergency signal has the highest priority and printer has the lowest
priority. The vector address starts from 2060 and the space between consecutive ISR
location is 4. Interrupt is to be sensed by edge triggering. Activate automatic end of interrupt.
PROGRAMMABLE INTERVAL TIMER
151
PROGRAMMABLE INTERVAL TIMER: 8253 / 54
 Generation of accurate time delay under software control
 No use of looping in system software; Only configuring

the hardware inside 8253/54
 Interrupts the CPU with precise time delays
 Lower software overhead
 Multiple delays can be easily maintained by assignment

of priority levels
 Non-delay type counter/timer operations are possible

152
8253: INTERNAL ARCHITECTURE
 6 programmable timer modes
 3 counters: counters 0, 1, 2
 Each counter with 2 inputs (Clock, &

Gate) and one output (Out)
 Variable function assertion on these lines

changes; depends on initialization of the
device.
153
8253: COUNTER
 16-bit pre-settable down counter
 Counts in binary or BCD
 The inputs (Clock, & Gate) and the output

(Out) configured by ‘modes’ in control
register
 Separate configuration for each counter
 Auto reload of count values
 On-the-fly reading of counter status; no

inhibition of clock
154
8253: OPERATION CODES
155
8253: SYSTEM INTERFACE
156
8253: PROGRAMMING
Control word
157
8253: PROGRAMMING
Control word
158
8253: PROGRAMMING
Control word
159
8253: PROGRAMMING
160
8253: PROGRAMMING
161
8253: PROGRAMMING
162
8253: PROGRAMMING
163
8253: PROGRAMMING
164
8253: PROGRAMMING
165
8253: CLOCKING
166
8253: GATING
167
8253: PROGRAMMING
Control word
168
8253: ADDRESSING CONTROL & COUNT REGISTERS
169
8253: STATUS READING
Simple I/O Reading: Required inhibition by clock or gate
170
171
Latching by MODE word and I/O Reading: Required inhibition of clock
172
Read back command
Status byte
173
8253: EXAMPLE 1
Write a subroutine to initialize

counter 2 in mode 0 to generate
25ms delay. Assume the clock
frequency is 2MHz and the
GATE 2 is tied to +5v. Use this
subroutine to generate 1s
interval.
174
8253: EXAMPLE 1
175
8253: EXAMPLE 1
176
8253: EXAMPLE 2
Write a subroutine to generate

1KHz square wave using counter
1. Assume the clock frequency is
2MHz and GATE 1 is tied to +5V
through 10k resistor. Use this
subroutine to generate 1s
interval
177
8253: EXAMPLE 2
In mode 3 the relation between clock frequency to desired frequency
=
×
So, = = 2000 = 07 0 Control Word Format
SQRW: MVI A, 76H ; Control word for mode 3 and counter 1

OUT 83H ; write in the control register
MVI A, D0H ;Low order byte first
OUT 81H ;Load in to counter 1
MVI A, 07H ;Higher order byte 2nd
OUT 81H ;Load in to counter 1 178
HLT
8253: EXAMPLE 3
Write a subroutine to generate

interrupt of 1s using mode 2.
Assume the clock frequency is
2MHz and GATEs tied to +5V
through 10k resistor.
179
8253: EXAMPLE 3
To +5V
1Hz interrupt
2MHz Clock
180
8253: EXAMPLE 3
1
= = 2M = 50000 × 40
0.5 × 10
181
DIRECT MEMORY ACCESS
182
DMA OPERATION
• Direct memory access (DMA) is a process in which an external device takes over the
control of system bus from the CPU.
• DMA used for high-speed data transfer from/to mass storage peripherals, e.g.
Hard disk drive,

Magnetic tape,
CD-ROM, and sometimes video controllers.
Example:
A hard disk transfer rate of 5 M bytes per second, i.e. 1 byte transmission every 200 ns.
To make such data transfer bypassing the CPU is desirable and necessary.
183
DMA ACTION
Memory
CPU DMA
Data – Address - Control
Handshaking
MEMORY-TO-DEVICE DATA TRANSFER
TYPICAL DMA MODULE DIAGRAM
BASIC PROCESS OF DMA
In maximum mode:
Handshaking Pins: The HOLD and HLDA pins  DMA request and acknowledge
Sequences:
1. Peripheral asserts high to HOLD pin
2. CPU completes its current bus cycle and enters into a HOLD state
3. CPU grants the right of bus control by asserting a grant signal via the HLDA pin
4. DMA operation starts
5. Upon completion of the DMA operation, the peripheral asserts low to HOLD pin
again to relinquish bus control.
DMA CONTROLLER: 8237
8237 BLOCK DIAGRAM
8237 BLOCK DIAGRAM
8237A contain three basic block of control logic.
1. Timing and control Block: It generate internal timing and external

control signal to the 8237A.
2. Program command control Block: It decodes various command given

to the 8237 by the microprocessor before servicing a DMA request. It
also decodes the mode control word which is used to select the type
of DMA during the servicing.
3. Internal registers: 8237 contain 344 bits of internal memory in the form
of register
8237 PIN DESCRIPTION
191
192
193
194
195
8237 INTERNAL REGISTERS SPECIFICATION
ADDRESSES
• 0000 = Base and Current Address (Ch0)

• 0001 = Base and Current Word (Ch0)
ADDRESSES
• 1000 = RD Status / WR Command

• 1001 = Request Register
• 1010 = RD Command / WR single Mask bit
• 1011 = Mode Register
• 1100 = Set/ Clear Last F/F
• 1101 = Read Temp Register / Master clear
• 1110 = CLR mode , counter / clear mask
• 1111 = All Masks bit
COMMAND REGISTER
This 8-bit register

controls the operation
of the 8237A. It is
programmed by the
microprocessor in the
Program Condition and
is cleared by Reset or
a Master Clear
instruction.
MODE REGISTER
Each channel has a

6-bit Mode register
associated with it.
When the register is
being written to by
the microprocessor
in the Program
Condition, bits 0 and
1 determine which
channel Mode
register is to be
written.
DATA TRANSFER MODE
1. Single Transfer Mode
• The device programmed to make one transfer only.

• The word count decremented and the address decremented or incremented
following each transfer.
• When the word count ``rolls over'' from zero to FFFFH, a Terminal Count (TC)
will cause an Auto initialize if the channel has been programmed to do so.
2. Block Transfer Mode

• The device is activated by DREQ to continue making transfers during the
service until a TC, caused by word count going to FFFFH, or an external End of
Process (EOP) is encountered.
• DREQ need only be held active until DACK becomes active. Again, an Auto
initialization will occur at the end of the service if the channel has been
programmed for it.
DATA TRANSFER MODE
1. Demand Transfer Mode
• In Demand Transfer mode the device is programmed to continue making

transfers until a TC or external EOP is encountered or until DREQ goes
inactive. Thus transfers may continue until the I/O device has exhausted its
data capacity.
2. Cascade Transfer Mode
• This mode is used to cascade more than one 8237A together for simple system
expansion. The HRQ and HLDA signals from the additional 8237A are
connected to the DREQ and DACK signals of a channel of the initial 8237A.
DATA TRANSFER MODE
Cascade Transfer Mode
REQUEST REGISTER
The 8237A can respond to requests for DMA service which are initiated by software as well
as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request
register. These are non-maskable and subject to prioritization by the Priority Encoder
network
MASK REGISTER
Each channel has associated with it a mask bit which can be set to disable the incoming
DREQ.
STATUS REGISTER
The Status register is available to be read out of the 8237A by the microprocessor. It
contains information about the status of the devices at this point.
OPERATION CODES
SOFTWARE COMMAND
Clear First/Last Flip-Flop: This command must be executed prior to writing or reading new
address or word count information to the 8237A. This initializes the flip-flop to a known state
so that subsequent accesses to register contents by the microprocessor will address upper
and lower bytes in the correct sequence.
Master Clear: This software instruction has the same effect as the hardware Reset. The
Command, Status, Request, Temporary, and Internal First/Last Flip-Flop registers are cleared
and the Mask register is set. The 8237A will enter the Idle cycle.
Clear Mask Register: This command clears the mask bits of all four channels, enabling them
to accept DMA requests.
ADDRESS CODE FOR SOFTWARE COMMAND
ADDRESS REGISTER COMMAND CODE
ADDRESS REGISTER COMMAND CODE
DMA CIRCUIT WITH 8085
PROGRAMMING FOR DMA
1. Disable the DMA controller and begin writing initializations

2. Initialize Channel 3 (CH3) to transfer 1K of bytes from the system
memory to the CD drive assigned to CH3
3. The starting address of the data block is 4075H and subsequent
data bytes have memory address in increasing order.
4. The command parameters should be normal timing, fixed priority,
late write, DREQ, and DACK are both active low.
5. Set up the demand mode whereby the DMA can complete the data
transfer without any interruption.
PROGRAMMING FOR DMA
MVI A, ;Command 0 0 0 0 0 1 0 0
00000100H
Disable DMA
OUT 08H ;Send to Command Reg.
MVI A, ;Command 0 0 0 0 0 1 1 1
00000111H
Demand Incre- Disable Write CH3
Mode ment Auto
Addr. Load
OUT 0BH ; Send to Mode Reg.
MVI A, 75H ; Low-order byte of starting address
OUT 06H ;Output to CH3 Memory Address Reg.
MVI A, 40H ; High-order byte of starting address
OUT 06H ;Output to CH3 Memory Address Reg.
PROGRAMMING FOR DMA
MVI A, FFH ; Low-order byte of the count 03FFH

OUT 07H ;Output to CH3 Count Reg.
MVI A, 03H ; Low-order byte of the count 03FFH
OUT 07H ;Output to CH3 Count Reg.
MVI A, 10000000H ;Command 1 0 0 0 0 0 0 0
DACK Late Fixed Normal DMA Disable

DREQ Write Priority Time Enable Mem.
High to
Mem.
OUT 08H ;Send to Command Reg.

Lecture Slides Post DAC For 8085 Interface

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DEVICE TO DEVICE COMMUNICATION

 Asynchronous: Universal asynchronous receiver/transmitter (UART Standard)

Parallel Communication Serial Communication

 Simplex: Data are transmitted only in one direction Transmitter Receiver

 Duplex: Data are transmitted both directions

1 byte-wide Data 1 byte-wide Data

1 byte-wide Data 1 byte-wide Data

The Transmitter The Receiver

 Baud rate (B bps): Bit rate of the serial port

1. Recognize the beginning of the transmission

 Software controlled asynchronous serial communication

 Hardware controlled asynchronous serial communication

 Output a start bit

 Convert the character to be

 Add error check bit

 Output one or two stop bits

 Serial Input Data (SID)

 Serial Output Data (SOD)

 Recognize start bit (with

 Read the data each data

 Check for errors after last

BACK: RET ; Return to main program

 Data Bus Buffer

Data, Control words, Command words &

Data Buffer TRANSMITTER

Internal Data Bus

Internal Data Bus

Internal Unit/Signal lines Functional Description

Internal Data Bus

Data Buffer Receiver

Internal Unit/Signal lines Functional Description

Baud Rate Factory

Framing Control Parity Control Character Length

Enable Hunt Mode* Data Terminal Ready

DSR SYNDET/BRKDET FE OE PE TxEMPTY RxRDY TxRDY

ANI 01H ;Check TxRDY

Write the code as an assignment to receive

Internal Functional Description Typical Specification

Name Priority Address Branched to (1) Type Trigger

Opcode Operand Hex Code Resart

Priority Type Triggering Resart Add.

 Resolve eight levels of interrupt priorities in a variety of modes.

 Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt

 In service register (ISR)

 Interrupt mask register (IMR)

 The 8259A is programmed by properly initializing:

 The initialization procedure may not need to initialize all of them.

Not required Always

CD H (Hex code of Call instruction)

Lower Byte of Vector Address

Upper Byte of Vector Address

Interrupt Modes Configured by OCWs

Operation Command/Operation Address

 There are two forms of EOI command: Specific and Non-Specific.

 No use of looping in system software; Only configuring

 Interrupts the CPU with precise time delays

 Lower software overhead

 Multiple delays can be easily maintained by assignment

 Non-delay type counter/timer operations are possible

 6 programmable timer modes

 Each counter with 2 inputs (Clock, &

 Variable function assertion on these lines

 16-bit pre-settable down counter