`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:32:57 06/07/2020
// Design Name:
// Module Name: system
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

//BOUNDARY SCAN ARCHITECTURE

module BS_arch (TCK, TMS, TDI, TDO, BSRin, BSRout, CellType);
parameter[6:0] NCELLS = 2; //range 2 to 120
input TCK;
input TMS;
input TDI;
output TDO;

input[1:NCELLS] BSRin;
inout[1:NCELLS] BSRout;
wire[1:NCELLS] BSRout;
wire[1:NCELLS] BSRout_xhd10;
input[1:NCELLS] CellType;

reg[1:3] IR; //instruction register

reg[1:3] IDR;
reg[1:NCELLS] BSR1; //boundary scan cells
reg[1:NCELLS] BSR2;
reg BYPASS; //bypass bit

// TAP Controller State

parameter[3:0] TestLogicReset = 0;
parameter[3:0] RunTest_Idle = 1;
parameter[3:0] SelectDRScan = 2;
parameter[3:0] CaptureDR = 3;
parameter[3:0] ShiftDR = 4;
parameter[3:0] ExitDR = 5;
parameter[3:0] PauseDR = 6;
parameter[3:0] Exit2DR = 7;
parameter[3:0] UpdateDR = 8;
parameter[3:0] SelectIRScan = 9;
parameter[3:0] CaptureIR = 10;
parameter[3:0] ShiftIR = 11;
parameter[3:0] ExitIR = 12;
parameter[3:0] PauseIR = 13;
parameter[3:0] Exit2IR = 14;
parameter[3:0] UpdateIR = 15;
reg[3:0] St;
 assign BSRout = BSRout_xhd10;

always @(TCK)
begin
if(TCK == 1'b1)
begin
case(St)
TestLogicReset:
begin
if(TMS == 1'b0)
St <= RunTest_Idle;
else
St <= TestLogicReset;
end
RunTest_Idle:
begin
if(TMS == 1'b0)
St <= RunTest_Idle;
else
St <= SelectDRScan;
end
SelectDRScan:
begin
if(TMS == 1'b0)
St <= CaptureDR;
else
St <= SelectIRScan;
end
CaptureDR:
begin
if(IDR == 3'b111)
BYPASS <= 1'b0; //EXTEST(input cells capture
pin data)
else if (IDR == 3'b000)
BSR1 <= (~CellType & BSRin) | (CellType & BSR1);
else if (IDR == 3'b001) //SAMPLE/PRELOAD
BSR1 <= BSRin; //all cells capture cell
input data
if (TMS == 1'b0)
St <= ShiftDR;
else
St<= ExitDR;
end
ShiftDR:
begin
if(IDR == 3'b111)
BYPASS <= TDI; //shift data through bypass
register
else
BSR1 <= {TDI, BSR1[1:NCELLS-1]}; //shift data
into BSR
if (TMS == 1'b0)
St <= ShiftDR;
else
St<= ExitDR;
end
ExitDR:
begin
 if(TMS == 1'b0)
St <= PauseDR;
else
St <= UpdateDR;
end
PauseDR:
begin
if(TMS == 1'b0)
St <= PauseDR;
else
St <= Exit2DR;
end
Exit2DR:
begin
if(TMS == 1'b0)
St <= ShiftDR;
else
St <= UpdateDR;
end
UpdateDR:
begin
if (IDR == 3'b000) //ETEST (update output
registers for output crlls)
BSR2 <= (~CellType & BSR1) | (CellType & BSR2);
else if (IDR == 3'b001) //SAMPLE/PRELOAD
BSR2 <= BSR1; // update output registers in
all cells
if (TMS == 1'b0)
St <= RunTest_Idle;
else
St<= SelectDRScan;
end
SelectIRScan:
begin
if (TMS == 1'b0)
St <= CaptureIR;
else
St<= TestLogicReset;
end
CaptureIR:
begin
IR <= 3'b001; // load 3 LSBs of IR with 01
as required by standard
if (TMS == 1'b0)
St <= ShiftIR;
else
St<= ExitIR;
end
ShiftIR:
begin
IR <= {TDI, IR[1:2]}; // shift in instruction
register
if (TMS == 1'b0)
St <= ShiftIR;
else
St<= ExitIR;
end
ExitIR:
begin
 if (TMS == 1'b0)
St <= PauseIR;
else
St<= UpdateIR;
end
PauseIR:
begin
if (TMS == 1'b0)
St <= PauseIR;
else
St<= Exit2IR;
end
Exit2IR:
begin
if (TMS == 1'b0)
St <= ShiftIR;
else
St<= UpdateIR;
end
UpdateIR:
begin
IDR <= IR; // update instruction decoder register
if (TMS == 1'b0)
St <= RunTest_Idle;
else
St<= SelectDRScan;
end
endcase
end
end
assign TDO = (St == ShiftDR & IDR == 3'b111) ? BYPASS : (St == ShiftDR) ?
BSR1[NCELLS] : (St == ShiftIR) ? IR[3] : TDO;
assign BSRout = (St == TestLogicReset | ~(IDR == 3'b000)) ? BSRin : BSR2;
//define cell outputs
endmodule

//BOUNDARY SCAN TESTER

module system();
reg TCK;
reg TMS;
reg TDI;
wire TDO;
wire TDO1;
reg Q0;
reg Q1;
reg CLK1;
wire[1:4] BSR1in;
wire[1:4] BSR1out;
wire[1:4] BSR2in;
wire[1:4] BSR2out;
integer count;
parameter[0:62] TMSpattern =
63'b011000000011100000000011110000000111000000000111000000000111111;
parameter[0:62] TDIpattern =
63'b000001001000000010001000000000000000001000100000000000000000000;
 initial
begin
count = 0;
TCK =0;
CLK1 = 0;
end

BS_arch BS1 (TCK, TMS, TDI, TDO1, BSR1in, BSR1out, 4'b0011);

BS_arch BS2 (TCK, TMS, TDO1, TDO, BS2in, BSR2out, 4'b0011);
//each BSR has two input cells and two output cells
assign BSR1in[1] = BSR2out[4]; //IC1 external connections
assign BSR1in[2] = BSR2out[3];
assign BSR1in[3] = Q1; //IC1 internal logic
assign BSR1in[4] = Q0;

always #7 CLK1 <= ~CLK1; //internal clock

always @(posedge CLK1)

begin
Q0 <= BSR1out[1]; //D flip-flop
Q1 <= BSR1out[2];
end

assign BSR2in[1] = BSR1out[4]; // IC2 external connection

assign BSR2in[2] = BSR1out[3];
assign BSR2in[3] = BSR1out[1] ^ BSR2out[2]; // IC2 internal logic
assign BSR2in[4] = BSR1out[1];

always #5 TCK <= ~TCK; //test clock

always
begin
TMS <= 1'b1;
#70
@(posedge TCK); //run internal logic
begin : xhdl_12
integer i;
for(i=0; i<=62; i=i+1) //run scan test
begin
TMS <= TMSpattern[i];
TDI <= TDIpattern[i];
#0;
count <= i+1; //count triggers listing
output
@(posedge TCK);
end
end
#70; //run internal logic
forever #100000; // wait for manual termination
end
endmodule