Defect Improvement by Optimizing Electroplating in BEOL Sub-50nm Pitch
Shafaat Ahmed, Ketan Shah, Tien-Jen Cheng, Adam da Silva, Mukta Sharma, Teng-Yin Lin, Dinesh Koli, Anbu Selvam KM
Mahalingam, Stephan Grunow, Craig Child
GLOBALFOUNDRIES, 400 Stone Break Road Extension, Malta, NY 12020
Contact: shafaat.ahmed@globalfoundries.com
ABSTRACT
Electroplating for the sub-50 nm pitch back-end-of-line (BEOL)
interconnect metallization has become increasingly challenging
mostly because of marginal seed coverage, inadequate plating
process and/or chemistry, the limitation of scaling the barrier-liner
and seed thickness. In this study we show how inadequate plating
due to the marginal seed caused degraded via open yield along the
perimeter of wafers from the 9:00 to 3:00 o’clock position which we
termed as a “crown”. The analysis of a failed die by transmission
electron microscope (TEM) revealed that a systematic embedded via
void had caused such open yield degradation at the “crown” area.
Plating waveforms were used to mitigate via voids through enhanced
conformal copper nucleation and void free fill. The optimal plating
waveform repeatedly demonstrated virtually equivalent via open
yield between crown and non-crown (remaining area of the wafer)
areas without any yield degradation at crown. We have shown that
the overall via open yield was improved by ~ 25% over the base-line
best known method (BKM).
Keywords— Electrochemical deposition (ECD), Semiconductor,
Dual Damscene, Copper Plating, BEOL, Metallization
INTRODUCTION
Copper was introduced for CMOS interconnect technology by IBM
in 1997[1] as a replacement of aluminum for lower resistivity and
better reliability [2]. Among those many key elements that have
enabled the copper technology; the successful development of void
free dual damascene plating by bottom up copper fill was considered
the key element [3,4]. An electroplating process was chosen for the
copper metallization not only because of it is a low cost, high
efficient and bottom up fill process, but also because the annealed
copper exhibits large grains which ultimately enhanced the reliability
of the copper lines and vias against electromigration and stress
induced migration [5]. As-plated copper films contain very small
grains in which the strain energy of the film acts as a driving force for
the larger copper grain growth during self or high temperature
annealing. Copper metallurgy is affected by the impurities
incorporated from the plating bath. The incorporated impurities
inhibit the grain growth by grain boundary pinning which increases
film resistivity. In advanced semiconductor nodes, due to CD shrink,
a stronger and purer suppressor is required for void free plating with
least impurities incorporation in the film. For recent generation of
technology, it has been proved that not only chemistry but also
process innovation (namely: high bias entry, high current pulse
followed by a fastest entry, e-pulse entry, low current fill or their
combinations) was required to maintain the void free fill by repairing
the incoming poor copper seed at plating.
Plating for the back-end-of-line (BEOL) interconnect
metallization has become increasingly challenging with the scaling of
technology. Especially from sub-50nm pitch interconnect structures
where further scaling of liner and seed thicknesses has resulted in a
978-1-5090-5448-0/17/$31.00 ©2017 IEEE
lack of conformal seed coverage (mostly along the trench or via’s
side walls) that produces embedded voids and very minimal
remaining opening of top CD for the plating without pinch-off. It also
increases plating terminal effect. As such, void free plating becomes
much more challenging and essentially impacts both yield and
reliability of the CMOS interconnect technology. To overcome such
challenges, there are two common approaches that can be taken,
namely, (i) new chemistry formulation with a stronger suppressor,
and/or in combination with optimum accelerator and leveler
concentration, and (ii) plating waveform engineering for better seed
repair through enhanced conformal nucleation and bottom up fill. The
second approach is considered easier to implement in high volume
manufacturing as generally new chemistry evaluation and
qualification is a lengthy process. In addition, as seed thickness is
being scaled down with technology, the waveform becomes essential
to seed repair at plating. In this paper, we demonstrate how plating
waveform engineering can be exploited to eliminate embedded voids
and improve via open yield.
EXPERIMENTAL
300-mm wafers with sub-50 nm pitch test structures were used in
this study. A combination of seeds and plating waveforms were used
in these experiments. The plating waveform consisted of combination
of entry time, entry speed, bias voltage and fill currents. Inline defect
metrology, scans were used to find post-chemical mechanical polish
(CMP) surface defects. The main emphasis was given to find the
metallization related defects; namely hollow metals, line end voids.
Electrical test was carried out for determining the opens yield for both
line and via. A four-point kelvin method was used for Rs
measurement of different ground rule (GR) and sub-GR features. In
this study all incoming processes includes patterning, etch, clean and
copper barrier seed were kept unchanged unless otherwise stated in the
description.
Results and Discussion
Not every void in metal interconnects impacts open yield and/or
health of line (HOL) but almost all voids impact reliability,
specifically the electromigration (EM). It has been seen that pinhole
and slit voids usually caused early EM fail although they do not cause
open yield fail at level test. But such voids indeed caused open yield
degradation when they were tested at upper wiring levels. During the
upper level high temperature cap and dielectrics deposition processes,
voids migration and accumulation caused line or via opens and thus
degraded the open yield. The high density pinhole and slit voids
caused Rs increase of the metal lines and via chains and thus affects
the HOL. Fig.1 shows examples of defects where (a) shows post CMP
line end (LE) voids defects on via chain which would not impact on
open yield as continuous metal interconnects were established for
current run path or electron flow. But it is considered to be a known
concern or potential threat for early EM fail. Fig.1b shows LE and
embedded via voids which both caused metal opens and
disconnections, which will indeed reduce time zero open yield and
lead to EM fail. Fig.1c shows embedded voids on vias chamfer area
and also center embedded voids in single damascene large vias. Both
of these embedded voids showed early EM fail, although HOL or
18 ASMC 2017
open yield was good, as these voids did not interrupt the electron flow
path. So void free metallization is not only a key prerequisite for
reliable interconnect for CMOS technology but also an essential
component for better yield and performance.

Fig.2 Current versus time traces of a typical plating entry

Fig.1 Examples of Line end (LE) and systematic embedded voids
defects and postulated potential impacts on HOL and/or EM
performance.
Copper metallization is facing real challenges upon scaling of the
dimension in advanced nodes; especially sub-50 nm pitch structures,
where after barrier-liner and seed deposition the remaining gap for the
plating fill becomes very limited. In addition, the patterning process
driven fill affects “unfriendly” profiles, for example undercut or
bowing, which also trigger less uniform seed deposition. Conformal
and continuous barrier, liner and seed are pre-requisites for the void
free fill and interconnect reliability. As such, both seed deposition and
plating tools processes have continuously been improved to meet these
challenges.
waveform. Here the regions A, B and C represent the current and
voltage traces from potentiostatic entry, multi-wave pulse and first fill
step respectively.
Fig.3a shows normalized defects density for BKM and DOE
conditions. Here both BKM and DOE conditions had the same seed
but plating entry waveforms were different. The plating DOE
experiment includes entry waveform and fill current different than
BKM plating. It can be seen that the BKM plating on BKM seed gives
very high voids defects density (Fig 2a: BKM split and 2b: wafer
map) versus the new plating on the same seed with newly defined
waveform (Fig.2a: DOE, DOE repeat splits and 2c: wafer stacked
map). The data further support the Automatic Photo Inspections (API)
on pre-defined coordinates of the post chemical mechanical polish
(CMP) wafers surface. The API images on BKM wafers (Fig. 3a, 3c
and 3e ) and on DOE wafers (Fig. 3b, 3d and 3f ) collected from the
exact same coordinate confirmed that plating waveform, for example
optimum high bias entry, can tolerate a fairly poor or marginal seed
and still fill the copper with least or minimum voids. It is clear that
without changing plating chemistry and seed process, a better void
free metallization can still be achieved by utilizing optimized plating
waveform.

The limitation of PVD process for obtaining a truly continuous,

conformal seed in advanced node metallization necessitates process
innovation for seed repairing at plating entry step. The plating entry
waveform has been developed for repairing the marginal PVD seed
through an enhanced nucleation by a potentiostatic entry followed by
multi-wave pulse or Galvano-dynamic ramp during wafer entrance to
the plating bath. Fig.2 shows current vs. time trace of a typical
potentiostatic entry with high current pulse waveform. Here the
regions A, B and C represent the current and voltage traces from
potentiostatic entry, multi-wave pulse and typical fill step respectively.
In addition, the high bias wafer entry helps the prevention of oxidized
seed dissolution during the wafer entrance into acidic copper bath. A
potentiostatic entry followed by a high current pulse helps to achieve
highly dense nucleation where the additives, especially leveler, helps
to get a dense, smooth and conformal nucleation on PVD seed at this
shortest period pulse. The leveler in the plating bath prevents any sort
of 3D-islands growth or rough deposit [6]. In advanced node copper
metallization, entry waveform is being used for poor PVD seed
repairs. In addition, fill currents in combination with entry waveform
and/or bath composition are used for voids free metallization.

Fig 3a: Normalized defect density vs. DOE conditions. 3b and 3c

show the stacked wafer map of BKM and a new plating DOE
respectively.

19 ASMC 2017

Fig. 4(a, c, e) and (b, d, f) show the API /SEM images on BKM and
DOE processed wafers respectively. Images (a, b), (c, d) and (e, f)
were collected from the exact same coordinate on wafers. Plating
waveform was used for fairly poor or marginal PVD seed repaired at
the plating entry.
Fig.5 shows trend line of the die open yield versus tested lot/splits
over the period. Dotted line with arrow indicates the timeframe when
via CD was shrunk to meet the process assumption. We detected that
the via CD shrink had caused via open yield degradation at wafer
crown area. The blue and red lines represent open yield at crown and
non-crown areas of the wafers (shown in the inset). It can clearly be
seen that after the via CD shrink the open yield at crown area was
much degraded. The difference in open yield between the crown and
non-crown areas was not significant prior to these changes. However,
it is clear from the trend line that the open yield in crown area was
marginal and it became worse after the change.
Fig.5 Trend line of the die open yield vs. tested lot/splits over the
period.
Fig. 6a shows an electrical test wafer map of via open yield
degradation (blue dies = 0 yield) at wafer crown where non-crown
areas (yellow dies) show 100% yield. A physical failure analysis
(PFA) was carried out on two separate failed dies (Fig.6b, brown die
x’ & y’) where opens were isolated, FIB marked and then cross-
sectioned for TEM to explore the root cause of via open fails. TEM x-
section images were acquired from two different zero yield dies of x’
20
and y’ (Fig.6b) are shown in Fig.6c & 6d respectively. PFA on
isolated opens revealed embedded voids at open fail via. It thus can be
shown that via open yield fail at wafer crown zone is caused by the
embedded via void and it is a systematic defect.
Void in the via
Fig. 6(a) electrical test wafer map of via yield degradation (blue
die = 0 open yield) at wafer crown area where non-crown area
(yellow) shows 100% yield. TEM cross-section images are shown in
Fig. 6(c) and 6(d) were acquired from failed dies xૼ and yૼ (Fig.6b)
respectively.
Fig.7. Via open yield as a function of plating DOE splits (S1-S5)
versus BKM (S0). Red and blue represent yield on crown and non-
crown area on wafer (inset).
After an unsuccessful set of seed DOE to restore via open
yield at crown area, a plating waveform engineering attempt was
made to repair seeds at plating entry with enhanced nucleation for
better fill. Fig.7 shows via opens yield for plating DOE (design of
experiment) splits where red and blue shows via open yield at crown
and non-crown area on a wafer respectively (shown on inset wafer
map). It can be seen that almost all plating DOE splits improved the
crown area yield versus BKM split (S0). However, the S1 and S2
plating conditions give minimum or no differences in via open yield
degradation between crown and non-crown area. It also can be seen
ASMC 2017
that the overall via open yield improved by 25% compared to the
BKM (S0) process.

The plating DOE not only helped to mitigate the via open yield
degradation at the crown area but also improved overall yield of
different DOE macros. Examples of two different single V0-M1
chains (V0_A and V0_C) open yield by upper extensions are shown
in Fig.8a and 8b respectively. It’s clear that plating DOE splits (S1-
S6) have better average die yield (12-18%) than the BKM S0.
Another example of plating DOE splits in one of the metal lines open
yield is shown in Fig.9, where M2 overall metal lines open yield of
DOE Splits (S1-S6) were improved ~ 50-150% vs. BKM (S0). It is
obvious that the plating DOE helped overall metal fills and thus
improved open yield across the different macros in BEOL. However,
Fig.10 shows kelvin resistance of different colors metal lines-via
(where median Rs values for most of these splits are comparable),
except S5& S6 (showed~20% lower Rs). Similarly Fig.11 shows that
Fig. 9. Normalized M2 metal lines open yield vs. DOE
the V0-CA link resistances of DOE (S1-S6) and BKM (S0) splits are splits.
also comparable.

Fig.10. Normalized Rs (a.u) vs. DOE splits of different

color Kelvin structure for metal lines/via

All embedded or exposed voids are main concerns as these are

Fig.8 Plot of average die yield vs. upper line extension.
It can be clearly seen that the median Rs values of these different
chains Kelvin structure are comparable and within the normal
variation. The significance of plating DOE splits on via open yield at
crown area and other DOE macros open yield are measureable as
compared to its impacts on the Rs macro. It indicates that the Kelvin
Rs structures of different color lines and Vo-CA R/link structures are
most likely not as sensitive as via open yield macro to differentiate
the influences of plating DOE. The impact of voids on Rs, whether
easily measureable or not, probably depends on the density of voids
in the filled metal structures. If the presence of voids caused metal
lines/via opens or reduced the total metal volume in the line/via, then
it would have caused geometric constrains on the electron flow.
Reduced copper volume fraction accounts well for observed increases
in effective Rs with reduced line width. It is therefore clear that an
optimum plating entry with enhanced nucleation indeed is critical for
repairing any marginal PVD seed and to achieving a defect free
metallization for overall die yield improvement.
potential threat for reliability. Voids in metallization could potentially
cause open yield degradation and Rs increase at upper level tests.
Not all voids impact on open yield but almost all voids affect the EM
life time. Pre-existing voids migrate, accumulate and cause line or
via open during the EM stress using high current at elevated
temperature. Fig. 12 shows EM time to fail vs. percentile plot of
BKM (red) and new best plating split (dark blue). The activation
energy Ea = 1 and 1.2 lines are given as a reference. A bimodal
distribution with many early fails (fails at t0 excluded from plot)
were seen in the BKM split (red curve). As BKM shows a bimodal
distribution of fails; therefore t50 and calculated sigma would not be
accurate for BKM EM plot. It is clear that the BKM has many early
fails than the new plating process. Excluding the time zero EM fails
of BKM, the minimum time at which first EM fail occurred in the
plating split was ~ 15x longer than the measureable first EM fail
time of the BKM split. The new plating split does not have any early
fail and the max time to EM fails was > 600 Hrs.

21 ASMC 2017
 Fig. 11. Vo-CA R/link structures for different chains.

Fig.13 EM Failure mode of first two failed die of BKM split where
13(a, b & c) and 13(d, e & f) shows different mode TEM images of
those fails.

Fig.12. Electromigration (EM) percentile plot for BKM (red) and

new go to plating splits (dark blue). The activation energy Ea = 1 and
1.2 lines are given as a references.

The post EM test physical failure analysis of the early fail

site helped to understand the EM failure mode. Fig. 13(a, b & c) and
13(d, e & f) show the physical failure analysis of two separate early
EM fails physical failure analysis of BKM split. Acquired images
from the two early EM fails die of BMK split are shown in Fig. 13(a
& d): TEM bright field, Fig.13 (b & e): high angular annular
diffraction (HAADF) and Fig. 13(c & f): EDX elemental maps. The
fails in both cases occurred in the via region, where the opens
occurred at the line end from via bottom (1st fail; Fig. 13a) or from
the top of the via (2nd fail; Fig. 13d). This was most likely caused by
the migration and accumulation of pre-existence fill voids which
Fig.14. EM Failure mode of first failed die of plating DOE split
ultimately disrupted the electrical continuity. On the other hand, the
where (a) bright field TEM, (b) copper elemental map/ Cu EDXA (c)
PFA on the first fail of the best plating split (dark blue, 1st fail site), is
cobalt elemental map.
shown in Fig 14 (a) bright field TEM, (b) copper elemental map/ Cu
14b) are due to the cobalt which seems to have migrated and
EDXA (c) cobalt elemental map /Co EDXA. The dark spots in
accumulated (see Fig. 14c). It’s clear that the EM fails for optimized
copper map (Fig.

22 ASMC 2017
plating DOE split were not due to the open fail around the via.
However, Fig 14(d) shows the fail mode of this first point EM fail
was due to the line opens at far right from the via region. There are
many factors that could have caused EM fail in BEOL copper
interconnect. Barrier, liner, metal cap, dielectric cap and voids in the
metal fill among them are key factors. Although it is not clear why
such voids have formed in the line far away from the via, however, it
can be postulated that a weaker TaN barrier or lack of conformal
cobalt liner or cap or their combination can cause a copper leak out
during the EM stress test using high current density at elevated
temperature (350C). Once copper started migrating from that region
of metal lines it is obvious that line resistance increases and thus
joule heating might have further accelerated the EM fail.

Conclusion

An optimized plating waveform has recovered marginal seed issue

through its repair at plating by enhanced nucleation and thus has
achieved a void free copper fill. The crown signature of the open
yield degradation on the wafer was eliminated by optimum plating
waveform. It indicates that void issues have been resolved. Improved
EM life time by optimized plating split has further confirmed that the
EM fail was not due to the pre-existing voids and overall fill quality
had been improved. For a marginal or poor PVD seed, plating
waveform engineering with critical plating steps, namely entry, fill
and their combination are indeed needed to acquire a void free
metallization. We have shown that optimum plating process
improved via open yield ~25% and eliminated the degraded yield
signature at the crown area. In addition, this new plating has
significantly improved the reliability (EM) that is critical to enable
the given technology.

ACKNOWLEDGEMENT
Thanks are due to ATD process, integration, characterization and
reliability team members and management for their support during
this work.

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