VHDL is strongly typed and structured.

This makes it somewhat tedious to program but also

makes it robust. There is less likelyhood of misbehaviour. It is better to correct a few syntax
errors during program development than to find the silicon goofing up.

VHDL
Pros:
 Strongly typed language.
 Dealing with signed and unsigned numbers is natural, and there’s less chance of
making a precision mistake or assigning a 16-bit signal to a 4-bit signal.
 Ability to define custom types.
 A VHDL state machine can be coded naturally using the actual state names (e.g.
wait, acknowledge, transmit, receive, etc.), not binary state numbers (e.g. 00, 01, 10, 11).
 Record types.
 Define multiple signals into one type.
 Natural coding style for asynchronous resets.
 Easily reverse bit order of a word.
 Logical statement (like case and if/then) endings are clearly marked.
Cons:
 Extremely verbose coding.
 VHDL modules must be defined by a prototype and declared before they’re used,
causing you to change code in at least 3 places if you want to make a change to the interface.
 The use of the keyword “downto” in every bit vector definition is tedious.
 Sensitivity lists.
 Missing a single signal in the sensitivity list can cause catastrophic differences
between simulation and synthesis.
 Each process must have a sensitivity list that may sometimes be very long.
 Type conversions.
 Signal types that are clearly related (e.g. std_logic and std_logic_vector) cannot
be simply used together and must be converted to another type.

Verilog
Pros:
 Compact language.
 Small code footprint.
 Familiar language conventions similar to C.
 Mixing and matching signals is very easy.
 Reduction operators.
 Perform logical tests on an entire array of bits with a single operator.
 Low-level descriptions closer to actual hardware.
 Instantiate gates directly.
 Explicitly declare wires and registers directly.
 Compiler directives.
Cons:
 Weakly-typed language.
 Code is more error prone due to accidental combination of differing signal types.
 Possible to create signal with a typo.
 No sensitivity lists.
 Less of a chance of design synthesis and simulation problems arising from
coding.
 No support of custom types.
 State machine coding is more difficult because states must be numeric values
with a static bit widths (techniques exist to ease this problem).
 Confusing signal declarations.
 Signal declarations are not always required.
 The difference between a wire and reg is not always obvious for beginners, and a
reg can sometimes be a wire.
 Confusing language conventions for beginners.
 The difference between blocking and non-blocking statements is sometimes
difficult to grasp for beginning FPGA programmers.
 Reduced support for asynchronous signals.
 Using asynchronous signals slows down simulation software.
 Language constructs don’t support natural usage of asynchronous signals.