Spyglass® Known Problems and Solutions: This Document Describes The Following

SpyGlass® Known Problems
and Solutions
This document describes the following:

 SpyGlass Known Problems and Their Solutions
 Licensing
 General
 SpyGlass Command-Line
 VHDL Design Processing
 Verilog Design Processing
 Mixed-Language Design Processing
 Synthesis Engine
 Precompiled Libraries
 SpyGlass Design Constraints (SGDC)
 Atrenta Console
 SpyGlass Tcl Shell Interface
 Waveform Viewer
 SpyGlass Customization
 SpyGlass RTL Modification Engine
 Documentation
 Atrenta Standard Products - Known Problems and Solutions
 General
 SpyGlass audits Solution
 SpyGlass Advanced Lint Solution
 SpyGlass CDC Solution
 SpyGlass Constraints Solution
 SpyGlass DFT Solution
 SpyGlass DFT DSM Solution
SpyGlass® Known Problems and Solutions 1

SpyGlass® Known Problems and Solutions
 SpyGlass DFT MBIST Solution

 SpyGlass lint Solution and SpyGlass OpenMore Solution
 SpyGlass Power Verify Solution
 SpyGlass moreLint Solution
 SpyGlass Power Family
 SpyGlass STARC Solution
 SpyGlass timing Solution
 SpyGlass TXV Solution
Best Regards,
The Atrenta Team
2 4.7.1.2
SpyGlass Known Problems and Their Solutions
SpyGlass Known Problems and Their

Solutions
This section describes the known problems in SpyGlass® and their
suggested solutions, if any.
Licensing
1. FlexLM version mismatch between different tools
Description: If the tools in your working environment use different
versions of FlexLM license server, SpyGlass might report license-related
problems.
Solution: Ensure that you use lmgrd (and any other lmtools) of the
latest version of FlexLM license server available with any of the tools for
license services on that license server.
2. Atrenta® has upgraded to FlexNet Publisher version 11.7 from

Flexera Inc. As per Flexera Inc utilities, such as lmgrd, lmutil for
11.7 version requires the RHEL OS to be LSB certified. Therefore,
user should use RHEL Update2 (or higher version) to run these
utilities successfully.
3. 3-node license server issue

Description: In case of a 3-node license server configuration, if the
current master is killed for any reason, the remaining two nodes select a
new master. However, SpyGlass terminates abnormally.
Solution: Shutdown and restart all license servers before restarting
SpyGlass.
General
1. Line numbers reported are erroneous when the number of lines
exceeds 221 (approximately 2 million).
Description: SpyGlass internally uses 21-bit representation for storing
line numbers of design data from input Verilog/VHDL files. Therefore,
4.7.1.2 3
when a design file has more than 221 lines, line numbers are reported
incorrectly.
Solution: Move a part of the design to other smaller files. For VHDL
files, specify all files in the correct order. For Verilog designs (where this
problem is more likely to happen), include other files in to the primary
file (containing the top-level module) using the 'include directive.
This ensures that SpyGlass command-line or other setup files do not
require any change.
2. Issues with the design save/restore feature

Description: Following are the issues:
 Object names longer than 32K characters are not supported.
 If SpyGlass reports rule violations on VHDL packages or Verilog
include files during design restore, the location reported in the
violation message may be incorrect in some cases.
 This feature is not supported for runs that are supplied with SDC files
containing the define_name_rules and/or change_names
commands. These commands allow design objects to be constrained
in a user-friendly manner and are supported as long as the save/
restore feature is not used.
 In some cases, there may be a difference between the backref
information generated by the save run and restore run.
Solution: Please be aware of this behavior.
3. Some violations may not appear in the single-step map-file run

(where library precompilation and usage are combined).
Description: SpyGlass may not report the following messages in the
single-step map-file run, although it reports these messages in the
normal run (that is, rule-checking from source files) on the same
design:
 CMD_incdir01
 CMD_incdir02
 CMD_define02
Solution: This problem will be fixed in a future SpyGlass release.
4. In case of save-restore in DesignWare, if the user changes the -
4 4.7.1.2
lib SPY_DW_WORK mapping to some other area in the restore

run, restore occurs that should not happen.
Solution: This problem will be fixed in a future release.
5. For some cases, built-in messages are not restored during

precompile/netlist restore.
Description: User can save built-in messages reported during
precompilation by specifying the -dump_precompile_builtin
option. User can restore these messages while using the precompiled
dump by specifying the -hdllibdu option. For encrypted precompiled
design units, messages (if saved) are restored by default unless the
user specifies the -disable_encrypted_hdl_checks option. In
addition, built-in messages reported during netlist save run are saved by
default and can be restored in restore run by specifying the
-enable_save_restore_builtin option.
However, built-in messages are not reported in the restore run in
following cases:
 Built-in messages are not reported for Verilog constructs, such as
`define.
Any construct that is outside a design unit boundary except
comments is not reported.
 Few built-in messages might not be reported on un-synthesized top
modules in the netlist restore run.
In addition, the following may happen:
 SpyGlass may report duplicate WRN_38 messages if the user uses a
precompiled module for which this message was reported in the
dump run and the user enables built-in message restoration in the
use run.
 Few built-in messages reported during synthesis of a parameterized
module might not be reported while restoring netlist for such a
module. This may happen if more than one parameterized
specifications of the module is synthesized.
6. Processing of spyRegisterGroup command

Description: In case of duplicate group registrations by using the
4.7.1.2 5
spyRegisterGroup command, Atrenta Console uses the last found

definition and the batch mode uses the first found definition.
Solution: Avoid duplicate group registrations.
7. Imported waive commands are not displayed in separate section

the in waiver report.
8. SpyGlass does not migrate internal net names (including supply

nets) as a part of hierarchical waiver migration while migrating
block-level waiver file to top-level.
Solution: Specify regexp or wildcard string in case of internal net
names while migrating such waivers at top-level.
9. Some block-level waiver commands that have only port name

and no other hierarchical object name in waiver message are not
imported correctly in SoC.
10. The Inline report is not generated properly when the

compressed netlist is used in the design.
11. Waivers do not work on the enhanced message string of the

SYNTH_5251 and SYNTH_5255 rules
Description: As the message string of the SYNTH_5251 and
SYNTH_5255 rules has changed in the 4.4.0 release, all the previously
applied waivers (prior to 4.4.0 release) on the old version of these
messages will not work for new messages.
Solution: Generally, waivers are not expected on these messages,
because they are synthesis errors. However, if they are present, reapply
waivers on these messages.
12. Waivers specified in a block-level do not work in GUI if the

waiver file is specified with an absolute path in the import
waiver command and the path contains current working
directory.
Solution: Specify the relative path for the file and then run SpyGlass
6 4.7.1.2
again.
13. SpyGlass may crash if your design contains a multiple

concatenation construct, such as {{0{1'b0}}*b, in which
concatenation multiplier is equal to or less than zero.
Description: To check if the crash is due to the above-mentioned
reason, check the stack trace. The stack trace in this case should be
similar to the following:
dfaStaticExprEval ()
getValueExprTempDO ()
dfaUpdatePVA ()
14. In cases where two arguments of a constraint support wildcard

expressions in which the first argument accepts a sub-module
name and the second argument accepts sub-module ports, if the
first wildcard pattern is expanded to multiple module names, the
second wildcard pattern for port is applied only to the first
module in the wildcard expanded module list.
Description: Consider the following constraint specification:
abstract_port -module "bbox*" -ports "a*" -clock ck1
The above wildcard constraint is interpreted as the following:
abstract_port -module bbox -ports a1 a2 a3 ad1 ad2 ad3
-clock ck1
abstract_port -module bbox1 -ports a1 a2 a3 ad1 ad2 ad3

-clock ck1
Ideally, it should have been expanded in the following manner as the
two modules can have different set of ports matching the wildcard
pattern:
abstract_port -module bbox -ports a -clock ck1
abstract_port -module bbox1 -ports a1 a2 a3 ad1 ad2 ad3

-clock ck1
4.7.1.2 7
15. Issue with applying the stop specification on DesignWare

modules
Description: Applying the stop specification (set_option stop
<module-name>) on any DesignWare module does not actually stop
that module and rule-checking is still done for that module.
Solution: User may consider DesignWare modules as black boxes. To
consider them as black boxes, run SpyGlass without specifying the
following command in the project file:
set_option dw yes
16. Issue with applying design constraints on DesignWare modules

Description: User can apply design constraints only on instances of
DesignWare modules by specifying a hierarchical path of the instance.
User cannot specify design constraints on DesignWare modules by using
module names because SpyGlass internally generates elaborated
names, such as DW01_add_width_A_B for such parameterized
modules.
Solution: To apply design constraints on DesignWare modules, use
elaborated names of module instances by performing the following
steps:
a. Run Atrenta Console.
b. Refer to the Module View to know the elaborated names of
DesignWare modules.
c. Specify these elaborated names as design unit names in the design
constraints specification.
17. Issues with width-related rules

Description: Some width-related rules, such as W116, W362,
STARC-2.10.3.2a, STARC-2.10.3.2b, and STARC-2.10.3.2c may report
an incorrect width.
For example, consider the following case of right-shift operation where
there is subtraction with a larger constant value:
module test;
wire [4:0] w1;
wire [4:0] w2;
8 4.7.1.2
assign w1 = (w2 - ((5'b10000 >> 4) - 12));

assign w1 = (w2 - ((5'b1 >> 4) - 12));
endmodule
In the above example, the resultant of ((5'b10000 >> 4) - 12)=-
11 is treated in 2's complement representation in 32 bits. As a result,
the width of expressions, such as w2 - ((5'b10000 >> 4) -12) is
also calculated as 32.
Therefore, RHS width of assignments in this case is incorrectly reported
as 32 bits by the W164 rule.
18. If an array bit select is used in the sensitivity list of an always

construct, SpyGlass reports WRN_901 warnings.
Description: For example, SpyGlass reports such warnings if the
following always construct is used:
module test(in1,clk,out1);
input [3:0] in1;
input [3:0][3:0] clk [3:0];
output reg [3:0] out1 [1:0];
always@(posedge clk[0][0][0])
out1[0]<=in1;
endmodule
Solution: Ignore or waive such warnings.
19. Issues with ignore specifications specified by using the

ignorefile or ignoredu commands
Description: Following are the issues related with ignore specifications:
 If the user specifies an ignore specification by using the
ignorefile or ignoredu commands on modules having generic
parameters, the ErrorAnalyzebbox rule reports such modules as pure
black boxes.
 If the user ignores a file that includes design units that are referred in
another file, SpyGlass may report an STX_* error.
For example, consider the following ignorefile specification in
4.7.1.2 9
which the specified file, file1.vhd, includes an entity and the

architecture of the same entity is defined in another file, file2.vhd:
set_option ignorefile file1.vhd
In this case, the architecture is not ignored and SpyGlass may report
an STX_* error.
20. Issues with the generation of the block dependency report.

 Redundant +incdir, -param, and -y entries are generated in
dependency reports. Therefore, when the user tries to use this
dependency report for subsequent runs, SpyGlass reports the
checkCMD_duplicate03 warning
 It is not recommended to generate dependency reports by using the
set_option gen_block_options <du-name> command for
modules specified by the
set_option v <files> or
set_option y <path> commands. However, if the user still
wants to generate such reports, user must take a note of the
following behavior:
If dependency reports are generated for some block (say du) that is
defined in a file specified by using the set_option v <files> or
set_option y <path> commands, the source file of du gets
dumped with the -v/-y commands in the generated dependency
report, <du>/std_opts.f.
In such cases, when this dependency report is used in fresh SpyGlass
run with du set as the top-level module, SpyGlass reports a fatal
violation indicating that the specified top-level design unit is not
found in the design.
Solution: Provide the file containing definition of du as a source file
(that is, without the v/y option).
21. Issues in ignoring design units from precompilation

Description: SpyGlass does not consider the ignorefile and
10 4.7.1.2
ignoredu specifications if they are specified in a source file that is

passed to the set_option libhdlf <logical-library-name>
"<source-files>" project file command or the -libhdlf classic
batch command.
However, SpyGlass considers the ignorefile and ignoredu
specifications in any of the following cases:
 If they are directly specified in classic batch or project file
 If they are specified in a source file that is different from the file
specified in libhdlf specification
Solution: To ignore design units from precompilation, perform the
following actions:
 Perform precompilation of design files in a separate SpyGlass run
along with the ignorefile and ignoredu commands.
 Use the precompiled dump for further analysis.
SpyGlass Command-Line
1. Two -top command-line option specifications implying the same
architecture
Description: SpyGlass might exhibit unpredictable behavior when two
-top specifications imply the same architecture as in the following
example (that is, architecture <arch> is the most recently analyzed
architecture of entity <entity>):
%> spyglass -top <entity> -top <entity>.<arch> ...
2. Named overloads and single overloads do not work together.

Description: You can either run named overload (by using the
-overload command) or single overload (by using the
-overloadpolicy command) for products (specified explicitly on
command-line or part of a goal) but you cannot run both types of
overloads together.
This is because an overload file to be picked for single overload is
different from an overload file to be picked for named overload. If you
4.7.1.2 11
specify both the -overload and -overloadpolicy commands, a

conflict occurs in determining the overload file to be picked.
3. Issue with the -overloadpolicy command-line option

Description: The -overloadpolicy command-line option does not
work if the overloaded product and the directory containing this product
have the same name.
Solution: Use a different name than the name of the overloaded
product for the directory containing this product.
4. The -param command-line option supports only integer

constants, binary, octal, decimal, and hexadecimal. However,
SpyGlass reports an error if parameters are overridden with a
string value.
Description: For Verilog, you can specify an argument for the -param
option in the following format:
<width>'<base> <value>
Where:
 <width> and <base> are optional.
 <base> can be b (for binary), o (for octal), d (for decimal), or h (for
hexadecimal).
 <value> is a valid number for the specified base.
Description: For VHDL, you can specify an argument for the -param
option in the following format:
<base>#<value>#
Where:
 <base> is optional.
 <base> can be 2 (for binary), 8 (for octal), 10 (for decimal), or 16
(for hexadecimal).
 <value> is a valid number for the specified base.
Solution: Do not override parameters with a string value. This problem
will be fixed in a future release.
12 4.7.1.2
5. If there is a pre-existing .sglib file because of the

-enable_gateslib_autocompile flow, such .sglib file is not
recompiled if the user just changes the -include_opt_data
option in subsequent runs. However, if the .sglib file is
recompiled because of reasons, such as .lib files changed, the -
include_opt_data option is taken into consideration.
VHDL Design Processing

1. SpyGlass reports the STX_VH_202 message when the same
design is compiled twice in a specific sequence of steps.
Description: SpyGlass reports the STX_VH_202 message when the
same design is complied twice in a specific sequence of steps, as shown
in the following example:
1. Package P1
Function F1_FROM_P1
2. Use work.p1.all
Use work.p2.all //Nothing from this package is being
//used in E1
Entity E1
3. Use work.p1.all
Package P2
Constant : MYCONST : unsigned (31 downto 0) :=
F1_FROM_P1(6, 32);
When the user compiles the above code in the first SpyGlass run,
SpyGlass reports the WRN_384 warning for work.p2.all, because it
is not present in work.
NOTE: This warning is actually a syntax error as per LRM and all other industry tools
report an error in this case.
If nothing is being used from the package in a design unit (E1 in this
case), other industry tools report an error. However, SpyGlass compiles
4.7.1.2 13
E1 with a warning.
In the re-entrant flow, when the user compiles the same code again, P1
is compiled freshly and p2 is used from the previous run. Therefore,
SpyGlass reports the STX_VH_202 message to indicate an out of date
situation, because the P2 package uses function from P1 that was
compiled later.
Solution: Clean the WORK directory, and recompile the design.
2. Limitations of memory reduction in VHDL

Description: Memory reduction is a feature in which a memory of M
words of W size is converted into two words of the W size. This is
achieved by specifying the handlememory command.
This feature has the following limitations for VHDL designs:
 Only two-dimensional arrays declared explicitly through TYPE
declarations are processed. Memory handling for a design aborts in
the following cases:
 If any identifier (signal/variable/constant) of three-dimensional or
higher array type is encountered.
 If two-dimensional array TYPE declaration of any identifier in a
design unit is in a precompiled library because precompiled library
is left untouched for memory handling.
 Two-dimensional records are not supported.
 Two-dimensional ports are not supported.
 Functions of precompiled libraries having 2-D argument/return type
are not supported.
3. SpyGlass does not support VHDL’2000 and VHDL'2008.

Description: SpyGlass front-end parser cannot compile VHDL-2000/
2008 code.
Solution: Please be aware of this issue.
Verilog Design Processing
14 4.7.1.2
1. Issues with SystemVerilog support during analysis

Description: Various issues are discussed below.
 The following points discuss cases in which SpyGlass reports false
syntax errors during parsing for unsupported SystemVerilog
constructs.
 No parsing and Object Model support is provided for classes. This
may result in false syntax error, as shown in the following
example:
class Demo;
logic x;
function new (logic x); // false STX_VE_599
this.x = x;
endfunction
endclass
 SpyGlass may report false errors for semantic checks performed
during analysis. For example, SpyGlass may report semantic
errors for unreachable generate-if/else block (dead code in RTL).
Fixing these errors may require moving semantic checks to
post-elaboration stage so that these checks can be performed on
an elaborated design
 If an encrypted IP is used in a design, SpyGlass does not open design
files in the File pane in GUI for the design units present in an
encrypted IP. If the user tries to open such file, SpyGlass reports a
message specifying that the file cannot be opened as it is encrypted.
If the user tries to open the design file corresponding to the
SystemVerilog interfaces or packages, no such message is reported.
Instead, SpyGlass shows the file, if that file exists. However, if the file
does not exist, SpyGlass simply flags a message to indicate that file
is not present.
 Modules containing unsupported SystemVerilog constructs are not
precompiled into the work library. As a result, they are treated as a
black box in the top-level run. Such modules in the design may result
in a difference in normal and precompile flow.
Solution: For all cases in which am unsupported SV construct is lying
within the module body, user can obtain a list of these modules from
the AnalyzeBBox messages in the top-level run, and apply a stop on
them during precompilation. This would ensure that results are
4.7.1.2 15
consistent in the normal and precompile flow. Applying a stop would

direct SpyGlass to just read the interface of the module and
precompile it into the work library. This would avoid the creation of
black boxes during the top-level run.
 SpyGlass allows tagged union expressions to be used as RHS of an
assignment or as an operand of a conditional operator. However, it
does not support tagged union expressions as a part of complex
expressions.
Consider the following example:
assign v1 = tagged valid; //correct
assign v1 = tagged valid + c; //incorrect. Used as part
// of expression
There is no RTL workaround for this issue.
 In certain cases, assignment pattern related checks give false
positives and negatives. For example, variables declared as data
types with implicit dimensions flag false errors when compared with
assignment pattern.
 Use of assignment pattern as lvalue is not supported. For
example,
'{a,b} = {1'b1, 1'b0} //parse error - not supported
There is no RTL workaround for this issue.
 Use of assignment pattern as value of parameter/localparam is not
supported as the value of this expression is not evaluated.
typedef struct { int a, b, c;} mystruct;
parameter mystruct p = '{1,2,3};
…
assign var = p.a;
For the above example, SpyGlass exhibits undesired behavior on
accessing elements such as p.a of the structure, mystruct.
 SpyGlass does not support certain enum methods with arguments.
For example, the following statement is not supported:
enum_var.next(i);
16 4.7.1.2
 Use of enum methods while declaring an enum as part of module

header gives false errors. For example, the following statement flags
an error:
module # (parameter typeenum ep = ep.first());
 Specparam evaluation is not supported. Evaluation of specparams
declared outside the specify block in the module scope is not
supported.
For example:
module test;
specparam s = 1;
...
var1 = s; // rhs evaluation is not supported
If possible, try to replace specparams with localparams.
 Interface parameters cannot be set from the command-line with the
-param switch.
2. Limitations of SystemVerilog support which impact rule-

checking in synthesis
Description: Various issues are discussed below:
 In nested modules if wire/parameter from the top module is used,
then the synthesized netlist may not be correct and an error is
reported.
 Nested interfaces are not supported. SpyGlass flags an error
message if a nested interface, as shown in the following example, is
given and used in the design module:
interface I1;
interface I2;
endinterface
endinterface
module test (I1 a);
endmodule
 Enum handling is not supported in some specific scenarios, as shown
in the following example:
module test;
4.7.1.2 17
typedef enum logic [2:0]

{a=3'b000,b=3'b001,c=3'b010,d=3'bzzz,e=3'b100}
var1;
assign out = d;
endmodule
An error is reported in such cases.
 Alias statements are not supported, as shown in the example:
module test;
typedef byte b;
b b1,b2;
alias b1 = b2;
endmodule
An error is reported in such cases.
In a literal assignment, SystemVerilog aliasing through a typedef is
not supported. An error is reported in such cases.
 Complex expression in asynchronous set/reset, such as structures, is
not supported. An error is reported is such expressions are used.
 Void casting is not supported. An error is reported if void casting is
used.
 Packed union members should have same size, but no error is
flagged when they do not have same size.
 Assignment patterns passed as module ports are not supported for
synthesis in SystemVerilog designs. An error is reported if such
patterns are used.
Solution: Some of these issues will be fixed in a future release.
3. Issues with SystemVerilog support during rule-checking

Description: Various issues are discussed below.
 Issues on nested SV modules
Following are the issues in handling of nested modules:
 For nested SV modules, RTL/LEXICAL rule checking is not done on
sub-modules inside the parent module except for a few rules. In
the given Example, rules such as W175, W154 etc., are not flagged
18 4.7.1.2
on the nested module, bottom. However, very few rules like

STARC-2.8.1.4 are checked on it.
 Few ELABDU-based rules report multiple violations inside the
nested module. For example, the W528 rule is reported twice in the
given Example.
 Waivers based on -du/-ip options do not work for nested
modules. For example, the waive -du bottom command will
not waive anything in the Example. Instead, user should define it
as waive -file_lineblock <filename> <bottom-
start-line> <bottom-end-line> to waive the messages
inside bottom.
Solution: Specify the nested module outside any other module. That
is, make it like the top module, below. An example demonstrating
these issues is as follows:
Example
module top();
wire a, b;
reg Q;
bottom inst(a, b, Q);
module bottom (Q, i_r, D); // nested module: make it
a
//normal module to fix above-mentioned //issues
parameter size = 1; //RTLDULIST:W175
//(Parameter not used)is not flagged
output Q;
input i_r; //LEXICAL: PortComment
//(Port declaration is not commented) is not flagged
input D;
and i1 (c, D, z); //RTLDULIST: W154
// (Declare net 'c/z' explicitly) is not flagged
and i2 (z, i_r, c);
reg Q1;
always @ (i_r) begin
case (i_r) //RTLDULIST: STARC-2.8.1.4
//(Missing default clause) is flagged
1'b0: Q1 = D; //ELABDU: W528
4.7.1.2 19
('Q1' set but not read) is reported twice

endcase
end
endmodule
endmodule
 Issues on SystemVerilog interface objects
There is no rule checking done on SV Interface objects except for
LEXICAL checks (which are also skipped if file contains just interface
objects, and no modules or UDP) and GuideWare rules. For example:
interface Utopia;
parameter int IfWidth = 8;
parameter int IfWidth2 = 8; // The W175 rule
(Parameter
// not used) is not flagged (not a GuideWare rule)
bit clk_in;
bit clk_out;
logic [0:IfWidth-1] data; // The ArrayIndex rule is
// flagged (GuideWare rule)
modport CoreReceive(
input clk_in, data, // LEXICAL: PortComment (Port
// declaration is not commented) is flagged
output clk_out );
endinterface
module utopia1_atm_rx ( Utopia.CoreReceive Rx );

assign Rx.clk_out = Rx.clk_in;
endmodule
 The OneStmtLine rule flags false violation if interfaces are
instantiated with different parameter value, as shown in the following
example:
`timescale 1ns/1ns
interface intf #(parameter width = 32);
//false violation here
bit [width-1:0] baa [4:0];
endinterface : intf
module param2(input bit [3:0] d [1:0], output int q);
20 4.7.1.2
intf #(4) intfinst();

assign intfinst.baa[1:0] = d;
assign q = intfinst.baa[1] + intfinst.baa[0];
endmodule
 Rules working on timescale do not handle SystemVerilog style time
unit and precision. Consider the following example:
timeunit 1ns;
timeprecision 1ns;
module top();
reg x,y,z;
initial
begin
x = 0; z = 0;
y = #5 x + z;
end
endmodule
Now, in the following code, the W701 rule reports a violation as the
include file is not used:
ìnclude "include.h"
module top();
reg x,y,z;
initial
begin
x = 0; z = 0;
y = #5 x + z;
end
endmodule
File: include.h
timeunit 1ns;
timeprecision 1ns;
 In some cases, SpyGlass may not report lexical checks on some
modules. Consider the following example:
File1:
...
module A(); //line number 50
...
4.7.1.2 21
endmodule
...
module B();
...
endmodule //line number 150
File2:
...
... //line number 150
... //only comment. No module definition
module C();
....
endmodule
...
In the above example, SpyGlass may not report lexical checks for the
module, C, if the following conditions hold true:
 There is no module definition in File2 before the module, C, that
is, module, C, is the first module definition in File2.
 Line number corresponding to end line of last module in File1 is
a comment line in
File2
 File1 and File2 are analyzed in a sequence.
Solution: Some of these problems will be fixed in a future release.
4. Verilog2005 and SystemVerilog are not treated separately in

SpyGlass.
Description: By default, SpyGlass supports Verilog2001. To enable
supported Verilog2005 constructs, use the set_option enableSV
yes command in a project file.
Design scenarios where the RTL is valid as per Verilog2005 but uses
SystemVerilog keywords as identifiers result in an STX error irrespective
of if the enableSV command is specified or not. For example,
SpyGlass flags STX errors in the following case:
module m2;
parameter DATA_WIDTH = 8;
22 4.7.1.2
wire [DATA_WIDTH-1:0] d;
wire final;
// final = SV keyword
generate
genvar i;
wire [DATA_WIDTH-1:0] q;
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
// Need name here for Verilog 2001
m0 m0_inst (.p1 (1'b0),
.p2 (d[i])
);
end
endgenerate
assign final = |d;
endmodule
Solution: To avoid STX errors in such cases, the RTL should be modified
either by specifying the name for the generate for block or by
avoiding the use of SV keyword (final in this case) as identifier
(signal names) and using the set_option enableSV yes
command in a project file.
5. SpyGlass does not support the $ construct in the set membership

operator.
Description: In the set membership operator, you can specify a range
with a low bound and a high bound separated by a colon and enclosed
within square braces, as shown below:
[low_bound:high_bound]
Currently, SpyGlass does not support the bound specified by $ to
represent the lowest or highest value for the expression on LHS, as
shown in the following example:
module test;
wire w;
assign w = 4'b1010 inside { [ $ : 4'b1111]};
endmodule
4.7.1.2 23
Solution: Provide the exact bounds of the range instead of the $

construct.
6. SpyGlass has the loop iteration limit of 1048576 for evaluation

of the for loop in constant functions.
Description: Consider the following example:
module top;
parameter P = 2000000;
function integer loop;
input [31:0] number;
begin
for (loop = 0; loop < number ; loop = loop + 1)
begin end
end
endfunction //for
parameter Q = loop(P);
endmodule
In the above example, while evaluating loop(P), the for loop iterates
till the loop iterations are equal to 1048576.
As the fix, a command-line option will be available to the user for
increasing the loop limit.
7. When the user provides an OVL file for a SystemVerilog module

and specifies the set_option sfcu true command in a project
file, SpyGlass may report STX errors.
Mixed-Language Design Processing

1. Working with Large Number of Files
Description: If you are processing a very large number of files, you
may exceed the maximum number of open files allowed by your
Operating System. Then, SpyGlass will produce Unable to Open File
messages.
24 4.7.1.2
Solution: Change the maximum number of open files allowed using the
limit (csh) or ulimit (sh and derived shells) built-in commands.
2. Issues while working with libraries in mixed-language designs

Description: Working with libraries in mixed-language designs has the
following limitations:
 VHDL design units instantiated in a Verilog module cannot have
unconnected terminals in the port mapping.
 In some designs, there can be multiple reporting of same synthesis
and elaboration errors.
 Syntax errors are suppressed during synthesis of a mixed-language
design with 'define macro declaration of the following type:
'define macro(A,B,C) A|B|C
Synthesis Engine
1. Language applicable for built-in rules
Description: The applicable language for some synthesis built-in rules
is mentioned as Verilog+VHDL in the rules spreadsheet shipped with this
release, while these rules may only be applicable for one of the
languages. For example, the SYNTH_5132 and SYNTH_5133 rules are
actually applicable for Verilog only.
Solution: Please ignore the language specification as it has no impact
on the functionality.
2. Discrepancy in violation messages between elaborator and VHDL

flow
Description: If two configurations are specified for a top-level design
unit and one of the configurations has been specified through the -top
option, the other configuration should not be used. However, if the
configuration that should not be used contains binding that does not
exist, STX errors are reported while running SpyGlass in VHDL mode.
Solution: Run SpyGlass in mixed mode. This behavior is in accord with
other tools.
4.7.1.2 25
3. False SYNTH_1038 messages in designs

Description: For non-synthesizable types, such as access type, file
type, and physical type, the SYNTH_1038 rule violations are reported on
declaration of these types, even if these types have not really been used
in the code.
Solution: Specify pragmas surrounding such usage.
For example, consider the following code:
use std.textio.all;
entity ent is
end entity;
architecture rtl of ent is
function conv_string( i:integer) return string is variable l:
line; begin write(l,i);
end conv_string;
begin
end architecture;
To fix the violation in the above code, enclose the conv_string
function definition within the translate_off and translate_on
pragmas.
4. Synthesis messages reported during synthesis process

Description: If a library contains cells with more than eight inputs,
these cells are ignored for technology mapping and the following
message appears on the screen out:
Nodes with more than 8 fanins will node be processed.
5. Less optimization achieved by propagating constants

Description: In SpyGlass-generated netlist, all non-blocking types of
user nets are preserved. This is done to preserve a strong correlation
between the input RTL and synthesized netlist. It allows rules/products
to find issues that may result in problems during chip generation.
Since SpyGlass preserves non-blocking type of user nets, this result in a
limitation in the amount of optimization that can be achieved by
propagating constants, as constants are usually not propagated
completely in several cases.
26 4.7.1.2
As a result, the netlist generated from standard synthesis tools may be

different from the input RTL. However, functionally they are same.
Such differences enable users to find maximum issues in the RTL.
Precompiled Libraries
1. Limitations of state-table and bus-keeper support
Description: SpyGlass supports state-tables and bus-keepers while
precompiling gate libraries with the following known limitations:
 Cells with state-table along with bus/bundle pins are not translated.
 SR Latches are not translated.
 Bus-holder cells with enable pins are not translated.
2. Peak memory increases while running a precompiled design with

the set_option hdllibdu yes project file command
Description: By default, SpyGlass enables the lexical rule-checking on
precompiled design units when the set_option hdllibdu yes
project file command is specified. This can result in an increased peak
memory.
Solution: If the increase in peak memory is significant resulting in an
out-of-memory situation, use the set_option
disable_hdllibdu_lexical_checks yes project file command
while running precompiled design units. This will disable lexical
rule-checking on precompiled design units by default.
SpyGlass Design Constraints (SGDC)

1. Issues in the waive constraint
Description: Please note the following issues with the waive constraint:
 Atrenta Console does not support the list of pairs/tuples specified
with the -file_line/-file_lineblock arguments respectively
4.7.1.2 27
as is supported in the batch mode. You need to use multiple -

file_line/-file_lineblock arguments, each with one value.
 The deprecated -script command-line option does not work with
the waive constraint unless the following line is added to the script:
require "reports.pl";
Solution: These problems will be fixed in a future release.
2. Issues with test_mode constraint

Description: The SGDC_testmode03 built-in rule has the following
issues:
 The SGDC_testmode03 built-in rule does not flag conflicting arguments
(-capture and -invertInCapture) when the test mode signal
names cannot be unambiguously determined.
The SGDC_testmode03 rule currently does not flag the following
example where nets n1 and test.n1 are same:
current_design test
test_mode -name test.n1 -value 0 -capture
test_mode -name n1 -value 0 -invertInCapture
 (Verilog only) The SGDC_testmode03 built-in rule flags when the test
mode net names are same except for the case as in the following
example:
current_design test
test_mode -name ABCD -value 1 -capture
test_mode -name abcd -value 0 -invertInCapture
Please note that signals ABCD and abcd are different signals in
Verilog context and hence the above example is not a case of
conflicting arguments.
3. Issues with hierarchical migration of block-level SGDC files to

the chip-level
 Currently, hierarchical migration is not supported for multi-top
designs.
28 4.7.1.2
 Nested SGDC commands are not supported. For example, in the

following specification, the top.sgdc (chip-level SGDC file) contains the
sgdc specification for a block-level module block. Further, the
block.sgdc (block-level SGDC file) contains the sgdc specification for
a sub-block module subblock. This specification for the sub-block
will not be processed.
--- top.sgdc ---
sgdc -import block block.sgdc
--- block.sgdc ---
sgdc -import subblock subblock.sgdc
 For VHDL designs, the block name specification in the top-level
design using the sgdc SGDC command, should be identical to the
block name specification in the corresponding block-level SGDC file
using the current_design command. For example,
<top.sgdc>
...
sgdc -import blk_ent.blk_arch blk.sgdc
<blk.sgdc>
current_design blk_ent.blk_arch
...
OR
<top.sgdc>
...
sgdc -import blk_ent blk.sgdc
<blk.sgdc>
current_design blk_ent
...

 If a multi-dimensional signal is specified as value in an SGDC
command with the top-name prefixed in the hierarchical name of the
signal, then the migrated name generated is incorrect. For example,
4.7.1.2 29
<blk.sgdc>
current_design blk
testpoint -name blk.mid_inst.data -type observe
...
Where, data is a multi-dimensional signal. Here, the incorrectly

generated output command will be:
testpoint -name top.blk_inst.blk.mid_inst.data
-type observe
Solution: Block-level top name should not be prefixed to the multi-
dimensional signal name in the block-level SGDC file as shown below:
<blk.sgdc>
current_design blk
testpoint -name mid_inst.data -type observe
4. Issues with migration of waiver messages from custom products

 Conversion fails if the message specified in waive command is a
regular expression.
 Conversion fails if the message specified in waive command is a
substring of the complete message.
 Conversion fails if a variable number of arguments have changed in a
message.
 Conversion fails if wildcard is used in message specified in waive
command.
 Conversion is done incorrectly if the order of variable arguments
changes in the message across releases.
 For custom products, waiver messages compatible with the current
release cannot be generated from previous release by using the
-gen_compat_waiver command-line switch.
NOTE: For examples of the above-mentioned limitations, refer to the application
note, Generating Compatible Waivers.
30 4.7.1.2
5. Issues with SGDC existence checks

 Existence check fails on SGDC commands that refer to the nets
generated due to integer variables in VHDL.
Existence checks are sanity checks on hierarchical objects specified
with various constraint fields. These sanity checks validate existence
of objects specified with the constraint fields.
Solution: This problem can be resolved by using SGDC files containing
such commands in restore mode of NOM save-restore flow.
 Wildcard support is not present for record nets.
6. Issues with global scoping in SGDC

Description: Translation from block-level to top-level does not work in
cdc_false_path if a wildcard is specified for a hierarchical object
(instance, internal net, and internal terminal).
7. Issues with local scoping in SGDC

Description: Entity name in e:: notation is case sensitive.
8. Issues with local and global scoping in SGDC

 Scoping does not work if the top name is an escaped name.
 Scoping does not work properly in multi-top designs.
9. Issues with names generated after unification with respect to

define_name_rules/change_names
Description: When you change the name of an object by using the
change_names command (in the context of define_name_rules
command) and there is a conflict in the namespace, SpyGlass might not
perform unification in the same way as it is done by various other
industry tools.
Consider the following example in which there are three instances of
tff:
module top(out,clk,reset,enb);
4.7.1.2 31
input clk,reset,enb;
output [2:0]out;
wire dc,dd,e;
tff tflipflop1(dc,clk,reset);
tff tflipflop2(dd,out[0],reset);
tff tflipflop3(e,out[1],reset);
endmodule
Now, consider that you apply the following constraints on naming:
define_name_rules simple -allowed "A-Z0-9_" -max_length 5
-type cell
change_names -rules simple -hierarchy
The above constraints specify that the cell instance names cannot
exceed the length of five characters, and all the names are changed to
uppercase (since a-z is not allowed). Hence, all the names get
truncated to TFLIP for all the three cells, tflipflop1,
tflipflop2, and tflipflop3.
In this example, unification comes into picture, and some industry tools
maintain the length of five characters and change the names to TFL_1,
TFL_2, and TFL_3. Hence, if the constraint file refers to the design
objects anywhere with the names, TFL_1, TFL_2, and TFL_3, they
can be found.
However, SpyGlass in this case generates the names, TFLIP, TFLIP0,
and TFLIP1, after unification. These names are different from the ones
that are generated by other industry tools, and do not respect the value
specified in the -max_length option.
Some industry tools change the hierarchical pin names but not the
hierarchical net names. However, SpyGlass changes both.
Solution: Change the SDC file for names that are compliant to SpyGlass
synthesis output.
Atrenta Console
1. After SpyGlass run, when the HDL and the Results area is
displayed during the Goal Setup stage, if the pane divider that
separates these two areas is pulled to the top, the pane divider
32 4.7.1.2
disappears.
Solution: Pull the pane divider in the downward direction to position it a
little above the session log. This prevents the pane divider from
disappearing.
2. When you open the 'Methodology Configuration System' in the

'VHDL' or 'Verilog' mode, in some cases, a pop-up of invalid
entries appears for those methodologies that do not have the
current language specific goal(s). For example, if a methodology
does not contain any goal of 'VHDL' language and you try to open
that methodology from the 'Methodology Configuration System',
you will get an invalid entries pop-up because 'VHDL' specific
goals are not present in that methodology.
3. If the user sets a methodology in Atrenta Console and if the

methodology directory does not contain the order file, the
aggregated reports fail to decipher the executed goal list from
the project. In this case, the results are not considered in the
aggregated report creation (either datasheet report, project_summary,
or dashboard report), and the report may be empty or incomplete.
4. SpyGlass GUI crashes when run through the RTDA-NC load-

sharing environment.
Description: The crash occurs because the RTDA-NC tool overrides the
SIGTERM signal handler, which prevents the custom signal handler of
SpyGlass from being invoked.
Solution: Set the SG_DEFAULT_SIGTERM environment, as shown
below, and then load the GUI.
setenv SG_DEFAULT_SIGTERM 1
5. In the Classic mode, Atrenta Console is unable to load messages

with very large number of objects in the Incremental Schematic
Window
Description: When you try to view the hierarchical view of a message
with very large number of objects (instances, nets, and ports) in the
Incremental Schematic Window, Atrenta Console may hang or exit due
to insufficient memory.
4.7.1.2 33
Solution: Such messages are normally expected to be viewed as

auxiliary messages. Therefore, you should be selecting a related
message first and then selecting this heavy message as its auxiliary
message in the Selective-Display mode. However, if you require the
heavy message to be the main message, then it is recommended that
you view this message in the Complete-Display mode keeping the
Incremental Schematic Window closed.
6. Issues with SpyGlass Results Analyzer (SGRA)

Description: Please note the following:
 SGRA is slow while loading big report pages.
 There is refresh problem related to de-selection of text in tables.
 The images in the Rule Help files are not shown.
7. Discrepancy in the generated waiver report in batch mode and

GUI if the waiver file contains any waive command specifying
multiple or a combination of the following commands:
-file, -file_line, -file_lineblock
8. Issues in parallel goal run in Atrenta Console and sg_shell

Following are the issues with parallel goal run in Atrenta Console and
sg_shell:
 If the login type in the specified parallel file is lsf, user cannot
specify the
-I option of bsub command in the LSF_CMD keyword.
Solution: Do not specify the -I option of bsub command in the
LSF_CMD keyword.
 Parallel goal run is not supported in DEF mode.
 Disk latency issue in parallel goal run
For some goals, SpyGlass may report the following status indicating
an unsuccessful run even if they were run successfully:
run_goal: info: <goal_name>: Goal run failed or could
not read status code from file <status_file_name> ...,
please see <goal_wdir>/spyglass.log and <goal_wdir>/
34 4.7.1.2
run_parallel_goal.out for details
For such goals, run results and reports are generated but run results
are not updated in the project. You can view results for these goals
by directly opening moresimple.rpt from the following results location:
<goal_wdir>/spyglass_reports/moresimple.rpt
Here, <goal_wdir> is same as that reported in the information

message above.
This issue occurs due to disk latency issue across the server on which
goal was run and the server on which you are running sg_shell.
Once a goal run completes, the goal run status and results are
written to the files present in <goal_wdir> directory. These files are
then read by parent sg_shell process that fired parallel runs.
In some cases, when the server on which the goal was fired is out of
sync for more than 20 seconds with respect to the server on which
the parent sg_shell process was running, the parent process fails
to read these files and does not update run results in the project
even though the process running child goal has finished successfully.
Solution: This issue will be fixed in a future when instead of a disk
based data communication, some IPC-based communication mechanism
would be used to update results in the parent sg_shell process, once
the child goal run has completed.
9. If a user creates setups for some goals individually and then

selects them for group run, a consolidated setup of goals is not
shown at the setup stage. User should modify them manually for
group run.
10. While generating aggregated reports, Atrenta Console may not

find input files and report an error.
Description: While generating aggregated reports, Atrenta Console
searches for input files under the relative path of the directory specified
by the set_option projectcwd <dir> command. However, if this
command is not specified in a project file, Atrenta Console searches for
4.7.1.2 35
input files under the directory containing the project file and then in the
user current working directory.
For example, consider the project file /usr/test-cases/design1/sample.prj with
the following contents:
# sample.prj
set_option projectcwd /usr/test-cases/test1
set source_file_list "sources.f"
source "./lib_precompile.f"
…
While generating reports for the above example, Atrenta Console
searches for the sources.f and lib_precompile.f files in the /usr/test-cases/test1
directory. However, if the projectcwd option is not specified in this
project file, Atrenta Console searches for these file under the /usr/test-
cases/design1 directory and then in the user current working directory.
Solution: Use the set_option projectcwd <dir> command in a
project file to specify the directory containing input files to be
considered for report generation.
11. GUI hangs if the animation interval of the image depicting the
GUI load process is less.
Description: An animation interval of the image specifies the time (in
ms) after which a refresh should occur.
If this interval is less, the refresh operation does not complete and GUI
hangs. This issue has been observed on few X-Servers on Windows.
Solution: Specify a different interval by using the
CONSOLE_ANIMATION_TIME environment variable, as shown in the
following example:
setenv CONSOLE_ANIMATION_TIME 200
This example is valid for csh only.
The default time interval is 300 ms and the minimum time interval is
100 ms. If you specify any invalid value, that is a value less than 100,
the default value is considered.
12. Help for options under the Set Read Options tab is currently not
36 4.7.1.2
visible.
13. Issues in Audit reports generation in GUI

Description: If a user does not specify the set_option report
Audit command in a project file and try to open any of the Audit report
(Audit, Audit-RTL or Audit struct) in GUI, the tool does not perform any
action.
However, if the user again tries to generate the Audit report, the tool
prompts the user to re-generate or open the report.
Solution: Specify the set_option report Audit command in the
project file or specify -report=Audit command in classic batch.
14. Ctrl+F1 key combination does not open the Shortcut Keys
window on KDE because KDE uses the Ctrl+F1 key combination
to switch between desktops. The shortcut key combination
however works on GNOME.
15. The Waveform Viewer window may hang while opening, if

localhost is not set properly.
Solution: To debug this problem, check if the standalone syncad
application is working fine on your machine. This application is present
at the following path:
$SPYGLASS_HOME/../waveform/Linux2/syncad/bin/syncad
If the syncad application is working fine, check if localhost is set
properly.
16. Issues while running Atrenta Console as a background process

on the Solaris platform
Description: While running Atrenta Console as a background process
on the Solaris platform, it hangs and does not open up. This occurs only
if you have set "stty erase ^H" in your shell startup file (.cshrc or
similar).
Solution: Either remove "stty erase ^H" from the startup file or
run Atrenta Console in the foreground.
4.7.1.2 37
17. Shortcut keys when invoked by using the left-most <Alt> key
on the keyboard does not work as expected in the exceed
environment.
Description: In the exceed environment, when the user presses the
left-most <Alt> key on the keyboard, this environment is unable to
register any event triggered. This is because the windows OS running
behind consumes this key by default. Therefore, all the shortcut keys
when invoked by using the left-most <Alt> key do not work as
expected.
Solution: Configure the left-most <Alt> key manually in the exceed
environment by performing the following steps:
a. Open the Xconfig file in the Xconfig Manager.
Under the Input tab, the Windows Modifier Behavior setting is
present.
b. Set the ALT Key option as "To X" instead of "Left To Windows, Right
To X" (default setting).
18. Red Hat Linux GNOME/sawfish window manager

Description: The Stop button in GUI sometimes does not work properly
when using Red Hat Linux GNOME/Sawfish window manager and Red
Hat Enterprise Linux WS release 4 (Nahant).
Solution: Use KDE.
19. Atrenta Console uses current versions of products with older

VDBs
Description: Atrenta Console rule descriptions and help messages are
based on the product files of the current release. When an older VDB is
opened, the messages and help may not correspond to the run that
created the release.
Solution: Opening old VDBs is provided to ease transition between
versions of SpyGlass. However, Atrenta recommends re-running the
design with the latest products.
20. In the Classic mode, Atrenta Console is unable to load flattened

blocks with very large number of objects (that is, around 15000
objects) in the main schematic window
Description: When you try to view a flattened design unit with very
large number of objects (instances, nets, and ports) in the main
38 4.7.1.2
schematic window, a warning is displayed and the schematic window is

closed automatically. Please note that this issue relates to flattened
design unit size and is not related to the overall design size.
Solution: Set the value of the
AUTOENABLE_HUGE_SCHEMATIC_DISPLAY configuration key to
yes.
Once changed to yes, a warning is still displayed but the user can
continue the action that may result in a long wait, hanging of Atrenta
Console, or out of memory situation. This would depend on design size
and available memory on the system.
21. Schematic is unable to load violations, such as

Info_CaseAnalysis which are primarily used to superimpose
debug data on other rules
Description: Rules, such as Info_CaseAnalysis produce huge amount of
annotation on schematic. Violations of such rules in most designs cannot
be loaded in the Incremental Schematic window.
Solution: Load any violation that user intends to debug. Then apply
case analysis data by using the Edit menu or using the Ctrl+A key
combination. In addition, turn on the Selective Display mode option
during this operation.
22. Issues with Multi-dimensional array support

Description: Schematic windows show the multi-dimensional array bit
name in a single bit format. The index shown is the index of the bit in a
flattened array with only single dimension. For example, if the bus was
declared as input[7:0][7:0], the bit input[3][3] is shown as
input[27].
Solution: Right-click on the bit to view the actual bit name in the
context menu. You can also view the tool-tip to see correct values.
23. Issues with spreadsheets

Description: The spreadsheet window is not refreshed in some cases.
When you move the mouse cursor over a message, the message text
temporarily disappears.
Solution: Scroll up or down the spreadsheet to fix the problem.
4.7.1.2 39
24. SGDC to schematic cross probing is not be possible for port

design objects
Description: Cross probing from SGDC to schematic is not possible for
port design objects when the current design is specified as
entity.architecture in the SGDC file.
25. Some partly commented lines in SGDC files are shown as fully
commented
Description: Lines in SGDC files containing current_design,
setvar, or set_hsep statements are shown as fully commented even
if they are partly commented.
Solution: The problem will get resolved in a future SpyGlass release.
26. If SpyGlass is invoked on a 64 bit Sun machine, then the Save

As menu option in MS/IS does not provide an option to save the
file in .png format.
27. Some constraints not generated properly in the Constraints

Editor window
Description: In the Constraints Editor window, the constraints
applicable to modules and nets are generated correctly. However, the
constraints that are applicable on instances are not generated correctly.
Solution: Modify such constraints manually as per your requirement.
28. The new Waveform Viewer version introduced in the SpyGlass

4.7.0 release crashes in some cases.
Solution: Post SpyGlass 4.7.0, both the old and the new Waveform
Viewer versions are shipped with a release. If the newer version
crashes, switch to the old Waveform Viewer version by setting the
following environment variable:
setenv SPYGLASS_USE_WAVEFORM2 yes
29. Editable fields in GUI appear disabled in some cases.

Description: The fields accepting user input, such as a top-level
module under the Set Read Options tab and a project file name while
saving a project appear disabled.
40 4.7.1.2
Solution: Change the input editor of the operating system you are
using.
30. Fatal messages getting waived in GUI.

Description: Fatal messages get waived in the following cases:
 When you select the message in the Msg Tree page and press
<Ctrl>+D.
 When you create a waiver file to waive such messages.
Fatal messages should never get waived.
31. Incorrect count of flip-flops and latches in the tooltip of the

Design link.
Description: After the goal run, when you place the cursor on the
Design link in the GUI, the tooltip of that link shows the count of
flip-flops and latches as zero.
However, when you click on the Design link, the Design Information
dialog appears that shows the correct count of flip-flops and latches.
Moreover, when you rerun SpyGlass on the same design, the tooltip
shows the correct count.
32. GUI crashes on loading incomplete runs.

Description: If the SpyGlass run terminates in between due to memory
failure or user interrupt, the generated SpyGlass results remain
incomplete. In such cases, if you try to load the incomplete results in
GUI, a crash occurs.
Solution: Error handling for such scenarios will be added in a future
SpyGlass release.
33. Unsaved changes in the Waiver Editor window

Description: While using the Waiver Editor window to waive messages,
if you do not specify a waiver file to save the changes, SpyGlass
temporarily stores the changes in a default waiver file.
However, if you close the GUI or run a goal without saving the default
waiver file, SpyGlass does not prompts you to save the changes. As a
result, all the changes are lost.
4.7.1.2 41
Description: Save the default waiver file before closing the Waiver
Editor window.
This problem will be fixed in a future SpyGlass release.
SpyGlass Tcl Shell Interface

1. If SpyGlass Dashboard report generated using a project is executed
through sg_shell (TCL flow), the report shows the goal run
status as Running even after the goal run is completed.
2. The help -report command does not display some product

specific reports unless the goal is being currently run.
Description: Some of the product specific reports become visible on
issuing the help -report command only after the goal has been
currently run. Therefore, if you switch to a previously run goal, then
even though these reports are available, you may not find them listed
by using the help -report command.
Solution: Re-run the goal after switching to it to get a complete active
reports list.
3. Issues with waive command

Description: Following are the issues with the waive command:
 Waiver commands having -import argument are applied when the
user is actually running a goal. If such waiver commands are
specified after the run_goal command, these waiver commands
are applied only during the consequent run_goal command.
Therefore, if your standard/custom reports contain messages which
you want to waive by using the -import command, re-run the goal
and then generate these reports.
 User cannot edit or remove import-related commands in a block-level
or a top-level file.
 Consider the following command.
waive -import <block-name> <block-file>
42 4.7.1.2
In the above command, user can specify the block file

<block-file> only in a non-Tcl format.
-file_line and -file_lineblock arguments of the

4. The
waive command do not support multiple files.
5. Ctrl-Z not supported in Tcl shell

Description: If you are on sg_shell prompt, and you open a file
using vim as shown below:
sg_shell> vim output.log
In the above case, you are working in vim and if you press CTRL-Z, this
will suspend the vim session as well as the sg_shell session, and you will
return to your native shell (tcsh etc.).
However, when you do an "fg" or "%" to resume the suspended job,
then it should take you to the vim session (or at least to the sg_shell
session). In this case, there is some known issue and it does not allow
you to type anything on the shell, or if you are able to type in something
then that command will not be honored.
Solution: It is recommended to start UNIX shell from within sg_shell
by typing tcsh or sh etc. (depending on the shell you want to start), and
then exit this UNIX shell whenever you want to return to sg_shell.
6. Custom reports do not work directly for goals run from Atrenta
Console.
Description: There is a separate message database created in
sg_shell that helps you to query message database. This database is
not generated by default in the Atrenta Console runs. Therefore, if you
want to use sg_shell and Atrenta Console UI/BATCH together and
generate custom reports, please set following environment variable
before invoking Atrenta Console UI/BATCH:
% setenv SPYGLASS_SMDB_SUPP 1
This would create the necessary message database so that you can re-
use the run results from Atrenta Console inside the sg_shell.
4.7.1.2 43
Solution: Either set the specified environment variable prior to Atrenta

Console invocation, or re-run goals inside sg_shell prior to custom
report generation.
7. Tab completion does not work if space is first character

Description: sg_shell supports tab completion that lets you choose
from the displayed list as you are typing the partial string. However, this
feature does not work if space is the first character on sg_shell
prompt.
8. Tcl shell re-direction operators, > and >>, are not supported for
Tcl built-in commands or procedures.
Description: Tcl shell re-direction operator, >, is not supported for Tcl
built-in commands or procedures. However, this is supported for Tcl shell
commands listed by using the help command. Further, UNIX shell re-
direction operator, >>, is not supported for append operation in Tcl shell.
Use the capture -append Tcl command to implement the append
operation.
9. DDR goal not supported in Tcl shell

Description: If there is a goal referring to multiple designs in a single
run where one is a reference design and other is the implementation
design, such goals are not supported in Tcl shell currently.
10. Error messages on old project files have new command names
only
Description: Some of the command names in project files have
changed in SpyGlass 4.3.0 release. Project files generated from
SpyGlass 4.2.0 or SpyGlass4.2.1 are still supported, but if there is any
error in these older project files, the error messages would show the
name of the new command names only.
Solution: Use the new command names only. Further, if there are any
old project files, open them in sg_shell, and save back to get
updated project files with new command names.
44 4.7.1.2
11. Wildcard support is not present for the read_file and

remove_file commands
Description: Currently, wildcard is not supported for the read_file
and remove_file commands. Therefore, you should provide the
expanded list in these commands.
Solution: You can use Tcl glob function to expand the wildcard as
follows:
sg_shell> set temp [glob *.v]
sg_shell> read_file -type verilog $temp # read all *.v
files
12. Help for rules, parameter, and SGDC commands is not available
without goal selection
Description: There is the help command available in sg_shell to
view the help for commands, methodology, goal, rules, options,
parameters, SGDC, and reports. You can get help for rules, parameters,
and SGDC only after a goal has been selected. These objects are not
available outside of goal scope.
13. Error message during capture would come in the captured file
and not on the screen
Description: The capture command can be used to re-direct output
of some other command to the specified file. If there are any errors
reported during execution of that command, those error messages are
also captured in the specified file and are not displayed on the screen.
For example, consider that an error has been reported during the
execution of the write_report <rpt_name> command as part of
following command:
sg_shell> capture my.rpt {write_report <rpt_name>}
In this case, the error is captured in the my.rpt file itself.
14. Hierarchical SGDC migration flow is not supported inside Tcl
4.7.1.2 45
shell
Description: Options gen_hiersgdc and validate_hiersgdc
are not supported.
Solution: In classic batch, perform SGDC migration using the
gen_hiersgdc and validate_hiersgdc options. Then, use these
migrated SGDC files inside Tcl shell.
15. Boolean options set using set_option not unset in goal scope
with set_goal_option
Description: If there is a Boolean option set in global scope for all goals
using set_option, it cannot be unset in goal scope using
set_goal_option. For example, consider the following.
sg_shell> set_option ignorelibs yes
sg_shell> current_goal initial_rtl/lint/synthesis
sg_shell> set_goal_option ignorelibs no
sg_shell> run_goal
In the above case, even if ignorelibs is being set to no inside goal
scope, it would still be treated as yes during run_goal. This problem
is there with only Boolean options.
Solution: It is currently recommended that if a specific Boolean option
is intended to be turned on/off on per goal basis, then set it inside goal
scope only, and not have it set globally using set_option.
16. Line number in violation messages for all ADC and AWL
commands is reported as 0.
17. User cannot selectively remove a project-level SGDC/ADC file

from specific goals.
User can remove a project-level SGDC/ADC file from outside the scope
of any goal, but it would be removed from all goals. However, user can
remove a goal-level SGDC/ADC file from within that goal scope. This is
explained in the following example:
current_methodology $SPYGLASS_HOME/GuideWare/New_RTL
read_file -type sgdc global.sgdc # global SGDC file
46 4.7.1.2
current_goal initial_rtl/lint/simulation
read_file -type sgdc local.sgdc # local SGDC file
remove_file -type sgdc global.sgdc # doesn't work as it is

# a project-level SGDC file
remove_file -type sgdc local.sgdc # works and removes

# the local SGDC file
current_goal none
remove_file -type sgdc global.sgdc # works as we have
# moved to project scope
18. SpyGlass CDC solution SoC abstraction flow is not supported in

sg_shell.
19. An escaped name is accepted in the set_option top <top-

name> command, but the corresponding escape directory is not
created.
20. Some setup rules do not run when the user specifies the
compile_design command after the link_design command.
SpyGlass may report the SDC_55 violation in this case.
21. SpyGlass reports the SDC_219 violation if the user specifies the
create_clock command without the -period argument. SpyGlass
adds 0.0 as the default period value in such cases.
22. Multi-mode is not supported for SDC equivalent command

specified on sg_shell.
23. SDC equivalent commands specified directly on sg_shell are not

considered if the user has deleted the default sdc_data
4.7.1.2 47
command, which is created by sg_shell, by using the

remove_adc command.
24. When the user specifies the open_project command to open an

existing project in which the user-specified SGDC file was
converted into an ADC file, SpyGlass may not consider the SDC
equivalent commands of that ADC file.
Description: While saving a project, the user-specified SGDC file is
converted into an ADC file if the user deletes some SGDC commands by
using the remove_adc command.
Later, when the user opens the same project by using the
open_project command, SpyGlass may not consider the SDC
equivalent commands of that ADC file.
25. Issues with running the get_constrained_muxes in sg_shell

after running a goal containing rules of SpyGlass TXV solution.
Description: If the user runs a goal that contains rules of SpyGlass TXV
solution and then the user runs the get_constrained_muxes
command, SpyGlass generates invalid results.
Solution: To fix this problem, perform the following steps:
a. Run a goal containing rules of the SpyGlass Constraints solution only.
b. Run the get_constrained_muxes command.
26. Discrepancies in the common SDC flow in Atrenta Console and

sg_shell
Description: The sdc2sgdc option is always on in sg_shell but is off
by default in Atrenta Console. Therefore, if you use a project file
(created in sg_shell) in Atrenta Console GUI, information contained in
SDC files may not get automatically used by rules during Console run.
Solution: Specify the following command in the project file before using
this file in Console:
set_option sdc2sgdc yes
48 4.7.1.2
Waveform Viewer
NOTE: Remove the .SynaptiCAD directory from your home directory before running
SpyGlass if you encounter any issues with the Waveform Viewer.
1. Currently, the Waveform Viewer has been tested on the

following Linux Window Managers — Sawfish, Icewm (GNOME),
Kwin (KDE), Metacity, and Enlightenment. There may be some
display issues on other Window Manager when invoked through
VNC.
Description: On most RedHat variants, it is easy to change the Window
Manager used by VNC by editing the ~/.vnc/xstartup file and
un-commenting the two lines following the comment:
# Uncomment the following two lines for normal desktop:
Alternatively, you can replace the line at the end that reads "twm&" with
a line to invoke the Window Manager of your choice. For example,
replace line "twm &" with "sawfish &" and re-start the VNC server.
The display issues should go away.
2. If you cannot execute the Alt+Tab key combination (to circulate

among windows where one of them is a Waveform Viewer) on
the SunOS platform, you need to set the following additional
environment variables:
setenv LANG en_US
setenv LC_ALL en_US
3. The Save as Filter and Reload Filter menu commands do not

work properly.
4. A signal cannot be loaded at a particular place in the Waveform

Viewer as the signals are arranged in a topological order by
default.
You can move any signal to the desired location manually by dragging
the signals to the desired location.
SpyGlass Customization
4.7.1.2 49
1. SystemVerilog constructs are not supported by Verilog C APIs or

RTL Perl Objects APIs
Description: SystemVerilog constructs are not available to a custom
product developer. You should be able to fetch non-SV specific
constructs of your design via existing Verilog C APIs and RTL Perl
Objects APIs.
2. Increase in SpyBuilder runtime

Description: SpyBuilder runtime increases when you run the
spygenlib utility. The spygenlib utility internally searches for a
per API license feature. This causes an increase in the SpyBuilder
runtime.
Solution: Use the -fast_so_build switch on the command-line to
save this runtime hit.
SpyGlass RTL Modification Engine

1. VHDL2000 constructs are not supported.
2. If a master name of an instantiation is specified by using

ìfdef, port-map changes to such instantiation may not happen
correctly.
Description: Consider the following block:
ìfdef ()
M1
èlse
M2
èndif
iname (portMap)
If the user tries to modify the above instantiation, SpyGlass RTL

Modification Engine may not work correctly.
Solution: In such cases, modify it manually to rectify the reported STX
error.
50 4.7.1.2
3. During RTL modification, some modules are required to be

cloned. This may result in increased synthesis warnings because
existing warnings on the original module are replicated in all the
clones.
4. The AutoFix feature currently works for single top design unit
only.
Solution: In case of multiple top design units, use the -top option.
5. Issues with ifdef usage.

Description: Consider the following RTL:
ìfdef <macro>
Mod1 inst_name
èlse
Mod2 inst_name
èndif
(<port assocn>);
The above RTL produces an incorrect post-BIST RTL.

Solution: To resolve this issue, modify the above RTL to the following:
ìfdef <macro>
Mod1 inst _name (<port assocn>)
èlse
Mod2 inst_name (<port assocn>)
èndif
6. RTL modification does not occur in some cases

Description: RTL modification does not occur in the following cases:
 When an enable expression contains internal/local-scope nets (VHDL
only). In Verilog, this is handled under the
-
rme_handle_flops_in_local_scope RME parameter.
 When an enable expression has a net that is of the enum/integer
data type (VHDL only)
 When LHS is an expression, as shown in the following example:
4.7.1.2 51
{q1, q2} <= {d1, d2}

But this is handled by the
-
rme_handle_flops_in_local_scope RME parameter.
 When a flip-flop is inside an instance that is instantiated, as shown in
the following example:
Master instance1 (<portmap>), instance2 (<portmap>)
 When port type or any net type is unpacked array type. RME sanitizes
out such expressions having nets from unpacked array data-type or
routing through module having ports of unpacked array datatype.
But, this is handled by the -
rme_handle_unpacked_data_type RME parameter.
7. It is not possible to modify VHDL designs with entities of the

same name (different definition) present in different libraries.
8. Modification of VHDL configurations is currently not supported.

Solution: The support will be provided in a future release.
9. Issues with include files

Description: Support for modification inside Verilog files passed
through the ìnclude macro is currently not present.
SpyGlass skips any such modifications. This may result in errors while
compilation of the modified RTL.
NOTE: The behavioral and structural components of a module are assumed to be in the
same file as the module declaration.
Solution: Do not use instantiations and always blocks within the files
that are used as ìnclude macro.
10. Issues in modification of an instance inside a generate block

having a parameter override by using defparam
Description: Consider the following original RTL:
module myblock(input in, output out);
defparam myparam = 2;
endmodule
ùndef MACRO_NAME // undefined
52 4.7.1.2
module top(input in, output out);

genvar i;
generate for(i=0; i<2; i++)
begin : gen_block
defparam I1.myparam = 4;
myblock I1(..);
end
endgenerate
endmodule
Following is the modified RTL in this case (See the comments in bold):
genvar i;
generate for(i=0; i<2; i++)
begin : gen_block
defparam I1.myparam = 4; // this result in STX as
// instance name has changed outside generate block
// myblock I1(..); //commented by SpyGlass RTL
// Modification Engine
end
endgenerate
//inserted by SpyGlass RTL Modification Engine

myblock \gen_block[0].I1 ();
myblock \gen_block[1].I1 ();
endmodule
Solution: Resolve the STX error, and move out the defparam
statement from the generate block.
11. Ungroup issue

Description: The RTL modification engine does not support the
ungroup constraint.
4.7.1.2 53
12. Unsupported RTL styles

Description: The following points discuss cases of unsupported RTL
styles:
 The following example explains the issue related with modification of
modules that did not have any port originally.
module myblock(); // no port exist for myblock
..
..
endmodule
myblock I1();
endmodule
 The RTL modification engine inserts ports/signals of type
std_logic.
A conflict may occur in case of interaction between a SpyGlass RTL
Modification Engine inserted signal and a user-defined signal of
incompatible data types. This is explained in the following example:
entity myblock
port (
P : in bit;
Q : out bit;
);
end entity;
architecture rtl of myblock is
signal atrenta_wire : std_logic; -- Atrenta inserted
--signal
begin
Q <= atrenta_wire; -- Conflict in data type
end rtl;
 Modification of multiple instances or an assignment statement on a
single line is not supported.
module myblock(…);
M1 inst1(); M2 inst2(); // multiple instances
always @(posedge clk)
begin
54 4.7.1.2
q1 <= in1 ; q2 <= in2; // multiple assignment

// statements
end
endmodule
Such cases may result in incorrect modifications.
 The RTL modification engine does not add an enable to modify flip-
flop statements defined by `define or parameterize parameter.
This is explained in the following example:
`define INDEX [7:0]
`define WIDTH 8
always @(posedge clk or negedge rst)
if (~rst) begin
q <= `WIDTH'b0;
end
else begin
q ÌNDEX <= d ; // SpyGlass RTL Modification Engine
// cannot modify this
end
The RTL modification engine may generate incorrect RTL in such
cases.
 The RTL modification engine does not modify a process block in which
a net/signal of a user defined-type is used.
This is reported in AutoFix summary report.
Ensure that no STX error is present in the modified RTL.
13. Issues with bus merging of signals greater than two

dimensions in VHDL
Description: The RTL modification engine does not merge bits of pins
(on an instance) greater than two dimensions in VHDL.
NOTE: This issue exists only in case of the SpyGlass RTL modification engine. This is not
an issue with SpyGlass analyzer.
14. SpyGlass RTL Modification Engine does not support

modification inside DesignWare components
Solution: Use the dont_touch constraint to avoid modification in
4.7.1.2 55
DesignWare components.
15. RME-generated source files and project files cannot be used for
designs that are precompiled either through single-step
precompilation by using the libhdlf command or through
two-step precompilation by using the lib command.
Description: If the precompiled dump of RTL files is generated by using
the libhdlf command or the lib command, the RME-generated
source files and project files become invalid for use once the RTL files of
that precompiled dump are modified.
NOTE: This issue does not exist if the precompiled dump is generated through
single-step precompilation by using the libhdlfiles command. In this
case, the RME-generated source files and project files can be used even if the
RTL files of that precompiled dump are modified.
Solution: Recompile the design again, preferably by using the
libhdlfiles command.
Refer to the RME Application note for details on handling of
pre-compiled designs post-modification.
16. Issues with VHDL composite type, record, in the selective

AutoFix flow
Description: The AutoFix feature of SpyGlass RTL Modification Engine
does not support gating on record field names.
For example, consider the following VHDL record snippet:
type memstattype is record
hsize : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
In the above example, gating on record.hsize is ignored by AutoFix
in the selective AutoFix flow.
Documentation
56 4.7.1.2
1. Unable to read SpyGlass PDF documentation

Description: Adobe Acrobat Reader fails to read PDF files of SpyGlass
documentation. Acrobat Reader generates an error message notifying
that it cannot read the file due to unknown symbols.
Solution: This error message is generated if you are using Acrobat
Reader 3.x or earlier version of Acrobat Reader. You require Adobe
Acrobat Reader 4.0 or higher to read SpyGlass documentation in PDF
format. Please note that Adobe Acrobat Reader is freely available from
Adobe site: www.adobe.com.
2. Issues with the search feature in the HTML-based help

Description: The vertical slider in the Search Results pane may indicate
that there are no more results even when more results are available.
Go to the last displayed match and press the down arrow key to view
other results.
3. When you open a pdf file from the

SPYGLASS_HOME\doc\AllDocs directory, the hyperlinks to the
SGDC commands do not work.
Solution: Instead of opening pdf files from the
SPYGLASS_HOME\doc\AllDocs directory, open a pdf file from the
SPYGLASS_HOME\doc\policies directory.
The SPYGLASS_HOME\doc\AllDocs directory lists all documents of a
release in a flat structure and is provided for backward compatibility
reasons.
4. HTML-based search does not work if a partial string is specified

Description: If a partial string is specified in the HTML-based search
then no results are returned. For example, specifying
SetResetConverge instead of SetResetConverge-ML does not
return the results for SetResetConverge-ML.
Solution: Specify the exact search string.
4.7.1.2 57
Atrenta Standard Products - Known Problems and Solutions
Atrenta Standard Products - Known Problems

and Solutions
This section describes the known problems and their solutions applicable to
Atrenta SpyGlass standard products for SpyGlass 3.5.x releases up to
4.7.1.2.
General
1. Issues with running the const_mgmt and const_intern1
products together
Description: SpyGlass flags the following warning message if the
const_mgmt and const_intern1 products are run together:
File-label 'UNPARSED_COMMAND_FILE' is already registered
2. Information present in the initialization report generated by the

SpyGlass TXV solution and SpyGlass CDC solution is different.
Description: Information generated in the SpyGlass CDC solution
initialization report (/spyglass_reports/clock-reset/adv_cdc.rpt) and SpyGlass
TXV solution initialization report (/spyglass_reports/txv/0.init) has the
following differences:
 Difference in information related with clocks
 SpyGlass CDC solution report does not contain generated clocks.
However, this information is present in the report of SpyGlass TXV
solution.
 SpyGlass CDC solution report shows clocks that have not been
used on any flip-flop. However, SpyGlass TXV solution report does
not show such clocks.
 Difference in information related with latches
 For SpyGlass TXV solution, latches are counted as sequential
elements while calculating an initialization percentage. This can
result in a different sequential element count and a different
initialization percentage, as shown below:
Initialization percentage in SpyGlass TXV = (Number of initialized
58 4.7.1.2
Atrenta Standard Products - Known Problems and
Solutions
sequential elements) /(Total no of sequential elements including

latches) * 100
Initialization percentage in SpyGlass CDC = (Number of initialized
flip-flops) /(Total no of flip-flops) * 100
 Difference in information related with resets
 If a reset is specified twice in an SGDC file, SpyGlass CDC solution
report shows that reset twice, while SpyGlass TXV solution report
shows it once.
 SpyGlass CDC solution report shows resets that have not been
used on any flip-flop, while SpyGlass TXV solution report does not
show such resets.
 Difference in sequential element initialization list
For a design containing complex clocks, different precision levels of
clock periods in SpyGlass TXV solution and SpyGlass CDC solution
may result in different clocks edges. This can cause a difference in
the initialization of sequential elements in the two products.
For example, clock period for a clock with its period as 6.66667 could
be treated differently in the SpyGlass TXV solution and SpyGlass CDC
solution due to different precision levels in the two products, which
can cause a difference in initialization results.
SpyGlass audits Solution

1. Issues with the Audit report
Description: The 1D/2D column of the Audit report that lists the total
of each One-dimensional array and two-dimensional array, respectively,
in a design currently works for Verilog designs only. These columns are
left blank for VHDL designs.
SpyGlass Advanced Lint Solution

1. Limitations of the Av_initstate01 rule
Description: The Av_initstate01 rule has following limitations:
4.7.1.2 59
 If a VCD file is specified for initialization by using the vcdfile

parameter, a spreadsheet file is not generated for uninitialized
sequential elements.
 If no reset is present in a design, a clock is reported as X for
uninitialized sequential elements.
2. OVL Issues
Description: For the assert_cycle_sequence OVL assertion or
constraint, the maximum number of clock cycles (num_cks) supported
is 64.
3. Limitations of the Av_case01 and Av_case02 rules

Description: Following are the limitations of the Av_case01 and
Av_case02 rules:
 When a function containing a case statement is called multiple
times, the Av_case01 and Av_case02 rules report a violation at the line
containing the case expression for each violating function call.
These violations may appear duplicate.
Solution: Use the schematic of a violation to analyze the corresponding
function call.
 These rules do not check functions that are without a begin-end
block and contain a case statement in which the expression is a
case-select expression, containing an operator, over the inputs of the
function.
4. Limitations of the Av_deadcode01 rule

Description: The Av_deadcode01 rule does not check inside a function
definition even if one of the corresponding function call is constant.
SpyGlass CDC Solution

1. If multi-dimensional signals that are used inside generate blocks
60 4.7.1.2
Solutions
are inferred as quasi-static signals by the Setup_quasi_static01

rule, the generated SGDC file may contain incorrect bus-merged
name string.
Solution: Review such signals from the generated SGDC file before
declaring them as quasi-static signals, and append the escape character
wherever required.
Refer to the Handling Nets declared in a Sequential Block topic in
Atrenta Console User Guide.
2. Limitations in the hierarchical verification flow

Description: Following are the limitations in the hierarchical verification
flow:
 Reset synchronizers propagated to block output ports are not
abstracted.
 If a top-level port goes to different domain flip-flops inside an
abstracted block, it is not reported by the Clock_sync05 rule.
Similarly, if a source flip-flop is synchronized multiple times inside
such block, it is not reported by the Clock_sync09 rule.
 The Reset_sync01, Reset_sync03, Reset_sync04, and Clock_glitch01
rules do not support the abstract_port constraint. These rules
support the input constraint.
In such cases, use the Ar_sync_group rules instead of the
Reset_sync01, and Reset_sync03 rules.
 If the abstract_port -sync constraint qualifies a crossing inside
a block, SpyGlass does not generate the abstract_port -sync
inactive constraint at the output port of the block during
abstraction of the block.
 If an input port is driving a multi-flop synchronizer inside a block, the
Clock_info15 rule generates the abstract_port constraint with a
virtual clock and the -combo no argument.
During constraints validation, if such port is driven by a clock that is
same as the destination clock, the SGDC_abstract_validation04 rule
reports a false violation.
 Considerations for multi-mode analysis with respect to the
hierarchical SoC flow.
4.7.1.2 61
A block may operate in multiple modes. In the current abstraction

flow, a block needs to be abstracted in each mode and used at the
higher level of hierarchy separately.
However, if a block has many modes or it can be parameterized, and
is instantiated in a higher level of hierarchy multiple times with
different parameters, the model can be dropped from abstraction.
In such cases, constraint the module by using the ip_block
constraint.
3. Limitations of the Ac_sync_group rules

Description: The Ac_sync_group rules have following limitations:
 These rules do not detect crossings if a sequential library cell with a
combinational arc for a pin is present between the source and
destination.
 These rules do not consider the following constraint specification:
qualifier -type src
 These rules may report false crossings with an IO pad cell present
between the source and destination.
4. If multiple clocks reach to a flip-flop, the sync_cell and

num_flops constraints consider any one of the clocks to match
the clock specified in these constraints.
Solution: Use the set_case_analysis constraint to select only one
clock on a flip-flop.
5. In a parallel file specified by the fa_parallelfile parameter,

the -I, -Ip, and -Is options of the bsub command are not
allowed in the LSF_CMD keyword.
While running the bsub command, SpyGlass internally passes the -K
option, which is mandatory for running parallel assertion runs. However,
the bsub command does not allow the -K option along with the -I,
-Ip, and -Is options. Therefore, if the user specifies these options,
parallel assertions are not run and the assertion status may remain
partially-proved.
62 4.7.1.2
Solutions
6. Handling multiple clocks by using the cdc_false_path constraint

is not supported in case of black boxes or ports.
Solution: User can specify all clocks in the same constraint. For
example, if the clk1 and clk2 clocks are reaching to a source black
box, user can specify it as the following:
cdc_false_path -from clk1 clk2
NOTE: For details, refer to SpyGlass CDC False Path application note.
7. Formal abstraction flow (setting the fa_flopcount and

fa_seqdepth parameters) may report more partially proved
assertions in case the assertions are expected to fail.
Solution: Run this flow only on partially-proved assertions through a
property file specified by using the fa_propfile parameter.
8. The Clock_info17 rule does not report a violation if a clock and

its corresponding derived clock is used in a particular hierarchy
even though they are synchronous to each other.
9. The Ac_fifo01 rule has the following limitations:

 It may report SpyGlass synthesis generated names for read-and-
write pointers
 Schematic may not be highlighted for pointers in some cases. Usually
this happens in case of delayed pointers.
 In case, there are more than one counter for pointers, they will not
be reported as valid FIFO
10. Issues with wild-card names

Description: Wild-card names with multi-dimensional arrays will not
work.
Solution: Set the parameter hier_wild_card to no to overcome
this limitation.
11. Issues with Report CKSGDCInfo

Description: Report CKSGDCInfo shows single dimensional names for
4.7.1.2 63
multi-dimensional arrays.
12. Issues with assert_cycle_sequence OVL assertion

Description: For the assert_cycle_sequence OVL assertion, the
maximum number of clock cycles (num_cks) supported is 64.
13. If clocks and other constraints are specified in the SGDC file
and clocks are also created by the Clock Setup step in an SGDC
file, the CDC Setup Manager only considers the generated SGDC
file.
Solution: It is recommended that you consolidate both the SGDC files.
You can take the clocks from the generated SGDC file and other
constraints from SGDC file that is provided by you.
14. The Reset Setup step does not have the interactive setup
similar to the Clock Setup step. It creates the autoresets.sgdc file.
Solution: It is recommended that you review the autoresets.sgdc file and
add/delete/modify the reset constraints from this file.
15. In the VHDL and Mixed flow, if the SGDC file (which has the
sdc_data constraint) has <entity.architecture> in
current_design, and you perform the following steps, the
clocks will not be used by setup step of the goals of SpyGlass
CDC solution:
1. Select the cdc_verif_base goal in Atrenta Console.
2. Click on "Setup" tab for the goal.
3. Choose to import constraints from an SDC file.
Solution: Use <entity> in current_design instead.
This problem will be fixed in a future release.
16. Auto-save is not supported in the IO Setup step of CDC Setup

Manager
Description: If the user completes a step and performs the next steps,
then comes back to a previous step that has been completed, and
chooses to skip that completed step, the CDC Setup Manager highlights
64 4.7.1.2
Solutions
that step in red color.

17. The Ac_meta01 rule does not generate monitors in the

following cases:
 If data, output, or clock name of the destination is a multi-
dimensional net
 If data, output, or clock net is inside generate statements
18. The Ac_cdc04a and Ac_cdc04b rules may report false violations
of data and enable changing simultaneously in certain scenarios
when the value of the fa_holdmargin parameter is set to 0.
Solution: Specify the value of the fa_holdmargin parameter to 1 or
2. This problem will be fixed in a future release.
19. Please note the known problems with the specific behavior of
the following rules of SpyGlass CDC solution:
Rule Behavior
Ac_handshake02 May report incorrect results when the request signal and the
acknowledgement signal do not have the same active phase.
Ac_Sanity02 The rule does not handle inout ports driven by black boxes
correctly and may report incorrect messages in such cases.
20. If you specify a clock signal in an input constraint, spurious

clock domain crossings may be detected. This is not the correct
usage of the input constraint.
21. The Ac_datahold01a rule does not check crossings

synchronized by the Clock Gating Cell Synchronization Scheme.
Solution: Set the value of the fa_abstract parameter to
Ac_datahold01a to check clock-gating cell based synchronized
crossings.
22. When users set the value of the fa_abstract parameter to
4.7.1.2 65
Ac_datahold01a, the failure cannot be determined.

Description: Such cases are reported as partially-proved.
Solution: Check failing properties without the fa_abstract
parameter.
23. When all flip-flops are asynchronously de-asserted by a reset,

the Reset_sync01 rule reports all of them except the
synchronizer chain flip-flops with respect to any one clock of a
design.
Solution: Use the Ar_sync_group rules instead of the Reset_sync01
rules.
24. Writing OVL constraints in VHDL is currently not supported.

Solution: Specify the required OVL constraints in Verilog in a separate
file, and pass that file to the tool by using the following command in a
project file:
set_option ovl_verilog { <OVL-file> }
In classic batch, specify the OVL file by using the -ovl_verilog
command-line option and specify the -mixed command also.
The following example shows the OVL file used for a VHDL design:
66 4.7.1.2
Solutions
VHDL File (test.vhd)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_Std.ALL;
library accellera;
use accellera.ovl_assert.all;
entity gray is
port (
clk1, clk2, rst : in std_logic;
in1 : in std_logic_vector(1 downto 0);
out1 : out std_logic_vector(1 downto 0));
end entity;
architecture gray_arc of gray is

signal reg1,reg2 : std_logic_vector(1 downto 0);
...
...
...
end architecture;
OVL File (verilog_ovl_file.ovl)

attach_properties gray:gray_arc
begin_ovl
assert_gray #(0, 2, 1, 1) gray_inst(clk1, 1'b1, reg1);
end_ovl
Project File Command

read_file -type vhdl test.vhd
set_option ovl_verilog { verilog_ovl_file.ovl }
25. Run-time of rules of SpyGlass CDC solution is increased up to

100X
Description: The run-time increases when:
 The ip_block or allow_combo_logic constraints are used.
 The synchronize_cells, synchronize_data_cells, or
reset_synchronize_cells parameters are specified.
 The SoC top-down constraints migration flow (Ac_blksgdc01 rule) is
enabled.
 The Ac_psync_group rules are run with UPF files.
4.7.1.2 67
26. Formal modeling of a port done with respect to the first clock in
some cases
Description: While running advanced SpyGlass CDC rules, formal
modeling of a port is done with respect to the first clock in following
cases:
 If multiple clocks are specified for the same port through the
abstract_port constraints
 If multiple abstract_port constraints are applied on the same
port with different clocks
SpyGlass Constraints Solution

1. Issues with timing exception commands
Description: For any timing exception command, if two consecutive
points are same or map to the same flat-level design object, the path is
considered as non-existent.
2. Issues with rule messages that report floating-point values

Description: Rule messages that report floating-point values may not
show the exact value (specified in the SDC file) due to the
floating-point-to-fixed-width conversion limitations. Therefore, the value
21.8 may be reported as 21.799999.
3. The set_false_path constraint is not considered while

propagating top-level clocks in the Inp_Del14 and Op_Del14
rules.
4. Handling of inout is not done properly for the False_Path01 and

MCP01 rules.
5. If a VDB file is loaded in SpyGlass and a goal is SDC-generated

for SDC_GenerateIncr, bus merging will not be present if the
68 4.7.1.2
Solutions
tc_bus_merge parameter is not specified.

6. For the set_case_analysis constraints, the equivalence report do

not show equivalent commands in reference and implement SDC.
SpyGlass DFT Solution

1. While using the require_path SGDC command for Soc_02 rule, if
you want to provide a vector, then its indices must always be
higher:lower.
Description: Consider the following example:
require_path -tag mode1 -from net_1[7:3] -to net_2[4:2]
net_3 net_4 -parallel
You should not provide a vector as shown in the following example:
require_path -tag mode1 -from net_1[3:7] -to net_4 net_3
net_2[2:4] -parallel
2. Issues with rule having multiple messages of different severities

Description: If a rule has multiple messages of different severities, out
of which one of the severity is DATA, and the user overloads a generic
rule severity (and not the severity of a specific message), the DATA
severity message is also changed to a new severity. This may result in
unwanted violations being reported.
In such cases, user should overload specific rule message of severity
other than DATA and not the generic rule severity.
3. Issues with changing a value of the dftDebugData parameter

from Atrenta Console GUI
Description: Changing the value of the dftDebugData parameter
from Atrenta Console GUI does not affect the automatic back annotation
behavior.
Solution: Specify the changed value through command-line while
invoking Atrenta Console GUI.
4.7.1.2 69
4. Multi-dimensional names are reported in a single-dimensional

format in reports and violation messages.
5. Issues with the support of multi-dimensional names in violation

messages and generated reports
Description: Following are the issues with the support of
multidimensional names in violation messages and generated reports:
 Only a sub-set of rules support multi-dimensional names
 Multi-dimensional names are supported as input in all rules through
SGDC.
6. Issues with running SpyGlass DFT solution when the sgdc

-import command is used
Description: Running SpyGlass DFT solution when the sgdc
-import command is used may create additional black boxes and
results may not be accurate.
7. Issues with the automatic schematic back annotation feature

Description: The automatic schematic back-annotation feature does
not work if the user specifies the -policy=dft,dft_dsm command
in batch mode.
Solution: To make this feature work, specify the
-policy=dft_dsm,dft command. That is, reverse the order of
solution specification.
NOTE: For issues related with RTL modification, see SpyGlass RTL Modification Engine.
SpyGlass DFT DSM Solution

1. Correlation of 'Fault Coverage' number (DC (normal stuck_at
coverage) as well as AC (transition coverage)) with actual ATPG
may not be good for a design having Tied-Faults or nodes with 0
sink.
2. Issues with changing a value of the dftDebugData parameter
70 4.7.1.2
Solutions
from Atrenta Console GUI

Description: Changing the value of the dftDebugData parameter
from Atrenta Console GUI does not affect the automatic back annotation
behavior.
Solution: User should specify the changed value through command-line
while invoking Atrenta Console GUI.
3. The SP_02, SP_03, and SP_04 rules do not support multi-top

designs.
Solution: User should analyze one top at a time.
4. The SP_02, SP_03, and SP_04 do not take information from a .lib
file.
Solution: User should use UPF / CPF to define power control signals.
5. Issues with the support of multi-dimensional names in violation

messages and generated reports
Description: Following are the issues with the support of
multidimensional names in violation messages and generated reports:
 Only a sub-set of rules support multi-dimensional names
 Multi-dimensional names are supported as input in all rules through
SGDC.
6. Issues with running SpyGlass DFT DSM solution when the sgdc
-import command is used
Description: Running SpyGlass DFT solution when the sgdc
-import command is used may create additional black boxes and
results may not be accurate.
SpyGlass DFT MBIST Solution

1. Issues with incremental BIST insertion
Description: Incremental BIST insertion has some issues, such as
existing serial chains cannot be broken and fuse-wrapper connections
are not managed in incremental flow.
4.7.1.2 71
2. Exception promotion is not supported in the bottom-up flow.
3. SpyGlass DFT MBIST solution does not allow parameterized

block insertion or replacement.
4. The flow of the SpyGlass DFT MBIST solution is currently not

supported in Atrenta Console.
5. Parameterized module insertion for VHDL is not supported.

Description: The following is not supported for a VHDL design:
mb_insert_instance -instance {FCNTL_1} \
-cell WRAP_FUSECNTL_T09 \
-parameter_map {{IBM_WRAPPER_NUM_BAYS 1} }
6. SpyGlass DFT MBIST solution does not support user-defined data

types (including 'record' and interface construct) on a
port-interface of BIST or memory modules. This is applicable for
both Verilog and VHDL.
SpyGlass lint Solution and SpyGlass OpenMore Solution

1. Following are some general issues
 If more than one tristate is inferred by using built-in gates (bufif1,
bufif0, etc.), the actual number of tristates inferred by SpyGlass is
more than actual.
 In case of nested function calls in which one of the function has an
inferred tristate signal, SpyGlass reports violation messages at the
location where the function containing the inferred tristate signal is
called rather than the top-most function call.
 Rules that check multi-dimensional arrays have the following
limitations:
 If the array size is greater than 16K then these rules ignore the
array for rule-checking.
72 4.7.1.2
Solutions
 Rule messages that report non-usage of multi-dimensional array

bits do not report the rule-violating bits; they report the array
name only.
2. Issues with specific rules

Description: Following are the issues with some rules:
Rule Behavior
ConsCase Does not flag function/procedure arguments if any case-
inconsistency has occurred
W120 Does not check same variable used in different generate
blocks
ReserveName This rule might flag duplicate violations when a UDP is
(Verilog) declared within the -v/-y file after a module declaration.
3. Issues with the vnSetResetFlop rule-primitive

Description: The vnSetResetFlop rule primitive does not detect cases in
which a flip-flop has both reset and set and any of them is tied to
inactive values. As a result, it reports such cases in the form of
messages.
SpyGlass Power Verify Solution

1. If command source is used in CPF/UPF, the file name/line
number in a violation message can be wrong.
2. False violation reported by the UPF_lowpower12 rule

Description: When level shifter and isolation strategies are written on
top-level ports and user overrides supply nets on the top-level ports by
using the set_related_supply_nets command such that the
power domain associated with a supply net is different from the power
domain of a top-level module, the UPF_lowpower12 rule reports a false
violation on level shifter and isolation strategies.
create_power_domain ALWAYS_ON -include_scope
4.7.1.2 73
create_power_domain OFF -elements u_pd

set_domain_supply_net ALWAYS_ON -primary_power_net VDD_ON
-primary_ground_net VSS set_domain_supply_net OFF
-primary_power_net VDD_OFF -primary_ground_net VSS
set_related_supply_net -ground {VSS} -power {VDD_OFF}

-object_list input_off set_isolation PD_out -domain ON
-elements {input_off} -clamp_value 0 -isolation_power_net
{VDD_ON} -isolation_ground_net {VSS}
In the above example, the UPF_lowpower12 rule reports a false violation

as the value of the -domain argument of the set_isolation
command is ON for the related supply VDD_OFF. For this rule to not
report a false violation in this case, the value of the -domain argument
should be OFF.
Solution: To fix such issues, change the value of the -domain
argument in level shifter and isolation strategy.
SpyGlass moreLint Solution

Description: Following are the issues with some rules:
Rule Behavior
UseBusWidth-ML (VHDL) Does not flag messages for formal arguments in
case of port mapping (instantiations)
RedundantLogicalOp-ML Does not flag messages when an operand in the
(Verilog) logical operation is a function with a constant
output.
The rule also does not check if the function will
always return a constant value.
74 4.7.1.2
Solutions
Rule Behavior
HangingNet-ML (rule False violations are reported if vector signals are
group) used as memory index when SpyGlass is run with
the set_option handlememory yes
project file command.
The set_option handlememory yes
project file command truncates memory size to 2
so that a user can run a design within limited
system resources.
However, using this option results in some false
violations of rules under the HangingNet-ML
group as these rules are checked on synthesized
netlist where AND gate is applied bit-wise with 1
on memory addressing signals. Therefore, only
0-th bit is used and rest remains unconnected if
not used anywhere else.
You can use the following rules of SpyGlass lint
solution for checking signal usage:
W120, W123, W240, W241, W528, W446, W494,
W495.
RptNegEdgeFF-ML False violations are reported if a clock path has an
odd number of inverters and the path has a self
loop.
2. During normal and precompile run, the ComplexExpr-ML rule

shows different line numbers for expression nodes.
3. Results of some rules may get interchanged

Description: Results of rules, such as UndrivenInTerm-ML,
UnloadedNet-ML, UndrivenNUnloaded-ML, and checkNetDriver may get
interchanged for signals that are explicitly assigned the value of 0 or 1
and are not driving anything. As a result, when a particular violation is
expected, some other violation may be reported.
assign b = 1’b0; // “b” is not even being used
For the above example, SpyGlass reports a violation for the
UndrivenNUnloaded-ML rule. Ideally, SpyGlass should have reported the
UnloadedNet-ML rule violation in this case.
4.7.1.2 75
4. Issues with the SetBeforeRead-ML rule

Description: The SetBeforeRead-ML rule does not report any violation
for a variable that is read inside a for loop before it is set.
For example, this rule does not report a violation in the following case:
for(i=0;i<2;i++) begin
o1[i] = w1;
w1 = 1'b1;
end
SpyGlass Power Family

1. In some cases, SpyGlass reports the SDC_46 warning when the
user specifies SDC files by using the sdc_data constraint.
Solution: Ignore this warning.
2. Issues with TAO (Timing Optimization)

 The TAO flow is not supported on the SuSe platform.
Solution: It is recommended to not invoke the TAO flow if the operating
system platform is SuSe.
 TAO is not supported on RHEL5 platform.
3. Using the pe_power_state_from_sim parameter with SGDC may

give incorrect power results.
Solution: This parameter is intended to be used with CPF.
4. The PEPWR22 and PESTR22 rules use formal engines to do

analysis, and are therefore runtime intensive.
5. Activity and probability values use a precision of three decimal

places. Therefore, if a signal has less than one-tenth percent
activity of the fastest signal, the activity of that signal is rounded
off to zero.
6. The graph generated for the PESA07 rule may not contain
76 4.7.1.2
Solutions
expected data
Description: The graph generated for the PESA07 rule does not contain
expected data if the user changes the value of X-axis in the Activity
Browser window from Time(ps) to Clock cycles.
7. Issues with the power reduction goals

Description: The power_reduction, power_reduction_adv,
and power_reduction_extra goals contain synthesis options that
maximize the number of power saving opportunities in a design.
These synthesis options are different from the default synthesis options,
which are used in the SpyGlass Power Estimate goal and the GuideWare
SpyGlass Power Reduce goal.
For some designs, which contain partially redundant muxes, the total
area and total power reported by the reduction goals may be larger than
the actual value reported by the SpyGlass Power Estimate goal. Power
savings reported by these reduction goals is correct. The synthesis
difference only affects combinational logic that is not involved in the
power reduction opportunity itself.
Solution: For such designs, please rely on the absolute power reported
by the SpyGlass Power Estimate goal rather than the absolute power
reported by the SpyGlass Power Reduce goals.
8. Errors in the Synopsys liberty file may not get reported during
SpyGlass library compilation
Description: In some cases, a Synopsys liberty file may contain errors,
which are not reported during SpyGlass library compilation. These errors
may prevent proper completion of data-path or DesignWare synthesis.
In such cases, an Error 1 message may appear on the standard output,
and the black box report displays elements that have names starting
with M_RTL. These extra black boxes result in a gate count, which is too
low.
Solution: Ensure that Synopsys liberty files have correct syntax before
running SpyGlass.
9. RTL AutoFix and SEC is not supported in case of hierarchy

ungrouping by using the ungroup constraint
Description: Using RTL AutoFix in this case may result in an RTL with
4.7.1.2 77
syntax errors.
10. Runtime of some rules may increase due to addition of new

features
Description: As various new features have been added in the
PEPWR20, PEPWR21, PEPWR22, PEPWR23, PESTR20, PESTR21,
PESTR22, and PESTR23 rules, runtime of these rules may increase.
However, better results in many designs are expected because of the
new features.
11. Issues with SpyGlass SEC solution

Description: SpyGlass SEC solution has the following known problems:
 Memories in which all write ports do not work on the same clock are
not supported.
 Memories in which there are multiple read ports and different read
ports differ in either of the retain_output or async property are
not supported.
 No special handling is done for write mask bits.
 No special handling is done for the writethru memory property.
 Handling of memories with no write port specification is erroneous.
SpyGlass SEC solution may produce false negatives in such cases.
 If address lines of memories are unconnected/undriven, SpyGlass
SEC solution may produce false positives.
 If memory output pins are unconnected/hanging, SpyGlass SEC
solution may produce false positives while verifying optimizations
done by the PEPWR25 rule.
 SEC verification of the light sleep technique (PESTR29 and PEPWR29
rules) is not supported in SpyGlass SEC.
SpyGlass STARC Solution

1. Wrong violations reported by the STARC-3.2.3.2 rule and the
78 4.7.1.2
Solutions
W110 rule of SpyGlass lint solution

Description: The STARC-3.2.3.2 rule and the W110 rule of SpyGlass
lint solution may report wrong violations for instances inside
generate-for blocks.
2. The STARC-2.9.2.1 rule cannot process value propagation.

Description: In such cases, SpyGlass cannot determine whether the
value is a constant or not.
3. Issues with FSM Interpretation (VHDL Only)

 FSMs with a combinational part specified by using the IF/ELSIF/ELSE
statements are not handled.
 FSMs with state handling distributed across multiple combinational
processes are considered as separate state machines.
4. Issues with some rules

Description: Following are the rule-specific issues:
Rule Rule-deck Behavior

STARC-1.1.4.4 Verilog Flags when a macro is defined locally in a
module by including a file that holds the
macro declaration even though it may be
used only within that module
STARC-1.2.1.3 Verilog Flags cell-defined modules also.
If there is a loop within another
combinational loop, only the outer loop
would be reported
STARC-2.3.1.2c Verilog Flags at the last line of the UDP definition
STARC-2.3.1.4 Verilog For arrays of type #(3,5), two messages
are shown in the same line. Similarly,
three messages are shown in same line
for arrays of type #(2,4,5)
4.7.1.2 79
Rule Rule-deck Behavior

STARC-2.5.2.1 VHDL Flags if NAND (NOR) gates are used in
the logic with tristate driven net and no
other logic is inferred in the module as
SpyGlass synthesis engine generates a
RTL AND (OR) gate and an inverter.
STARC-2.8.5.3 Verilog Considers the return value of functions as
non-constant even for functions returning
constant values in all branches while
evaluating the case select expression for
fixed value
STARC-1.1.1.3a/ Verilog These rules might flag duplicate violations
STARC02- when a UDP is declared within the -v/-y
1.1.1.3a/ file after a module declaration.
STARC05-1.1.1.3
SpyGlass timing Solution

Description: Following are some rules-specific issues:
Rule Behavior
ShiftReg Does not report some cases of circular shift registers
LogicDepth May report violation multiple times in some cases
SpyGlass TXV Solution

1. Issues observed when a user tries to use an existing SGDC file to
extract clock information in Atrenta Console
Description: If the user tries to use an existing SGDC file to extract
clock information in Atrenta Console, SpyGlass reports the
SGDCSTX_024 violation. This violation message indicates the repetition
of same clock name specified by the -name argument of the clock
constraint.
Solution: At the end of the setup process, perform the following steps:
80 4.7.1.2
Solutions
a. Select all the SGDC files that you want to use in the run of SpyGlass
TXV solution.
b. By default, the cdc_setup_clocks.sgdc file (containing all the clock
information in the form of the clock constraint) is disabled.
c. Enable the cdc_setup_clocks.sgdc option if the clock
constraint is not specified in the txv.sgdc file.
d. Comment the clock constraints in the txv.sgdc file that are not
complete, and enable the cdc_setup_clocks.sgdc file.
2. Some critical paths are not reported in the spreadsheet of the

Txv_CP01 rule or in the txv_summary report
Description: In the STA flow of SpyGlass TXV solution, if both FP and
MCP rules are enabled and if a critical path could not be proved either as
a false path or as a multi-cycle path, that critical path is not reported in
the spreadsheet of the Txv_CP01 rule or in the txv_summary report.
In such cases, the spreadsheet may remain empty if none of the critical
path is a false path or a multi-cycle path.
3. In a parallel file specified by the txv_parallel_file parameter, the

-I, -Ip, and -Is options of the bsub command are not allowed in
the LSF_CMD keyword.
Description: While running the bsub command, SpyGlass internally
passes the -K option, which is mandatory for running parallel assertion
runs. However, the bsub command does not allow the -K option along
with the -I, -Ip, and -Is options. Therefore, if the user specifies
these options, the formal verification engine is not run. As a result,
timing exception constraint verification results are not complete.
End of the Document
4.7.1.2 81
82 4.7.1.2

Spyglass® Known Problems and Solutions: This Document Describes The Following

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Spyglass® Known Problems and Solutions: This Document Describes The Following

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SpyGlass® Known Problems

This document describes the following:

SpyGlass® Known Problems and Solutions 1

 SpyGlass DFT MBIST Solution

SpyGlass Known Problems and Their

2. Atrenta® has upgraded to FlexNet Publisher version 11.7 from

3. 3-node license server issue

2. Issues with the design save/restore feature

3. Some violations may not appear in the single-step map-file run

4. In case of save-restore in DesignWare, if the user changes the -

lib SPY_DW_WORK mapping to some other area in the restore

5. For some cases, built-in messages are not restored during

6. Processing of spyRegisterGroup command

spyRegisterGroup command, Atrenta Console uses the last found

7. Imported waive commands are not displayed in separate section

8. SpyGlass does not migrate internal net names (including supply

9. Some block-level waiver commands that have only port name

10. The Inline report is not generated properly when the

11. Waivers do not work on the enhanced message string of the

12. Waivers specified in a block-level do not work in GUI if the

13. SpyGlass may crash if your design contains a multiple

Solution: This problem will be fixed in a future SpyGlass release.

14. In cases where two arguments of a constraint support wildcard

abstract_port -module bbox1 -ports a1 a2 a3 ad1 ad2 ad3

abstract_port -module bbox1 -ports a1 a2 a3 ad1 ad2 ad3

15. Issue with applying the stop specification on DesignWare

16. Issue with applying design constraints on DesignWare modules

17. Issues with width-related rules

assign w1 = (w2 - ((5'b10000 >> 4) - 12));

18. If an array bit select is used in the sensitivity list of an always

19. Issues with ignore specifications specified by using the

which the specified file, file1.vhd, includes an entity and the

20. Issues with the generation of the block dependency report.

21. Issues in ignoring design units from precompilation

ignoredu specifications if they are specified in a source file that is

2. Named overloads and single overloads do not work together.

specify both the -overload and -overloadpolicy commands, a

3. Issue with the -overloadpolicy command-line option

4. The -param command-line option supports only integer

5. If there is a pre-existing .sglib file because of the

VHDL Design Processing

2. Limitations of memory reduction in VHDL

3. SpyGlass does not support VHDL’2000 and VHDL'2008.

Verilog Design Processing

1. Issues with SystemVerilog support during analysis

consistent in the normal and precompile flow. Applying a stop would

 Use of enum methods while declaring an enum as part of module

2. Limitations of SystemVerilog support which impact rule-

typedef enum logic [2:0]

3. Issues with SystemVerilog support during rule-checking

on the nested module, bottom. However, very few rules like

('Q1' set but not read) is reported twice

module utopia1_atm_rx ( Utopia.CoreReceive Rx );

intf #(4) intfinst();

4. Verilog2005 and SystemVerilog are not treated separately in

5. SpyGlass does not support the $ construct in the set membership

Solution: Provide the exact bounds of the range instead of the $

6. SpyGlass has the loop iteration limit of 1048576 for evaluation

7. When the user provides an OVL file for a SystemVerilog module

Mixed-Language Design Processing

2. Issues while working with libraries in mixed-language designs

2. Discrepancy in violation messages between elaborator and VHDL

3. False SYNTH_1038 messages in designs