ECE

 305     Spring  2015  

ECE  305  Homework  SOLUTIONS:  Week  12  

 
Mark  Lundstrom  
Purdue  University  
 
 
1) The  energy  band  diagram  for  an  MOS  capacitor  is  sketched  below.  Assume  T  =  300K  
and  an  oxide  thickness  of   xo = 1.1  nm.    Answer  the  following  questions  using  the  
delta-­‐depletion  approximation  as  needed.  (Note  that   E F = Ei  at  the  oxide-­‐silicon  
interface.)  (This  problem  is  similar  to  prob.  16.7,  Pierret,  SDF).  
 
 

 
 
1a)    Sketch  the  electrostatic  potential  vs.  position  inside  the  semiconductor.  
 
Solution:  

     
 
 
 
 

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1b)    Roughly  sketch  the  electric  field  vs.  position  inside  the  oxide  and  
semiconductor.  
 
Solution:  

     
 
Note:    We  assume  that  there  is  no  charge  in  the  oxide  and  no  charge  at  the  
oxide-­‐Si  interface.  
 
1c)    Do  equilibrium  conditions  apply  inside  the  semiconductor?    Explain  
 
Solution:  
YES.    The  Fermi  level  is  constant,  but  even  if  the  Fermi  level  in  the  metal  does  
not  align  with  the  Fermi  level  in  the  semiconductor  (as  is  the  case  when  a  
gate  voltage  is  applied)  the  oxide  insures  that  no  current  flows,  so  the  metal  
and  semiconductor  are  two  separate  systems  in  equilibrium  with  possibly  
different  Fermi  levels.  (Note:    We  assume  that  light  is  not  shining  on  the  
semiconductor.)  
 
1d)    Roughly  sketch  the  hole  concentration  vs.  position  inside  the  semiconductor.  
 
Solution:  

     

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1e)    What  is  the  hole  concentration  in  the  bulk?  
 
Solution:  
p ( x → ∞ ) = ni e( Ei −EF ) kBT = 1010 e0.51/0.026 = 3.3 × 1018
 cm-­‐3  
p ( x → ∞ ) = 3.3 × 1018 cm -3
 
 
1f)    What  is  the  hole  concentration  at  the  surface?  
 
Solution:  
p ( x = 0 ) = ni e( Ei −EF ) kBT = 1010 e0 = 1 × 1010
 
p ( x = 0 ) = 10 cm 10 -3

 
 
1g)    What  is  the  surface  potential?  
 
Solution:  
φS = φ ( x = 0 ) − φ ( x → ∞ ) = 0.51 V
 
 
1h)    What  is  the  gate  voltage?  
 
Solution:  
The  Fermi  level  in  the  metal  aligns  with  the  Fermi  level  in  the  semiconductor,  
so  the  gate  voltage  must  be  zero.  (Note:    The  fact  that  there  is  a  volt  drop  
across  the  oxide  and  the  semiconductor  with  VG  =  0  indicates  that  there  is  a  
workfunction  difference  between  the  metal  and  the  semiconductor.)  
 
1i)    What  is  the  voltage  drop  across  the  oxide?  
 
Solution:  
The  electric  field  at  the  surface  of  the  semiconductor  is  given  by  eqn.  (16.27)  
in  SDF  as:  
2qN AφS
ES =    
KSε0
We  find  the  electric  field  in  the  oxide  from:  
 
K OE ox = K SE S  
so  
KS 2qN AφS
E ox =  
KO KSε0

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HW  Week  12  Solutions  (continued)  

 
The  volt  drop  across  the  oxide  is:  
KS 2qN AφS
Δφox = x0E ox = x0  
K ox KSε0
alternatively  we  can  write  this  as:  
x Q (φ )
Δφox = 0 2qK S ε 0 N AφS = − B S  
KOε 0 Cox
where  
 
QB (φS ) is  the  depletion  charge  in  C/cm2  in  the  semiconductor  and  
Cox  is  the  oxide  capacitance  in  F/cm2  
 

Putting  in  numbers:  

K Oε 0 3.9 × 8.854 × 10−14
Cox = = −7
= 3.6 × 10−6  F/cm2  
x0 1.1× 10
We  found  the  doping  density  in  1e)  and  the  surface  potential  in  1g),  so  
QD = − 2qK S ε 0 N AφS = − 2 × 1.6 × 10−19 × 11.8 × 8.854 × 10−14 × 3.3× 1018 × 0.51  
QD = −7.5 × 10−7  C/cm2  
QD (φS ) 7.5 × 10−7
Δφox = − = = 0.21
Cox 3.6 × 10−6  
 
Δφox = 0.21 V
 
 
Question:    If  the  substrate  were  n-­‐type,  as  in  the  figure  below,  could  you  repeat  this  
problem?  
 

 
 
 

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HW  Week  12  Solutions  (continued)  

 
2) There  is  currently  great  interest  in  replacing  SiO2  with  a  higher  dielectric  constant  
material.    Different  oxides  are  compared  to  SiO2  in  terms  of  the  “Equivalent  Oxide  
Thickness”  (EOT).    EOT  is  the  thickness  of  SiO2  that  would  give  the  same  capacitance  
per  unit  area.    What  is  the  EOT  of  4  nm  of  hafnium  dioxide,  HfO2,  which  has  a  relative  
dielectric  constant  of  25?  
 
Solution:  
K HfO ε 0
CHfO = 2
   
2
xHfO
2

K Oε 0
CEOT =    (The  capacitance  of  a  layer  of  SiO2  of  thickness,  EOT.  
EOT
By  definition,  the  above  two  capacitances  must  be  equal:  
K HfO ε 0 K ε
CHfO = 2
= CEOT = O 0  
2
xHfO EOT
2

KO 3.9
EOT = xHfO = 4× = 0.6 nm     EOT = 0.6 nm  
2
K HfO 25
2

 
Note  that  0.6  nm  of  SiO2  would  be  too  leaky  because  of  quantum  mechanical  
tunneling,  but  4  nm  of  HfO2  gives  the  same  capacitance  with  less  leakage  current  due  
to  quantum  mechanical  tunneling.  
 
 
3) Assume  an  MOS  capacitor  on  a  p-­‐type  Si  substrate  with  the  following  parameters:  
 
N A = 2.7 × 1018 cm -3  for  the  bulk  doping   Oxide  thickness:     xo = 1.1 nm   K O = 3.9  
QF = 0  (no  charge  at  the  oxide-­‐Si  interface)     T = 300 K     VG = 1 V  
 
Also  assume  that  the  structure  is  ideal  with  no  metal-­‐semiconductor  workfunction  
difference.      Determine  the  following  quantities  by  analytical  calculations.    You  should  
use  the  depletion  or  delta-­‐depletion  approximation  for  these  calculations.  
 
3a)    The  flatband  voltage,   VFB .  
 
Solution:  
VFB = 0    because  there  is  no  workfunction  difference  and  no  charge  at  the  
interface.  
 
 
 

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HW  Week  12  Solutions  (continued)  

 
3b)    The  surface  potential,   φS .  
 
Solution:  
QS (φS ) 2qK S ε 0 N A
VG = φS + Δφox = φS − = φS + φS  
Cox Cox
(We  are  assuming  here  that  all  of  the  charge  in  the  semiconductor  is  
depletion  charge  -­‐    no  inversion  charge.    This  assumption  will  be  checked  
later.  
2qK S ε 0 N A
VG = φS + β φS     β= = 0.303  
Cox
φS + β φS − VG = 0  is  a  quadratic  equation  for   φS  
− β ± β 2 + 4VG
φS =  (take  positive  sign.    Since  there  is  a  positive  gate  
2
voltage,  we  should  get  a  positive  surface  potential.)  
 
Putting  in  numbers,  we  find:  
φS = 0.74  V  
Is  this  greater  than   2φ F ?  
k BT ⎛ N A ⎞ ⎛ 2.7 × 1018 ⎞
φF = ln ⎜ ⎟ = 0.026 × ln ⎜⎝ 1010 ⎟⎠ = 0.505
q ⎝ ni ⎠  
2φ F = 1.01 V  
Our  use  of  the  depletion  approximation  for   QS (φS )  in  the  first  equation  is  
justified,  and  
φS = 0.74 V
 
 
3c)    The  electric  field  in  the  oxide,  E OX .  
 
Solution:  
Since  there  is  no  metal-­‐semiconductor  workfunction  difference,  the  voltage  
on  the  gate  is  just  1V  (no  built-­‐in  voltage  to  worry  about)  and  the  voltage  at  
the  oxide-­‐Si  interface  is  0.74  V,  so  
V −φ 1− 0.74
E ox = G S = −7
= 2.4 × 106 V cm
x0 1.1× 10  
 
 
 
 

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HW  Week  12  Solutions  (continued)  

 
Alternatively,  we  could  do  it  another  way.  
Gauss’s  Law  gives:     K Oε 0E ox = −QS = −QB = 2qK S ε 0 N AφS  
QB = − 2qK S ε 0 N AφS = − 2 × 1.6 × 10−19 × 11.8 × 8.854 × 10−14 × 2.7 × 1018 × 0.74  
QB = −8.17 × 10−7  C/cm2  
QB 8.17 × 10−7
E ox = − = = 2.35 × 106
κ ox ε 0 4 × 8.854 × 10 −14
 
E ox = 2.3× 106 V/cm
 
(slight  round-­‐off  error  gives  different  answers)  
 
3d)    The  electric  field  in  the  silicon  at  the  surface,  E S .  
 
Solution:  
At  the  oxide-­‐Si  interface,  we  have:     K Oε 0E ox = K S ε 0E S  

ES =
KO
KS
E ox =
3.9
11.8
( )
2.4 × 106 = 7.9 × 105  

E S = 7.9 × 105 V/cm

 
 
3e)    The  depletion  region  depth,   WD .  
 
Solution:  
2K S ε 0 2 × 11.8 × 8.854 × 10−14
WD = φ = × 0.74  
qN A S 1.6 × 10−19 × 2.7 × 1018
WD = 1.89 × 10−6 cm  
WD = 18.9 nm  
 
3f)    The  charge  in  the  silicon,   QS  in  C/cm2  
 
Solution:  
From  the  solution  to  2c):     QS = −8.17 × 10−7  C/cm2  
QS = −8.17 × 10−7 C/cm 2  

 
 
 
 
 

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HW  Week  12  Solutions  (continued)  

 
3g)    The  charge  on  the  gate,   QG  in  C/cm2  
 
Solution:  
Charge  balance  dictates  that  the  charge  on  the  gate  must  be  equal  and  
opposite  to  the  charge  in  the  semiconductor  (there  is  no  charge  at  the  oxide-­‐
Si  interface).  
QG = −QS = +8.17 × 10−7 C/cm 2  
 
3h)    The  voltage  drop  across  the  oxide  
 
Solution:  
VG = Δφox + φS
 
Δφox = VG − φS = 1− 0.77 = 0.23  V  
Δφox = 0.23 V
 
 
3i)    The  threshold  voltage  for  this  MOS  capacitor  
 
Solution:  
QB ( 2φ F ) 2qK S ε 0 N A (1.01)
VT = 2φ F − = 1.01+  
Cox Cox
VT = 1.01+ 0.304 = 1.314 V  
VT = 1.314 V
 
 
4) The  measured  IV  characteristics  of  a  75  nm,  unstrained  Si,  N-­‐MOSFET  are  shown  
below.    Estimate  the  device  metrics  for  this  transistor.  Specifically,  determine:    a)  the  
on-­‐current,  b)  the  off  current,  c)  the  subthreshold  swing,  d)  the  DIBL,  e)  the  output  
resistance,  f)  the  transconductance  in  the  saturation  region,  and  g)  the  “on-­‐resistance”  
(the  resistance  in  the  linear  region  for  the  maximum  gate  voltage).  
 
 
 
 
 
 
 
 
 
 
 

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HW  Week  12  Solutions  (continued)  

 

 
Solution:  
 

ION  

ROUT   gm  

RON  
DIBL  
S  
IOFF  

 
 
On  current  in   mA/µm :       ≈ 800 µA/µm    
The  on-­‐current  is  the  current  for  the  maximum  gate  and  drain  voltages.  
 
Off  current  in   µ A/µm :       ≈ 6 µA/µm  
The  off  current  is  the  current  for  zero  gate  voltage  when  the  drain  voltage  is  at  its  
maximum  value.  

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HW  Week  12  Solutions  (continued)  

 
Subthreshold  swing  in  mV/decade:   ≈ 85 mV/decade  
This  is  the  millivolts  it  take  to  increase  the  drain  voltage  by  a  factor  of  10  when  
operating  in  the  linear  region.  Typically  measured  at  maximum  drain  voltage.  
 
DIBL  in  mV/V:         ≈ 85 mV/V  
The  horizontal  shift  in  gate  voltage  at  a  fixed  subthreshold  current  between  a  low  and  
high  drain  voltage.  
 
On-­‐resistance  in   Ω-µm :       ≈ 450 Ω − µm  
The  minimum  resistance  in  te  linear  region.  
 
Output  resistance:  in   Ω-µm ;       ≈ 8000 Ω − µm  
One  over  the  slope  of  drain  current  vs.  drain  voltage  in  the  saturation  region.  
 
Transconductance  in   µS µm :       ≈ 1000 µS/µm  
             (at  maximum  drain  and  gate  voltage)  
The  change  in  drain  current  divided  by  the  change  in  gate  voltage.  
 
 
5) Real  transistors  have  parasitic  series  resistances  at  the  source  and  drain.    As  shown  in  
the  figure  below,  the  result  is  that  the  voltages  applied  to  the  terminals  of  the  device  
are  not  the  voltages  on  the  terminals  of  the  intrinsic  device.      
 

   
 
 
 

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HW  Week  12  Solutions  (continued)  

 
5a)   Modify  the  square  law  MOSFET  equations  to  include  the  effects  of  source  and  
drain  series  resistances.  
 
Solution:  
The  voltages  in  the  square  law  expressions  are  the  intrinsic  voltages  –  not  the  
voltages  applied  to  the  terminals.    Using  primes  to  denote  the  intrinsic  voltages:  
 
W µ nCox ⎡ ′2 ⎤
VDS
ID = ⎢(V ′ − VT )VDS ′ − ⎥
L ⎣ GS 2 ⎦ 0 ≤ VDS ′ < VDsat    VGS
′ ≥ VT  
 
W µ nCox
( ′ − VT )
2
ID = VGS
2L       VDS ′ ≥ VDsat   VGS ′ ≥ VT  
 
Note  that  we  use   VGS′  instead  of   VG′  and     VDS
′  instead  of   VGS′  because  with  a  series  
resistance,  the  intrinsic  source  is  not  at  ground  potential.    
 
Straightforward  circuit  analysis  gives  the  intrinsic    voltages  as  
 
VGS ′ = VG − I D RS  
′ = VDS − I D ( RS + RD )
VDS
 
 
Inserting  these  voltages  in  the  square  law  theory  gives  the  answer.    Note  that  ID  ends  
up  on  both  sides  of  the  equations,  and  it  is  not  completely  trivial  to  plot  the  IV  with  
series  resistance.  
 
 
5b)   The  series  resistances  affect  the  drain  current  differently  in  the  linear  and  the  
saturation  regions.    Explain  how  RS  and  RD  affect  the  linear  region  drain  current  
and  the  saturation  region  drain  current.  
 
Solution:  
′ 2 2  can  be  ignored:  
Begin  with  the  linear  region  and  assume   VDS
W µ nCox W µ nCox
ID =
L
(VGS ′ − VT )VDS ′ =
L
(VGS′ − VT ) ⎡⎣VDS − I D ( RS + RD )⎤⎦
 
W µ nCox
To  keep  track  of  the  algebra,  define:   α =  
L
I D = α (VGS
′ − VT ) ⎡⎣VDS − I D ( RS + RD ) ⎤⎦
 
I D = α (VGS
′ − VT )VDS − α (VGS ′ − VT ) I D ( RS + RD )
 
or  
 

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HW  Week  12  Solutions  (continued)  

 
α (VGS′ − VT )VDS VDS
ID = =
1+ α (VGS
′ − VT ) ( RS + RD ) 1
+ ( RS + RD )
α (VGS′ − VT )
 
Note  that  
W µ nCox V′
ID =
L
( ′ − VT )VDS
VGS ′ = DS
RCH  
where      
1
RCH =
α (VGS′ − VT )
 
is  the  resistance  of  the  channel.    Finally,  we  find:  
VDS
ID =
RCH + ( RS + RD )
 
 
which  is  intuitively  what  we  expect.    In  the  absence  of  series  resistance,  we  just  have  a  
channel  resistance.      In  the  presence  of  series  resistance,  the  measured  resistance  in  
the  linear  region,    
V
Rmeas = DS
I D    
is  the  sum  of  the  intrinsic  channel  resistance  and  the  two  series  resistors.  
 
Now  consider  the  saturation  region.    If  
 
VDS ′ = VDS − I D ( RS + RD ) > VDsat
,  
then  we  are  saturated  and  
W µ nCox W µ nCox
( ′ − VT ) = I D = (VGS − I D RS − VT )
2 2
ID = VGS
2L 2L    
so  if   VDS  is  large  enough,  the  RD  does  not  matter.      
The  current  of  the  intrinsic  device  (no  series  resistance)  would  be  
W µ nCox
(VGS − VT )
2
I Di =
2L  
so  
2
I D ⎛ VGS − I D RS − VT ⎞
=
I Di ⎜⎝ VGS − VT ⎟
⎠  
2
ID ⎛ I D RS ⎞
= ⎜ 1− ⎟
I D ⎝ (VGS − VT ) ⎠
i

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HW  Week  12  Solutions  (continued)  

 
When  the  volt  drop  across  the  series  resistance  of  the  source  is  comparable  to  the  
gate  overdrive,  then  the  saturation  current  decreases.  
 
The  effect  of  the  series  resistors  on  the  IV  characteristic  in  the  linear  and  saturation  
regions  is  shown  below.  
 

 
The  source  and  drain  series  resistors  increase  the  linear  region  resistance,  and  the  
source  series  resistance  lowers  the  saturation  current.  
 
 

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