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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
A Low-Power Current-Reuse Analog Front-End
for High-Density Neural Recording Implants
Masoud Rezaei, Student Member, IEEE, Esmaeel Maghsoudloo, Student Member, IEEE, Cyril Bories, Yves De
Koninck, and Benoit Gosselin, Member, IEEE
Abstract—Studying brain activity in vivo requires collecting bio-
electrical signals from several microelectrodes simultaneously in
order to capture neuron interactions. In this work, we present
a new current-reuse analog front-end (AFE), which is scalable
to very large numbers of recording channels, thanks to its small
implementation silicon area and its low-power consumption. This
current-reuse AFE, which is including a low-noise amplifier (LNA)
and a programmable gain amplifier (PGA), employs a new fully
differential current-mirror topology using fewer transistors, and
improving several design parameters, such as power consump-
tion and noise, over previous current-reuse amplifier circuit im-
plementations. We show that the proposed current-reuse amplifier
can provide a theoretical noise efficiency factor (NEF) as low as
1.01, which is the lowest reported theoretical NEF provided by an
LNA topology. A foue-channel current-reuse AFE implemented in
a CMOS 0.18-µm technology is presented as a proof-of-concept.
T-network capacitive circuits are used to decrease the size of input
capacitors and to increase the gain accuracy in the AFE. The mea-
sured performance of the whole AFE is presented. The total power
consumption per channel, including the LNA and the PGA stage, is
9 µW (4.5 µW for LNA and 4.5 µW for PGA), for an input referred
noise of 3.2 µVrm s , achieving a measured NEF of 1.94. The entire
AFE presents three selectable gains of 35.04, 43.1, and 49.5 dB, and
occupies a die area of 0.072 mm2 per channel. The implemented cir-
cuit has a measured inter-channel rejection ratio of 54 dB. In vivo
recording results obtained with the proposed AFE are reported.
It successfully allows collecting low-amplitude extracellular action
potential signals from a tungsten wire microelectrode implanted in
the hippocampus of a laboratory mouse.
Index Terms—Analog front-end, bio-potential amplifier,
current-reuse amplifier, high-density, multi-channel neural record-
ing, noise efficiency factor.
I. INTRODUCTION
EURAL recording systems featuring several parallel
N readout channels enable neuroscientists to study brain
Manuscript received April 23, 2017; revised July 30, 2017, September 27,
2017, and January 14, 2018; accepted January 16, 2018. This work was sup-
ported in part by the Natural Sciences and Engineering Research Council of
Canada, in part by the Weston Brain Institute, and in part by the Microsystems
Strategic Alliance of Quebec. This paper was recommended by Associate Editor
G. Wang. (Corresponding author: Masoud Rezaei.)
M. Rezaei, E. Maghsoudloo, and B. Gosselin are with the Department
of Electrical and Computer Engineering, Université Laval, Quebec, QC
G1V 0A6, Canada (e-mail: masoud.rezaei.1@ulaval.ca; esmaeel.maghsoudloo.
1@ulaval.ca; Benoit.Gosselin@gel.ulaval.ca).
C. Bories and Y. De Koninck are with the Research Center of the Que-
bec Mental Health Institute, Université Laval, Quebec, QC G1J 2G3, Canada
(e-mail: cyril.bories.1@ulaval.ca; Yves.DeKoninck@neuro.ulaval.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TBCAS.2018.2805278
1932-4545 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
1
neurodynamics in-vivo. Such invaluable information is critical
to study and to understand the functions of biological neural net-
works. Moreover, such devices open up opportunities for build-
ing feedback systems to help patients with spinal cord injuries,
Parkinson’s disease and other chronic neurological diseases.
State-of-the-art neural recording systems consists of two main
parts: 1) an implantable device typically including a data acqui-
sition unit, a power management unit (using either a wireless
power transmission link [1] or a small battery as power source
[2]), as well as a wireless transmitter, and 2) an external base sta-
tion made of a wireless receiver connected to a host PC [3]. Thus,
the design of a suitable multichannel neural recording system
must address several critical challenges. Among others, it must
handle a large number of low-noise amplifiers (LNA) (typically
one per channel) under stringent power budget [4]. As it must
interface with implanted microelectrode arrays presenting sev-
eral recording sites, the small pitch of the microelectrode arrays
(a few hundred micrometers typically) usually determines the
circuit density and overall system area. Heat dissipation, which
needs to be kept as small as possible not to harming tissues,
also puts limits on power consumption. For instance, it has been
shown that a local temperature rise of only a few °C can harm
adjacent tissues [5]. Power is often provided to the recording
system by a small battery or by a wireless power transmission
scheme [2], which also contributes to power limitation. Addi-
tionally, the LNA circuits must present very low-noise, so the
weak neural signals can be properly collected, and they must
suppress the microelectrode potentials to avoid large offset volt-
age at the input of the LNA [4]. The LNA usually determines the
overall signal-to-noise ratio of a given neural signal recording
device. Therefore, the design of suitable LNA is critical for this
application as it must present low-input noise and low-power,
while being scalable to very large numbers of recording chan-
nels (typically hundreds [6]). Several analog front-end (AFE)
topologies were proposed to address these requirements and
challenges. A robust approach consists of using an ac-coupled
capacitive feedback topology consisting of feedback capacitors
implemented around an operational transconductance amplifier
(OTA) [4], as a first stage LNA. Such feedback topology, the
goal of which is to properly amplify the neural signal while
removing the electrode potentials, often uses very large resis-
tive elements known as pseudo-resistors [4], in parallel with
feedback capacitors to bias the amplifier and to create a very
large-time constant high-pass filter for suppressing the dc offset
voltage of the electrodes, the low-frequency noise and the drift.
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2 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

current-reuse structure (Fig. 1) a well-suited solution for

the design of a high-performance neural recording AFE. As
shown in Fig. 1, a current-reuse structure consists of stacked
differential input pairs, which converts the input voltages into
currents, a current recombination block, which separates the
output currents assigned to each input signal, and an output
stage, which uses the recombined currents to generate an output
voltage that corresponds to a given low-amplitude input signal
[13]. The voltage headroom required in each input differential
pair is minimized by operating each input pair transistor in the
sub-threshold region.

A. Principle of Current-Reuse Amplifier

The schematic of a stacked current-reuse amplifier previously
Fig. 1. Conceptual representation of a four-channel stacked current-reuse
amplifier. The input differential pairs share the same supply currents and the presented in [14] is shown in Fig. 2. A two-stacked input topol-
recombination and output blocks provide an output signal that is related to each ogy is shown for simplicity. Such a current-reuse circuit topol-
corresponding input. ogy presents several stacked input differential pairs separated
across a binary tree structure in which each transistor of an input
In this paper, we first review the principle of current reusing pair has at most one stacked children input pair [13]. Since gm =
amplifiers (Fig. 1) which prompt for very low power consump- (2 μCox (W/ L)Id )1/2 and Vgs = Vth + (2Id /(μCox (W/L))1/2
tion designs. We then provide a noise analysis of this circuit equivalent transconductances and gate-source voltages are
topology detailed in Section II-B, and we propose a new current- maintained across all stacked input pair transistors by using
reuse AFE circuit, including an LNA and a programmable gain half the transistor size in the children branches compared to the
amplifier (PGA), which is improving previous implementations, transistors of the parent branches, and by using half the current
in Sections II-C and II-D. Additionally, we discuss the utiliza- in the children branches compared to the current flowing into the
tion of a capacitive T-network in the implementation of the LNA parent branches. Then, a single current source can be employed
(Sections II-E and II-F) to implement small capacitors values to bias all stacked differential input pairs at once, the tail currents
with very high accuracy for decreasing the size of the input ca- of which are coming from the previous stages. Indeed, since the
pacitors of the LNA. Then, in Section II-G we analyze the noise same total current flows into Stage 1 and Stage 2 (Fig. 2), both
performance of this new current reuse circuit and we show that it stages have equal overall gm values. The small signal currents
can reach the lowest reported theoretical noise efficiency factor output i1 , i2 , i3 , i4 are independent and linear combinations
(NEF). The measured performance, as well as in-vivo results ob- of the several output currents that are derived from one output
tained with this front-end design fabricated in a CMOS process, branch which corresponds to a given stacked input pair. For in-
are presented in Section III. Finally, conclusions are drawn. stance, in Fig. 2, Stage 1 has a single input pair, while Stage 2
has two input pairs, having identical input voltages Vin2+ and
II. CURRENT-REUSE ANALOG FRONT-END OVERVIEW Vin2− , in parallel. Then, in order to generate Vout1− and Vout1+ ,
the corresponding small signal output currents io1− and io1+
Previously, several efforts have been devoted to improving the
are re-constructed by summing output currents i1 , i2 and i3 ,
size, the precision and the NEF of biomedical signal recording
i4 (Fig. 2) respectively in the Recombination output stage 1.
LNAs [7]. Several energy-efficient circuit topologies were in-
Similarly, Vout2+ and Vout2− are generated by summing i1 , i3 ,
troduced for that purpose, like the component sharing arrays [8],
and i2 , i4 in the Recombination output stage 2. The small signal
or the self-biased fully-differential structure [9]. Furthermore,
output currents are given by (1) to (4).
specific circuit techniques have been proposed to improve fur-
g  g 
ther the noise vs power tradeoff, such as folded cascodes with m1 m2
i1 = · Vin1+ + · Vin2+ (1)
low-current folds [8], reference electrode sharing [9], gm boost- 4 4
ing via current-splitting [10], and complementary inputs devices g   g 
m1 m2
i2 = · Vin1+ + − · Vin2+ (2)
[11] or back-gate driven devices [12]. Despite this progress that 4 4
is improving current techniques, an integrated AFE design scal-  g  g 
m1 m2
able to thousands of channels for collecting the signals of large i3 = − · Vin1− + · Vin2− (3)
4 4
groups of neurons at once is still missing.  g   g 
m1 m2
Recently, an orthogonal current-reuse structure has been i4 = − · Vin1− + − · Vin2− (4)
4 4
presented in [13] to improve previous techniques. Such an
orthogonal current-reuse structure is attractive since it yields
ultra-low power by properly operating under very low-voltage
B. Noise Analysis
supplies, without affecting the noise performance. Furthermore,
low-power consumption and robust crosstalk suppression The thermal noise density of a MOSFET can be approxi-
between the stacked amplifier parts makes the orthogonal mated by i2n = 4KT γgm where K is the Boltzmann constant
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REZAEI et al.: LOW-POWER CURRENT-REUSE ANALOG FRONT-END FOR HIGH-DENSITY 3

Fig. 2. A conventional two-stage folded-cascode current reused amplifier. Two stacked input differential pairs share a same bias current source and each
recombination output stage consumes B times the Ibias where B should be made smaller than 1. The common mode feedback circuits are also depicted.

(1.38 × 10−23 J/ K), T is the temperature in Kelvin, γ is a con- fewer transistors in the signal path compared to the conven-
stant (which approximately equals 2/3 in long-channel transistor tional topology shown in Fig. 2. Indeed, the conventional circuit
processes and 2∼3 in short-channel transistor processes [7]) and (Fig. 2) folds the currents i1 , i2 , i3 , i4 through M11∼14 , where
gm is the transconductance of the transistors. Considering a ra- the currents are being mirrored by M15∼18 towards the corre-
tio B:1 between M19∼26 and M15∼18 in the circuit shown in sponding output recombination stages. In the proposed circuit
Fig. 2, the thermal noise current contribution of all transistors (Fig. 3), the currents are mirrored directly by M7∼10 , which
at the output nodes Vout1 and Vout2 are avoids the utilization of M15∼18 , compared to the conventional
 folded-cascode topology. Therefore, the Itotal of this new circuit
i2n ,o1 = 4KT γ 2B 2 gm 1 + 4B 2 gm 7 + 4B 2 gm 15 is given by
+ 4gm 19 + 2gm 35 ) , (5) Itotal = Ibias + N · IRecomb = Ibias (1 + N · B) , (10)

i2n ,o2 = 4KT γ 4B 2 gm 3 + 4B 2 gm 7 + 4B 2 gm 15 where N is the number of stacked inputs requiring as much
+ 4gm 23 + 2gm 37 ) . (6) recombination stages, N · I Recomb is the total supply current of
the recombination stages, and B = (I Recomb /I bias ). Thus, Itotal
As mentioned above, since the size of M3 is half of M1 , and can approach Ibias if a sufficiently small ratio B is used. As for
the drain current of M3 is half of M1 , gm 3 has half the value of noise analysis of this new proposed circuit, we set a ratio of B:1
gm 1 (gm 1 = 2gm 3 ). Hence, the input-referred noise is obtained between M11∼18 and M7∼10 in Fig. 3 to find the output current
as follow noises of circuit branches 1 and 2:
  
2 8KT γ 2gm 7 2gm 15 2gm 19 gm 35 i2n ,o1 = 4KT γ 2gm 1 + 4gm 7 + 4B 2 gm 11
Vn ,in1 = 1+ + + 2 +
gm 1 gm 1 gm 1 B gm 1 B 2 gm 1 
(7) + 2B 2 gm 27 , (11)
  
8KT γ 2gm 7 2gm 15 2gm 23 gm 37 i2n ,o2 = 4KT γ 4gm 3 + 4gm 7 + 4B 2 gm 15
Vn2,in2 = 1+ + + + 
2gm 3 2gm 3 2gm 3 2B 2 gm 3 2B 2 gm 3 + 2B 2 gm 29 . (12)
(8)

It can be shown that Vn2,in2 = Vn2,in1 if (W/ L)3 and (W/ L)4 Hence, dividing (11) and (12) by the gain of the LNA gives
are equal to 1/ 2(W/ L)1 . In addition, it can be shown that the the input-referred noise:
total supply current Itotal can be expressed by  
2 8KT γ 2gm 7 2gm 11 gm 27
Itotal = Ibias + Im irror + N · IRecomb = Ibias Vn ,in1 = 1+ + 2 + 2 , (13)
gm 1 gm 1 B gm 1 B gm 1
+ Im irror (1 + N · B) , (9)  
8KT γ 2gm 7 2gm 15 gm 29
Vn2,in2 = 1+ + + .
where Imirror and IRecomb are the currents flowing in the current 2gm 3 2gm 3 2B 2 gm 3 2B 2 gm 3
mirror (Fig. 2) and the recombination output stage, respectively. (14)
The total current can be approximated to Itotal = Ibias + Imirror
As for the conventional circuit, it can be shown that Vn2,in2 =
if B is chosen significantly small.
Vn2,in1 if (W/ L)3 and (W/ L)4 are equal to 1/ 2(W/ L)1 . In these
conditions, it can be seen that the proposed design has less input
C. Proposed Current-Reuse Amplifier Design
referred noise compared to the conventional circuit shown in
We propose a new current-reuse structure based on a sim- Fig. 2, the noise of which is given by (7) and (8). Additionally,
plified current-mirror topology (shown in Fig. 3) which uses its power consumption is reduced since the Imirror formed by
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4 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

Fig. 3. The proposed optimized current reused amplifier circuit. A two-stage current mirror-based current-reuse amplifier topology uses less transistors than
previous topologies. The current mirrors at the input of the recombination output stages scale the output current of the stacked input pairs by a factor of B.

Fig. 4. Schematic of the implemented four stacked-input stage using the proposed optimized current reused amplifier circuit. In this design, W p = 1000 μm,
L p = 0.8 μm, W n = 80 μm, L n = 4 μm, Ibias = 2.5 μA.

Increasing the number of stacked inputs by 2 compared to the

Fig. 5. The recombination output stage for one of the outputs related to the
four-stacked input LNA (Fig. 4). In this design, W p = 80 μm, L p = 4 μm,
W n = 80 μm, L n = 4 μm, L = 1 μm, B = 1/8.
transistors M15∼18 in Fig. 2 are removed in this new design
(Fig. 3).
D. Current-Reuse AFE Design
We used this improved current-reused amplifier circuit to
implement a new advanced neural recording AFE including a
four-channel LNA and a four-channel PGA (Figs. 4 and 5).
circuits of Figs. 2 and 3 gives 4 times additional output currents
to be mirrored and recombined in the output stages. In fact,
there are 2n output currents for n input stacked pairs (or stacked
stages). Thus, this four-stacked input current-reuse structure has
16 individual currents that must be recombined (Fig. 5) in the
output stages to provide appropriate output signal voltages.
Although the complexity of the current-reuse amplifier circuit
schematic increases exponentially with the number of stacked
inputs, it can be shown that the complexity of its physical layout
implementation is comparable to a regular LNA with matched
transistors. Indeed, to decrease 1/f noise, LNA are typically
using large input MOSFET, the size of which typically domi-
nates the overall chip area of the circuit. These input devices
are typically split into several smaller matched devices (often
using finger structures) connected in parallel to achieve better
matching and better small signal performance. The proposed
current-reuse LNA must use large input MOSFET equivalent-
size as well to limit noise. These MOSFET are split into several
devices across the tree structure, and connected together in a
specific fashion, using metal layers, to reflect the given circuit
schematic. Therefore, it can achieve equivalent chip area as a
regular LNA with matched transistors. Of course, the proposed
design has additional complexity at the level of the metal layer
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REZAEI et al.: LOW-POWER CURRENT-REUSE ANALOG FRONT-END FOR HIGH-DENSITY
Fig. 6. Block diagram of the proposed analog front-end, which includes four
stacked current-reuse low-noise amplifiers (LNA) and programmable gain am-
plifiers (PGA). The analog multiplexer and outputs analog buffers are also
shown.
interconnections, but this represents minor overhead compared
to a well-matched regular LNA design using split transistors in
the differential pair.
Besides, it should be noted that once the number of stacked
inputs of the proposed amplifier have been determined, the num-
ber of channels of an AFE can be increased further simply by
repeating the given current-reused tree structure, the complexity
of which increases linearly with the number of inputs.
On the other hand, while the complexity of the physical im-
plementation can be comparable to a regular LNA with matched
input transistors, it can be seen that the power consumption of
the tree structure remains constant as the number of stacked
input channel is increasing, which is a desirable feature for this
application
A common-mode feedback (CMFB) circuit must be used to
stabilize the output common mode voltage of the fully differen-
tial output stage. Such a CMFB (Fig. 5) is sampling the output
common mode voltage through two high-value resistors (im-
plemented with pseudo-resistors [4]), and then compares the
sampled voltages with VCM , the desired common mode voltage
value, through a none-inverting single-ended differential pair
which generates the required bias voltages for M27∼30 .
The proposed 4-channel AFE using the new current-reuse
structure is illustrated in Fig. 6. It uses two four-channel current-
reuse structures for implementing four LNAs and four 2nd stage
amplifiers at once. As shown in Fig. 6, these current–reuse
structures allow reusing the same current sources to supply four
5
Fig. 7. (a) The proposed LNA design with the implemented T-network.
(b) The equivalent circuit. The parasitic capacitor from input transistors are
shown as C P .
LNAs at once with I1 and four PGAs at once with I2 . In order
to maintain identical gate-to-source voltages in all stacked input
transistors, each stacked input differential pair is biased at a
particular bias voltage, as shown in Fig. 6. Bias voltages Vbi are
shown in Fig. 6, where i is a number between 1 to 4 representing
the channel order in the stack. For example, the common mode
DC voltage at the input of the 1st stage Vb1 (Fig. 4), is set to
Vgs1 + Vds bias , while the common mode DC voltage at the input
of the 2nd stage Vb2 (Fig. 4), is set to Vgs2 + Vds1 + Vds bias , and
so on.
To minimize the inter-channel cross talk in this design, it is
critical to match all transistors in the differential pairs and in the
current mirrors of the recombination circuits [13]. The common
centroid technique was used in the physical implementation
to improve matching. For common centroid symmetry, the B
ratio is chosen equal to 1/8 so it allows putting most of the
current in the input stacked differential pairs to improve noise
performance.
E. Parasitic Input Capacitors Analysis
Due to the small amplitude and wide range of the differ-
ent neural signal modalities (i.e., action potentials are between
50 μV and 500 μV, while the local field potentials can be as high
as 5 mV [7]), this application requires an AFE providing a wide
input range and a programmable gain, ranging from several hun-
dred to a few hundreds of V/V. A capacitive feedback amplifier
topology is employed in this LNA design (Fig. 6). The gain of
the LNA is set by the capacitor ratio CIN /Ceqf . Thus, achieving
high gain with this topology requires either using large CIN ,
which can lead to large die area, or small Ceqf , which can lead
to high sensitivity to mismatch and process variations. There-
fore, a T-network capacitive structure [15] is used in this design
to provide small capacitors in the feedback network while using
bigger capacitor values, which are less sensitive to mismatch.
Such a T-network is shown in Fig. 7 along with the parasitic in-
put capacitors of the AFE. The T-network equivalent feedback
capacitor Ceqf is derived in [15]. For an accurate design, the
effect of equivalent capacitors Ceqi and Ceqo must be taken into
account. Otherwise, it can degrade the gain and change the cut-
off frequency of the low-pass filter. The equivalent capacitors
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6 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

of the T-network are given by

Cu Cu
Ceqf = and Ceqi = Ceq o = , (15)
M +2 1 + M2
where M is the number of unit capacitors used in the shunt ca-
pacitor (M Cu ). In this design, 7 pF is used for CIN and 0.5 pF
is used for Cu with M = 4, which leads to a gain of approx-
imately 38.5 dB in the LNA. However, there is an attenuation
factor of 0.67 in this design due to the capacitive voltage divider
formed by CIN and the input parasitic capacitance Cp resulting
from the gate-to-source capacitance of the huge input transistors
employed in the differential pairs [4] and Ceqi of the T-network
(shown in Fig. 7(b)). Therefore, the total gain of the LNA, the
value of which is 35 dB, is given by
CIN CIN
GainLNA = · , (16) Fig. 8. The minimum NEF versus the number of stacked differential inputs for
Ceqf CIN + Cp + Ceqi + Ceqf different B factors. With B = 1/ 8 and N = 4, this design achieves a theorical
NEF of 1.237.
where, Cp is the parasitic capacitance of the input transistors
M1∼6 in Fig. 4, which forms a gain attenuation factor with
Then, using (10), the NEF is given by
CIN , Ceq i and Ceqf . In order to set the desired low pass cut-off 
frequency (fH ), CL is selected as follow 4γ (1 + N · B)
NEF = (21)
gm 1 · Ceqf N ·k
fH = . (17)
2π · (2CL + Ceq o ) · CIN for sufficiently small B ratios, such that the supply current of the
recombination stages IRecomb is much smaller than Ibias , Itotal in
(19) can be approximated by Ibias divided by N, since Ibias is used
to bias N differential input pairs at once. Under these conditions,
F. Implementation of Current-Reuse PGA
the NEF of the proposed current-reuse LNA simplifies to
The PGA shown in Fig. 6 is based on a capacitive feedback 
amplifier topology as well. The gain of the PGA is set by the 4γ
NEF = = 1.01, (22)
capacitor ratio CC /Cf i , which is programmable by selecting N ·k
different values for Cf through two transmission gate switches where k = 1/2γ = 0.7 in subthreshold regime [7]. Then, the
controlled by a 2-bit decoder and digital inputs D1 , D0 . The minimum NEF that can be achieved with a 4-channel LNA
selectable capacitor values for Cf (C f 1 , Cf 2 , Cf 3 ) are shown (N = 4) based on the proposed current reuse circuit with four
in Fig. 6. Therefore, the total gain of the AFE, including the stacked input differential pairs, is found to be 1.01, for small
gains of the LNA and the PGA, is described in (18). B factors. The NEF is given in Fig. 8 for different values of B
CIN Cc CIN and N. As it can be seen in (21), for small B ratios, the NEF
GainAFE = · · . (18) can be decreased further by increasing
√ the number of stacked
Ceqf Cf i CIN + Cp + Ceqi + Ceqf
input pairs according to 2.02/ N . For instance, an LNA with
5 stacked inputs using a very small B ratio would allow for
G. Noise and Power Efficiency Factors Analysis a minimum NEF of 0.9 with the proposed topology. A com-
The noise efficiency factor (NEF) [16] is a common figure of parison with previously reported LNA topologies shows that
merit used to compare different LNA circuit topologies working the proposed current-reuse LNA circuit achieves the best min-
in the baseband at low frequencies [4]. It is calculated as follow: imum theoretical NEF compared with other circuits, like the
 folded cascode amplifier in [7], and the complimentary differen-
2 · Itotal tial pair-amplifier in [17], which achieved minimum theoretical
NEF = Vrm s,in , (19)
UT · π · 4KT · BW NEF of 2.02 and 1.41, respectively.
where Vrm s,in is the total input referred noise, UT is the thermal As seen above, an efficient design requires that the total cur-
voltage, Itotal is total supply current of the LNA and BW is rent Itotal approaches Ibias as much as possible, requiring a
the desired bandwidth. If gm 1 is made big enough in (13), such small B ratio, which imposes that the supply current flowing
that gm 7 , gm 11 and gm 27 can be neglected, and gm is approx- into the recombination output stages IRecomb , be kept negligi-
imated to kId /UT for M1 and M2 biased in the subthreshold ble compared to Ibias , the current flowing in the stacked in-
region for providing maximum gm /Id ratios [7], Vrm s,in can be puts. In this design, which has 4 recombination stages to ac-
obtained by commodate 4 stacked input stages, the ratio IRecomb /Ibias =
 B equals 1/8. Hence, according to (10), the total current is
8 · KT γ · UT π Itotal = Ibias (1 + 4 · 1/8) = 1.5Ibias , which is 1.5 times larger
Vrm s,in = · BW . (20) than the lowest Itotal considered in (22) for this circuit. In
kId1 2
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REZAEI et al.: LOW-POWER CURRENT-REUSE ANALOG FRONT-END FOR HIGH-DENSITY 7

Fig. 10. Frequency responses (gain and phase) of the AFE for the 4 channels.
Fig. 9. Die photograph of the 4-channel analog front-end fabricated in a
TSMC CMOS 180-nm process.

addition, the capacitive voltage divider in (16), which is due

to the parasitic capacitances at the input of the LNA, contributes
to slightly degrading the theoretical NEF (see Section II-E). As
detailed in Section II.E, the attenuation factor caused by the volt-
age divider in (16) equals 0.67 in this design. When including
the gain attenuating factor (see Section II-E), the input-referred
becomes

CIN+C p +C e q i +C e q f 8 · KT γ · UT π
Vrm s,in = · BW . (23)
CIN kId1 2
Considering all these practical factors, a NEF of 1.83 is fore-
casted for a practical circuit prototype.
The power versus noise tradeoff achieved by this design can
also be assessed using the Power Efficiency Factor (PEF) [18],
which is given by
Fig. 11. The different measured gain values for one channel in the AFE.
2Vrm s,in 2 VDD · Itotal
PEF = = VDD · N EF 2 , (24)
UT · π · 4KT · BW
where VDD is the power supply voltage, which equals 1.8 V in 35.04 dB, 43.1 dB and 49.5 dB through a selectable gain (as
this design. Therefore, the minimum theoretical PEF that can be shown in Fig. 11), with a 0.7-Hz high-pass corner frequency
achieved by this proposed design equals 1.83, when very small B and a 10-kHz low-pass corner frequency. The proposed AFE
ratios are used, and when the effect of parasitic input capacitors has an input range of 4.5 mV at maximum gain, while it has an
is neglected. With B = 1/ 8, N = 4, and an attenuation factor input range of 24 mV at minimum gain. In Fig. 11 the measured
due to parasitic capacitors of 0.67, a practical PEF of 6.02 is gain variation across channels most likely come from the fact
expected for this design. that the input and feedback capacitors of each channel were
separately matched together to improve the CMRR of this fully
III. MEASUREMENT RESULTS differential circuit. Thus, capacitor matching inside each chan-
nel was favored in this design to the detriment of matching
The proposed 4-channel AFE was fabricated in a
across channel. For improved gain matching across channels, it
180-nm CMOS process from TSMC through CMC Microsys-
is recommended to provide capacitor matching across channels
tems (Kingston, ON). A photograph of the fabricated chip is
as well.
shown in Fig. 9. The dimensions of the whole AFE are of
The measured AFE input-referred noise density is shown in
800 μm × 540 μm.
Fig. 12. The thermal noise floor is of 60 nV/Hz from 1 kHz
to 10 kHz. The flicker noise, which is minimized by using large
A. Measured Performance
input transistors in all stacked input pairs in the LNA, has a
The measured AFE frequency response is shown in Fig. 10. corner frequency located at 200 Hz. The input referred-noise
The AFE in-band differential gain can be changed between integrated from 1 Hz to 10 kHz is of 3.2 μVrms for a power
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

TABLE I
SUMMARIZED PERFORMANCE OF THE LNA AND COMPARISON

Parameter (LNA) [13] [17] [19] [20] [21] This

work

Technology 130 nm 180 nm 130 nm 90 nm 65 nm 180 nm

Topology Current- Comp. Comp. Single- Bulk Current-
reuse inputs inputs ended switching reuse
VDD (V) 1.5 1.8 1.2 1 1.2 1.8
Power/ch. (μW) 0.80 2.5 1.92 2.85 3.96 4.5
Noise (μVrms) 3.6 2.85 3.8 3.04 2.64 3.2
BW (kHz) 19.9 10 7.2 10 6 9.3
Gain (dB) 36.1 34.1 46 58.7 39 35.04
PSRR (dB) 80 67 75 50 – 80
CMRR (dB) 78 80 85 45 88 76
THD @ 1mVp −p (%) 1.0 ∗ 0.07 0.08∗∗ 1.6 – 0.07
ICRR (dB) 40 – – – – 54
Area/ch. (mm2 ) 0.031 – – 0.137 0.053 0.072
NEF 1.64 1.58 2.16 1.93 2.4 1.94
Fig. 12. Measured AFE input referred noise when the input of the AFE is PEF 4.03 4.49 5.59 3.7 6.91 6.77
shorted.
∗
The THD is provided for a 16.5-mVp −p input.
∗∗
The THD is provided for a 3-mVp −p input.
consumption of 4.5 μW per channel in the LNA, corresponding
to a NEF of 1.94, which is close to the expected value calculated
in Section II-E, while occupying a chip area of 0.072 mm2 . For
a fair comparison with other designs, the NEF is provided with
a gain attenuation of 0.67 included, which is produced by the
parasitic capacitance at the input of the LNA. The proposed
design achieves a NEF of 1.3 without considering the gain
attenuation. Note that the total input-referred noise of the AFE
is approximately equal to the input-referred noise of the LNA.
To assess the crosstalk performance of the proposed AFE, we
measured the Inter-Channel Rejection Ratio (ICRR), which
equals 54 dB. The ICRR is defined as follow
Vout x,y
ICRR = 20 · log10 , (25)
Gainx · Vin y
where Vout x,y is the signal measured at the output of a given
channel (Channel x), while a signal is connected at the input
of another channel (Channel y), and all other channels are Fig. 13. The in-vivo test setup is performed at the (CRIUSQ) on an anes-
grounded. Vin y is the value in volt of the input signal connected thetized 23 g mouse.
to Channel y, and parameter Gainx is the gain value of Channel
x. For this measurement, 1) we selected the maximum gain
proposed current-reuse AFE design would consume only 9 mW,
(i.e., 49.5 dB) of the LNA, 2) we gave an input sinewave
and occupy 1.01 cm2 .
Vin y = 4 mV at 1 KHz to Channel y, 3) and we measured
the output signal at the output of another channel (Vout x,y ).
B. In-Vivo Recording Results
The implemented design has a THD of 0.07% for a 1-kHz single
tone, 1-mVp−p input test signal. Additionally, the proposed The fabricated AFE chip has been used to perform in-
design has a PEF of 6.77, which is close to the theoretical vivo recordings at the Quebec Mental Health Research Insti-
values calculated in Section II-G. tute (CRIUSMQ). The in-vivo experimental setup is shown in
For convenience, the same bias current value was used for the Fig. 13. In this setup, the fabricated chip is used to collect neu-
LNA and for the PGA. Note that the bias current of the PGA ral signals from the brain of an anesthetized mouse weighting
could be decreased without significant impact on the input- 23 g. Ketamine and Xylazine with dosage of 100 mg/kg and
referred noise, since it deals with amplified signals. 10 mg/kg, respectively are used to anesthetize the animal. A
Table I summarizes the measurement results from LNA and reference node is connected under the skin of the animal and
compares the proposed design with most recent reported works. four tungsten electrodes with diameter of 75 μm are located in
As it can be seen, its low-power and small size performance the Hippocampus (2.5 mm depth) of the mouse. The electrodes
makes this proposed AFE scalable to very high channel counts have a tip resistance of approximately 8 MΩ. Fig. 14 shows ex-
for implementing high-density multichannel neural record- amples of neural signals recorded from the four implanted elec-
ing systems. For instance, a 1000-channel system using this trodes, and sampled at 20 ksps. The output spike signals have
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
REZAEI et al.: LOW-POWER CURRENT-REUSE ANALOG FRONT-END FOR HIGH-DENSITY
Fig. 14. (a) Recorded neural activity of each AFE channel from the hippocam-
pus of a mouse. (b) 135 similar action potentials isolated from the recorded
waveform and aligned (waveforms are referred to the amplifier input).
amplitudes as high as 300 μVp−p , which makes them easily de-
tectable from the background noise. Fig. 14(b) shows 135 spikes
that have been isolated from one recorded signal with the AFE
and aligned. All protocols were performed in accordance with
the Canadian Council on Animal Care Guidelines.
IV. CONCLUSION
We presented a new current reuse structure which improves
previous current reuse topologies with less input referred noise
and less power consumption. A four-channel analog front-end
has been implemented based on this proposed structure and
fabricated in a CMOS 180-nm technology. Analysis show that
this new four stacked current reuse structure can theoretically
achieve a NEF as low as 1.01. In addition, the utilization
of a capacitive T-network feedback circuit was discussed in
9
detail to enhance the gain accuracy of the AFE. The total mea-
sured power consumption of the whole front-end including an
LNA and a variable gain stage is 9 μW (4.5 μW for LNA and
4.5 μW for PGA), with an input referred noise of 3.2 μVrms ,
while occupying a die area of 0.072 mm2 per channel. The fab-
ricated chip was verified in-vivo and succeeded to record spikes
of amplitudes as low as 300 μVp−p from the hippocampus of a
23-g anesthetized mouse.
ACKNOWLEDGMENT
The authors acknowledge the design and testing tools from
CMC Microsystems.
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Masoud Rezaei (S’09) received the B.S. degree in
electrical engineering from Hakim Sabzevari Univer-
sity, Sabzevar, Khorasan Razavi, Iran, in 2006, the
M.S. degree in electrical engineering from Ferdowsi
University of Mashhad, Mashhad, Khorasan Razavi,
Iran, in 2010, and is currently working toward the
Ph.D. degree at Microelectronic Lab, Laval Univer-
sity, Quebec, Canada. His research interests include
low-power implantable biomedical circuits, wireless
implantable biomedical systems, data converters in-
tegrated analog circuit design, and wireless data
transmission.
Esmaeel Maghsoudloo (S’09) received the B.S. de-
gree in biomedical engineering from Sahand Univer-
sity of Technology, Tabriz, East Azerbaidjan, Iran,
in 2007, the M.S. degree in electrical engineering
from Ferdowsi University of Mashhad, Mashhad,
Khorasan Razavi, Iran, in 2011, and is currently
working toward the Ph.D. degree at Microelectronic
Lab, Laval University, Quebec, Canada. His research
interests include low-power implantable biomedi-
cal circuits, wireless implantable biomedical sys-
tems, data converters integrated analog circuit design,
and wireless power and data transmission.
Cyril Bories received the Ph.D. degree in neuro-
science from Laval University, Ville de Québec, QC,
Canada, in 2013. He is currently an Assistant Project
Scientist at the Mental Health Institute of Quebec,
Quebec, Canada and the Canadian Neurophotonics
Platform, Quebec, Canada. His research interests
range from fundamental neuroscience to new tech-
nologies in neuroscience to decipher the neurobiolog-
ical processes underlying neurological diseases with
a special emphasis on aging, Alzheimer’s disease,
and chronic pain.
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Yves De Koninck, a Professor of psychiatry and neu-
roscience at Laval University, Laval, QC, Canada, is
a world-leading expert in neurophysiology and op-
tical technologies applied to neuroscience, as well
as a Leader of the Neurophotonics Center, Laval
University (www.neurophotonics.ca), where research
in neuroscience drives the development of innova-
tive new optical technologies. He was the Found-
ing Scientific Director of the Quebec Pain Network
from 2002 to 2014 and the former President of the
Canadian Association for Neuroscience from 2010 to
2012). He is the Scientific Director of Quebec Mental Health Institute. He has
made important contributions to the understanding of synaptic transmission in
the brain and spinal cord especially as they pertain to epilepsy, chronic pain,
and neurodegenerative diseases associated with aging. Recently, he discovered a
novel mechanism underlying neuropathic pain syndromes (Nature 2003, 2005)
involving a neuroimmune interaction responsible for neuronal hyperexcitability
in the spinal cord. This led to three patents and the creation of a startup company
for the development of novel analgesics. He has expertise in synaptic physiol-
ogy, biophysics, neuroanatomy, in vivo electrophysiology, cellular imaging and
multiphoton microscopy, neuroinflammation, behavioral testing, optogenetics,
sensory mechanisms, chronic pain, and cognitive function. He was the recipient
of the Jacques Rousseau Prize from ACFAS for multidisciplinarity in 2013.
He is a Project Leader of the CIHR Neurophysics Training Program Grant. He
has served on multiple advisory boards for Natural Sciences and Engineering
Research Council of Canada, Canadian Institutes of Health Research, Fonds
de recherche du Québec – Santé, the NSF Centre for Biophotonics Science
and Technology, the University of New England, University College London,
and the Centre de Psychiatrie et Neuroscience de Paris. He is a Fellow of
the Canadian Academy of Health Sciences and the Royal Society of Canada
and a Member of the Centre d’Optique, Photonique et Laser, Université Laval,
Quebec, QC, Canada.
Benoit Gosselin received the Ph.D. degree in elec-
trical engineering from École Polytechnique de
Montréal, Montreal, QC, Canada, in 2009. In 2010,
he was an NSERC Postdoctoral Fellow at the Georgia
Institute of Technology. He is currently an Associate
Professor at the Department of Electrical and Com-
puter Engineering, Université Laval, Quebec, QC,
Canada, where he is the Head of the Biomedical Mi-
crosystems Lab. His research consists of developing
innovative microelectronic platforms to collect and
study brain activity through advanced multimodal
bioinstrumentation and actuation technology. His research interests include
wireless microsystems for brain computer interfaces, analog/mixed-mode and
RF-integrated circuits for neural engineering, interface circuits of implantable
sensors/actuators, and point-of-care diagnostic microsystems for personalized
healthcare. He is an Associate Editor of the IEEE Transactions on Biomedical
Circuits and Systems and a Chair and Founder of the Quebec IEEE CAS/EMB
Chapter (2015 Best New Chapter Award). He has served on the committees
of several international conferences such as IEEE BIOCAS, IEEE NEWCAS,
IEEE EMBC/NER, and IEEE ISCAS, and he is currently serving on the commit-
tees of the IEEE ISCAS’16 and the IEEE NEWCAS’16. In addition to receiving
several awards, such as the 2015 Mitacs Award for Outstanding Innovation –
Master’s and the IEEE BioCAS’15 Best Paper Award, his contributions has led
to the commercialization of the first wireless electronic implant to combine op-
togenetics and large-scale brain monitoring capabilities within a single device,
with partner Doric Lenses Inc.