Analytical Methodology of Tree Microstrip Interconnects Modelling For Signal Distribution

Blaise Ravelo Editor
Analytical
Methodology
of Tree Microstrip
Interconnects
Modelling For
Signal Distribution
Voltage Transfer Function and S-parameter
Analyses
Analytical Methodology of Tree Microstrip
Interconnects Modelling For Signal Distribution
Blaise Ravelo
Editor
Analytical Methodology
of Tree Microstrip
Interconnects Modelling
For Signal Distribution
Voltage Transfer Function and S-parameter
Analyses
123
Editor
Blaise Ravelo
ESIGELEC Graduate School of Engineering
Sotteville-lès-Rouen, Seine-Maritime
France
ISBN 978-981-15-0551-5 ISBN 978-981-15-0552-2 (eBook)

https://doi.org/10.1007/978-981-15-0552-2
© Springer Nature Singapore Pte Ltd. 2020
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Preface
The present book introduces a fast analysis and modelling of the printed circuit
board (PCB) arbitrary shape interconnect. The developed methods are based on the
consideration of interconnect elementary transmission line. The methodology is
essentially built with the combination of circuit, signal and transmission theory. The
materials presented in the book constitute basic tools to solve the electronic PCB
problematics regularly exposed to graduate students, academic researchers and
industrial engineers. Efficient way to elaborate the electrical topology equivalent to
tree behaved interconnect structure is developed. Analytical approach enabling to
determine the fundamental parameters as Z and Y and T and S-matrices is detailly
explored. Sensational methodology to establish the analytical answer about the
additional problematic related to the interbranch coupling of non-symmetric
interconnect PCB is also established. The feasibility of the analysis and modelling
methodology is verified with microstrip interconnect structures.
These research works have been implemented within the frame of the “Time
Domain Electromagnetic Characterization and Simulation for EMC” (TECS) pro-
ject 2009–2013 which is part-funded by the Haute-Normandie Region (FRANCE)
and the ERDF via the Franco-British Interreg IVA programme No 4081.
Acknowledgement is made to the Upper Normandy Region for the PULSAT
2013–2015 project support of this research work through the FEDER fund.
Acknowledgement is made to the Normandy Region for the BRIDGE project
support of this research work through the FEDER fund.
Sotteville-lès-Rouen, France Blaise Ravelo
v
Contents
1 General Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Blaise Ravelo
2 Basic Analysis of Single-Input Single-Output (SISO) PCB
Interconnect Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thomas Eudes and Blaise Ravelo
3 Discrete Periodical Model of Microstrip Line with Cascaded
Elementary L-Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Blaise Ravelo and Lala Rajaoarisoa
4 Modelling of the Signal Delay Induced by PCB Interconnect
SISO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Blaise Ravelo and Thomas Eudes
5 Analytical Modeling Methodology of Single-Input
Multiple-Output (SIMO) Symmetric Tree Interconnects
by Using Lumped Element L-Cell . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Blaise Ravelo
6 Symmetric Tree Interconnects Modeling with Elementary
Distributed RC-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Blaise Ravelo
7 Z/Y/T/S-Matrices’ Modelling of Symmetric SIMO Structure
Based on Elementary Distributed RLC-Cell . . . . . . . . . . . . . . . . . . 117
8 Z/Y/T/S-Matrices’ Analysis of Non-symmetric SIMO Tree Based
on Elementary Distributed Element . . . . . . . . . . . . . . . . . . . . . . . . 137
Thomas Eudes, Blaise Ravelo, Thierry Lacrevaz and Bernard Fléchet
9 Cartographical Analyses of Reflection and Transmission
Coefficients of Shunt Coupled Lines . . . . . . . . . . . . . . . . . . . . . . . . 167
Blaise Ravelo
vii
viii Contents
10 Analytical Modelling of Interbranch Coupling Effect on Coupled

Microstrip Tree PCB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . 191
Blaise Ravelo
11 Temperature Effect Analysis on Microstrip Structure . . . . . . . . . . . 215
Blaise Ravelo, Atul Thakur, Ashish Saini and Preeti Thakur
12 General Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Blaise Ravelo
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
About the Author
Dr. Blaise Ravelo is currently an Associate Professor at the Graduate Engineering

School, ESIGELEC located in Rouen, France. His research interest is focused on:
• the design of RF/microwave circuits for wireless communication system,
• development and applications of negative group delay (NGD) circuits,
• the electrical RF/mixed circuit interconnect modelling for signal and power
integrity (SI/PI) analysis,
• EM near-field scanning and modelling, electromagnetic compatibility/
interference (EMC/EMI), and Multiphysics system engineering/modelling.
He is a pioneer of the development of NGD concept. He received the Dipl.-Ing.
Degree in electronic engineering from the University of Antsiranana, Madagascar,
in 2000. He received the Professional/Research Sci. Master degrees, and the Ph.D.
degrees from Brest University, Brest, France, in 2004, 2005, and 2008, respec-
tively. He hold his degree of dissertation to lead researches (“HDR: Habilitation à
Diriger des Recherches”) from the Univ. of Rouen in 2012.
He is regularly involved and initiated to participate and to lead national and
international research projects (FP7, INTERREG, ANR, FUI, H2020, Euripides,
Eurostars…) on the electronic, microwave, and EMC engineering. He is (co)author
of more than 210 papers published in international journals, chapters, and confer-
ence proceedings. He co-supervised and directed nine Ph.D. students whose six
Ph.D. candidates defended. His current publication h-index is 17 (Reference:
Google Scholar 2018).
He is the Scientific Chair of the 5th International Conference on Electromagnetic
Near-Field Characterization and Imaging (ICONIC 2011, http://iconic.esigelec.fr),
member of the IEEE RADIO 2015 scientific committee (http://www.radiosociety.
org/radio2015/). He was been IEEE member since 2007, URSI member and regu-
larly invited to review papers submitted to international journals (Ieee Transactions
On Microwave Theory And Techniques, Ieee Transactions On Circuits And Systems,
Ieee Transactions On Electromagnetic Compatibility, Ieee Transactions On
ix
x About the Author
Instrumentation & Measurement, Ieee Transactions On Industrial Electronics,

Journal of Electromagnetic Waves and Applications, IET CDS, IET MAP and
International Journal of Electronics…) and international books (Wiley, Intech
Science…).
Abbreviations
2D Two dimensions
3D Three dimensions
2.5G/3G/4G Mobile phone generations
AC Alternative current (generally used for the frequency analysis)
ADS® Advanced Design System® (Simulation tool from Keysight
(ex-Agilent®) Technologies®)
BGA Ball grid array
BW Bandwidth
CMOS Complementary metal-oxide semiconductor
CPL Coupled-parallel-line
CPU Computer processor unit
CTL Coupled transmission line
CST® Computer Simulation Technology® (Simulation tool from Dassault
Aviation®)
CTF Current transfer function
Cu Copper
CUT Circuit under test
DC Direct current
DDR Double data rate
DIMM Dual inline memory module
EM Electromagnetic
EMC Electromagnetic compatibility
EMDS® Electromagnetic Design System® (Simulation tool from Keysight
Technologies®)
EMI Electromagnetic interference
FEXT Far-end cross talk
FFT Fast Fourier Transform
FR4 Epoxy dielectric substrate (In this book, used to build the microstrip
line)
xi
xii Abbreviations
HFSS® High Frequency Solver Simulator® (Simulation tool from

ANSYS®)
IC Integrated circuits
IFFT Inverse Fast Fourier Transform
IUT Interconnect under test
ITRS International Technology Roadmap for Seminconductors
LTCC Low-temperature co-fired ceramics
LUT Line under test
MCM Multi-chip module
MMIC Monolithic microwave integrated circuit
MoM Method of moment
MOS MetalOxide Semiconductor
NEXT Near-end cross talk
NGD Negative group delay
PC Personal computer
PCB Printed Circuit Board
PEN Poly ethylene naphtalate
PLL Phase-locked loop
PI Power integrity
PiP Package in package
POC Proof of concept
PoP Package on package
RC Lumped elementary cell (implemented in L-topology) constituted
by a series resistor R and a parallel capacitor C
RLC Lumped elementary cell (implemented in L-topology) constituted
by a series resistor R and inductor L and a parallel capacitor C
RLCG Lumped elementary cell (implemented in L-topology) constituted
by a series RL series network and a parallel capacitor C and
conductor G (CG parallel network)
RF Radio frequency
Rx Receiver
RZ Reflection zero
[S] Scattering matrix
SDRAM Synchronous dynamic random-access memory
SI Signal integrity
SIMO Single-input multiple-output
SiP System in package
SISO Single-input single-output
SoC System on chip
SOLT Short Open Load Thru (VNA calibration technique)
SPICE Simulation Program with Integrated Circuit Emphasis (Circuit
simulation language/tool)
[T] Transfer or ABCD or chain matrix
TEM Transverse electromagnetic
TL Transmission line
Abbreviations xiii
Tx Transmitter
TZ Transmission zero
UWB Ultra-Wide Band
VNA Vector Network Analyzer
VLSI Very large system integration
VTF Voltage transfer function
[Y] Admittance matrix
[Z] Impedance matrix
Chapter 1
General Introduction
Blaise Ravelo
1.1 Preliminary Introduction
To meet the public and industrial needs, the printed circuit boards (PCBs) must oper-
ate with the higher speed and design density. With the increase of the data speed and
the design complexity, the interconnect effect becomes the dominant factor of signal
degradation. The present book addresses a basic methodology to analyse the printed
circuit board electrical interconnects. The chapters elaborate the different analyti-
cal methodologies suitable to the interconnect modelling. The methods are applied
from the simplex cases of typically single-input single-output (SISO) to complex
cases of single-input multiple-output (SIMO) structures. The SIMO interconnects
are represented as tree networks.
1.2 Analysis Methodology of PCB Electrical Interconnects
The analysis presented in Chaps. 2, 3 and 4 is based on the signal, circuit, system
and transmission line (TL) theories. The methodology explored is fundamentally
based on the equivalent circuit approach of the PCB electrical interconnects. As
introduced in Chap. 2, the analysis can be performed in the frequency domain or
in the time domain in function of the input signal behaviour. The equivalent circuit
must be established in function of the operating signal bandwidth and the interconnect
physical parameters. The interconnects can be assumed as ideal connection wire or
lumped element-based circuits, or distributed TL structure. The distributed TLs are
basically defined by the characteristic and propagation constant parameters. The
lumped elements are essentially a L-topology cell composed of two-port impedance
B. Ravelo (B)
Graduate Engineering School, ESIGELEC, Sotteville les Rouen, Seine-Maritime, France
e-mail: blaise.ravelo@yahoo.fr
© Springer Nature Singapore Pte Ltd. 2020 1

B. Ravelo (ed.), Analytical Methodology of Tree Microstrip Interconnects
Modelling For Signal Distribution, https://doi.org/10.1007/978-981-15-0552-2_1
2 B. Ravelo
and two-port admittance. In the other words, the interconnect structure is equivalent
to electrical multiport system. In function of the number of output nodes, two types
of system are analysed in this book.
1.3 Z/Y/T/S Parameter of Single-Input Single-Output

(SISO) System
The SISO systems are two-port block diagrams whose one port is the input and
the other one is the output. Acting as electrical system, the analytical approach is to
elaborate the relation between the input and output currents and voltages. The relation
can be expressed analytical two-dimensional (2D) matrix approach. As developed
in Chaps. 2, 3 and 4, the analysis can be proceeded in the function of the unknown
variables and the interconnect configuration, with:
– The impedance or [Z] matrix,
– The admittance or [Y ] matrix,
– The transfer or chain or [T ] matrix,
– Or the scattering or [S] matrix.
In addition, the different signal integrity parameters as attenuation loss, propaga-
tion delay, rise-time, fall-time, under-shoot and over-shoot are estimated in fast way
in Chap. 4.
1.4 Analytical Modelling of Single-Input Multiple-Output

(SIMO) System
The interconnect structure is assigned as a SIMO system when it presents several

output nodes. The electrical equivalent is essentially constituted by elementary TLs
represented by the telegraphist model of cascaded RLCG cells. The RLCG cells
are characterized by its per unit length resistance R, inductance L, capacitor C and
conductance G. By proceeding with the reduction of electric schematic, the equivalent
SISO circuit between the input node and one output node can be established. As
reported in Chaps. 5, 6, 7 and 8, the modelling of this structure consists in establishing
the electrical path between the input–output nodes. To do this, a circuit reduction
technique named as SIMO to SISO transform is developed. Depending on the output
current and voltage behaviours, there are two different kinds of SIMO structure, the
symmetric-type and non-symmetric-type or asymmetric-type one. The elaboration
of the analytical model depends on these types of SIMO structure.
The methodology of the interconnect tree proposed in this book is performed in
the following steps:
1 General Introduction 3
– Step 1: Identification of the interconnect tree electrical topology and the consti-
tuting TL parameters,
– Step 2: Determination of the reduced circuit diagram via SIMO–SISO transform,
– Step 3: Equating the output currents and/or voltages in function of the input, and
analytical calculation and Z/Y /T /S-matrices,
– Step 4: Determination of current or voltage transfer functions (CTF and VTF).
1.4.1 Symmetric Tree
The symmetric interconnect trees present similar electrical responses at all output
nodes. The analyses of this symmetric-type tree-type are developed in Chaps. 5, 6
and 7. The modelling of symmetric-type tree constituted by lumped RC and RLC cells
is developed in Chap. 5. Analyses of multilevel symmetric tree constituted by RC
and RLC network cells are proposed. The modelling of symmetric tree constituted
by RC- and RLC-based distributed TLs is elaborated in Chap. 6 and in Chap. 7,
respectively.
1.4.2 Non-symmetric or Asymmetric Tree
The modelling of asymmetric type of interconnect trees is developed in Chap. 8.

Generally, the modelling is quite more complex than the symmetric case because
each output current and voltage behave differently. So, careful analysis must be
realized to perform the SIMO–SISO transform for the electrical paths between each
input–output link.
1.5 Analysis of PCB Interconnect Interbranch Coupling
Chapters 9 and 10 describe the analyses of coupling effect between interconnect

branches. The elaborated theoretical circuit is focused on the microstrip line cou-
pling effects. Analytical answers on deep questions about the interconnect as stub
effects onto the reflection and transmission zeroes (RZ and TZ) are presented. More
interestingly, the modelling of asymmetric-type tree with interbranch coupling effect
is also developed.
4 B. Ravelo
1.6 Analysis of Temperature Effect onto the PCB

Interconnect
Because of the conductor and dielectric material properties, the TL parameters are
particularly sensitive to the ambient temperature variation. Meanwhile, the tem-
perature can affect the PCB interconnect behaviours. Chapter 11 introduces an
empirical study illustrating how the microstrip line behaviour varies with the ambi-
ent temperature effect. The study is based on the empirical observation of the
S-parameters.
1.7 Outline of the Book Chapters
The present book is organized in ten main chapters:

– Chapter 2 is focused on the fundamental analysis of SISO PCB interconnect
structure,
– Chapter 3 presents the analysis of SISO structure by considering discrete periodical
model of microstrip line constituted by cascaded elementary L-cells,
– Chapter 4 develops the modelling of the signal delay induced by PCB interconnect
SISO structure,
– Chapter 5 develops the analytical modelling methodology of SIMO symmetric
tree interconnects by using lumped element L-cell,
– Chapter 6 is focused on the modelling of symmetric tree interconnects with
elementary distributed RC-line,
– Chapter 7 elaborates the modelling of symmetric SIMO structure based on
elementary distributed RLC-cell,
– Chapter 8 introduces the analysis of non-symmetric SIMO tree based on
elementary distributed element,
– Chapter 9 describes an innovative way to perform the cartographical analyses of
reflection and transmission coefficients of shunt coupled lines,
– Chapter 10 addresses the analytical modelling of interbranch coupling effect on
coupled microstrip tree PCB interconnects,
– Finally, Chap. 11 presents the ambient temperature effect analysis on the microstrip
structure.
Chapter 2
Basic Analysis of Single-Input
Single-Output (SISO) PCB Interconnect
Structure
2.1 Introduction
The last century was particularly remarkable with the spectacular progress of the
microelectronic semiconductor industries. This constant technological progress was
till now unique in the mankind history. It is nowadays a source of innovative product
developments in numerous civil sectors as the mobile phones, multimedia systems,
medical equipments and even vehicles. As an undeniable quantification of this indus-
trial development, according to Moore’s law prediction, at each generation the size
of electronic PCB is reduced of 30% and every two or three years, the number of the
transistors integrated in the microelectronic chips must be increased of four times
[1]. Despite this fascinating scenario of technological development, the structures
of the current interconnection circuitry between the logic gates, electronic chips and
digital devices, and even the buses linking the different electronic boards become
more and more complicated [2–7].
Furthermore, due to the incessant increase of the operating frequencies and the
integration density, the contributions of the interconnection electric parameters as the
resistance, capacitance and inductance effects [8–15] cannot presently be neglected
by the electronic equipment manufacturers. Indeed, the SI which represents the
numerical/digital data is not preserved especially for the high-rate communication.
This signal degradation effect needs to be taken into account by the electronic design-
ers during the manufacture processes of the high-speed electronic devices. For this
reason, different characterization techniques of the interconnection TL based on the
S-parameter extractions were introduced since two decades ago [16–21]. In this optic,
performance optimization methods dedicated to the clock tree distribution networks
were proposed [22–24] in order to minimize the undesired influences of intercon-
nection systems notably for the VLSI circuits. In addition, a compensation technique
T. Eudes · B. Ravelo (B)


6 T. Eudes and B. Ravelo
based on the insertion of repeaters between the piece of TLs was also proposed [11,
25] in order to reduce the TL interconnection negative effects. As improvement of
this interconnection compensation technique, an alternative solution based on the
use of negative group delay (NGD) circuits is introduced in [26, 27].
Notwithstanding these various technical solutions, further simpler, faster and more
accurate methods need to be developed to model the interconnection line effects espe-
cially for the complex circuitry especially, in transient domain. One underlines that
most of existing characterization methods were developed only in frequency domain
by using the S-parameter characterization deduced from the geometrical parameters
(width, length, substrate height) of the TL and the electromagnetic properties (dielec-
tric permittivity and metal resistivity) [16–20, 28]. Whereas the existing time-domain
characterization methods are usually based on the use of the classical RC or RLC
transfer function models [8–15, 29]. So, more complete modelling method is still
necessary for the estimation of the transient response induced by the interconnection
TLs particularly for the high-speed digital and/or mixed electronic systems.
For this reason, we suggest developing further modelling process allowing to
forecast simply the influences of RF/digital interconnection circuitries on the signal
quality via the analysis of the transient response behaviours. To make this chapter
more understandable, the theoretical analysis highlighting the determination of the
microstrip TL high-frequency parameters as the characteristic impedance and con-
stant propagation from the geometrical (width, length, substrate height) and physical
(dielectric permittivity and metal resistivity) characteristics is recalled in Sect. 2.2.
Then, the calculation method enabling the extraction of the RLCG model per-unit-
length parameters is equally presented. Hence, mathematical analyses explaining the
determination of the linear transfer function and S-parameters of the interconnec-
tion transient responses are developed in Sects. 2.2, 2.3 and 2.4. To illustrate the
feasibility of the modelling concept, discussions on validation results based on the
comparison with standard electronic simulation tool SPICE results are the object of
Sect. 2.5. Finally, the last section is the conclusion of the chapter.
2.2 Recall on Elementary Cell
2.2.1 Elementary L-Cell
For the beginning, let us consider the unit L-cell composed of Z-series impedance and
Y-parallel admittance depicted in Fig. 2.1. This fundamental circuit which behaves
as a passive four-terminal network is excited by the input voltage vin at the node N in
and generates an output voltage vout at the node N out .
According to the circuit and system theory, it is well known that the transfer matrix
of the L-cell shown in Fig. 2.1 is merely written as:
2 Basic Analysis of Single-Input Single-Output (SISO) PCB … 7
Fig. 2.1 Unit L-cell formed N in Z N out

by Z-series impedance and
Y-parallel admittance
vin Y v out

1+ Z ·Y Z
[T ] = . (2.1)
Y 1
The expressions of the transfer function H(s) and the input impedance Z in (s)
associated to this transfer matrix are written as:
Vout (s) 1 1
H (s) = = = , (2.2)
Vin (s) T11 1+ Z ·Y
T11 1
Z in (s) = =Z+ , (2.3)
T21 Y
where s is the Laplace variable. A mathematical analogy related to these elementary

relations will serve us for the proposed characterization of multi-level global T-tree
network formed by L-cell in the next subsections.
2.2.2 T-Matrix Modelling of Periodical Identical L-Cell

Cascaded [30]
For the sake of simplification, let us consider the generalized periodical network
comprised of n-element identical L-cells cascaded as illustrated in Fig. 2.2 [30] by
1 st-cell n th-cell
Z Z
o u tp u t
in p u t
Y Y
Fig. 2.2 Periodical n-element identical L-cells in cascade formed by Z-series impedance and Y-
parallel impedance [30]
supposing that each elementary cell is formed by Z-series impedance and Y-parallel
admittance.
According to the circuit and system theory, the transfer matrix of this circuit
consisted of n-cells cascaded can be written as the matrix product:
n

1+ Z ·Y Z
[Mn ] = . (2.4)
Y 1
k=1
So, one demonstrates that the recursive

expressions
connecting the four elements
of the consecutive matrices [Mn ] and Mn+1 are given by:
M(n+1)11 = (1 + Z · Y )Mn11 + Y · Mn12 , (2.5)
M(n+1)12 = Z · Mn11 + Mn12 , (2.6)
M(n+1)21 = (1 + Z · Y )Mn21 + Y · Mn22 , (2.7)
M(n+1)11 = Z · Mn21 + Mn22 , (2.8)
where the four elements of the initial matrix represent the transfer matrix of one
unique L-cell:

1+ Z ·Y Z
[M1 ] = , (2.9)
Y 1
According to the electronic circuit and system, the transfer function of this sys-
tem is the inverse of the first element M n11 . The recursive relationship between the
consecutive transfer function Tn and Tn+1 is expressed as:
Tn
Tn+1 = . (2.10)
1 + Y (Z + Tn · Mn,12 )
2.3 Analytical Investigation of Microstrip Transmission

Line-Based Tx-Rx Passive Chain
2.3.1 Microstrip Line Physical Parameters
Figure 2.3 represents the microstrip TL structure. It presents the physical parame-
ters: geometrical length d, width w and metallization thickness t. The constituting
Fig. 2.3 Microstrip TL

structure
y
z
x
dielectric substrate is characterized by its height h, relative permittivity εr and loss

constant tan(δ).
In electrical point of view, the microstrip line is essentially parametrized by its
frequency-dependent characteristic impedance Z c (f ) and its propagation constant
γ (f ) which can be expressed in function of the attenuation constant α(f ) and phase
constant β(f ) defined by:
γ ( f ) = α( f ) + j · β( f ). (2.11)
Knowing the physical properties of the microstrip structure, the characteristic

impedance can be deduced according to the formulations reported in [16, 17, 31]
expressed as:

η0 h · ψ(w/ h) 4h 2
Zc = √ ln + 1+ 2 , (2.12)
2π εeff w w
where

30.66 h 0.7528
ψ(w/ h) = 6 + (2π − 6) · exp − , (2.13)
w
with η0 is the air impedance and εeff is the effective permittivity of the medium. One
points out that as reported in [31], by denoting c is the speed of light in the vacuum,
the constant propagation:
2π f
γ ( f ) = αc ( f ) + αd ( f ) + j εeff ( f ), (2.14)
c
includes the metallic conductor and the dielectric losses, respectively, given by:

2
h 1 2h Rs ( f ) 32 − wh
αc ( f ) = 1.38 · 1 + · 1 + · ln · · , (2.15)
weff π t h · Z c ( f ) 32 + w 2
h
εr εeff − 1 c tan(δ)
αd ( f ) = 27.3 · √ · , (2.16)
εr − 1 εeff 2π f
with:

Rs ( f ) = π · μ0 · ρ · f , (2.17)

w + 1.25
π
1 + ln 2ht , if w
< 2π
1
weff = h (2.18)
w + 1.25
π
1 + ln 4πw
t
, if w
h
≥ 2π1
2.3.2 RLCG Parameter Extraction Method
For the calculations including the radiating loss, more explicit analytical expressions
of the propagation constant real part or the per-unit-length loss constant α(f ) are
presented in [31–34]. Knowing Z c and γ (f ), one can extract the equivalent TL RLCG
model with the per-unit-length parameters Ru , L u , C u and Gu as described in Fig. 2.4.
As established in [28], the TL global parameters:
R = Ru · d, (2.19)
L = L u·d , (2.20)
C = Cu · d, (2.21)
and
G = G u · d, (2.22)
can be calculated with the following expressions:

R = γ ( f ) · Zc , (2.23)
Ru x Lu x Ru x Lu x
Cu x Gu x Cu x Gu x
x x
Fig. 2.4 TL RLCG model


γ ( f ) · Zc
L= , (2.24)
ω

γ Z( cf )
C= , (2.25)
ω

γ( f )
G= , (2.26)
Zc
where [z] and [z] are, respectively, the real and imaginary parts of the complex
number z, and
ω = 2π f, (2.27)
is the operating angular frequency.

By denoting ρ the resistivity of the metallic conductor constituting the TL struc-
ture, it yields from the previous expressions that the global RLCG parameter can be
written as follows:
√
d π · μ0 · ρ · f
R= , (2.28)
w
d · Zc √
L= εeff , (2.29)
c
√
d εeff
C= , (2.30)
c · Zc
G = d · tan(δ) · ω · C, (2.31)
where μ0 is the vacuum permeability. By using these parameter definitions, one

proposes to establish the second-order transfer function of the microstrip line before
the determination of the TL transient responses.
2.3.3 T-Matrix Modelling
As example of numerical–digital interconnection circuitry [11, 25–27], let us con-

sider the microwave-digital system comprised of a TL driven and loaded by logic
gates represented in Fig. 2.5. As can be seen here, the TL is characterized by its
parameters (Z c , γ ) and its physical length d. One assumes that the driven gate output
behaviour is consisted of a voltage source V s with series impedance Z s and the load
gate as its input impedance denoted Z L . According to the microwave theory, the
d
Zs
vs (Zu, ) vL ZL
gate source interconnection line load gate
Fig. 2.5 Interconnection TL driven and loaded by logic gates
transfer matrix of the interconnection line characterized by (Z c , γ ) with geometrical

length d is expressed as:

cosh(γ · d) Z c sinh(γ · d)
[TT L ] = sinh(γ ·d) . (2.32)
Z cosh(γ · d)
c
The considered RLCG modelling behaviour is previously depicted in Fig. 2.4.

The overall interconnect system presented in Fig. 2.5 will be naturally transformed
as shown in Fig. 2.6.
According to the signal processing theory, the frequency band of any digital signals
is delimited by its theoretical bandwidth containing more than 85% of the baseband
harmonic components [32]. Thus, it was established that for the square wave digital
signal presenting rise-/fall-times t r , the frequency band is usually approximately
equal to:
0.35
f max ≈ . (2.33)
tr
It means that to study the analog–digital systems, one can consider its transfer
function behaviour from DC to f max . More generally, one can take into account the
Zs Ru x Lu x Ru x Lu x
vs Cu x Gu x Cu x Gu x vL ZL
gate source interconnection line load gate
Fig. 2.6 Interconnection RLCG model driven by a voltage source V s with inner impedance Z s and
loaded by Z L
transfer matrix of the TL as its baseband modelling behaviour by exploiting, for exam-
ple, the equivalent polynomial expression of the matrix [TT L ]. This approximation
can be realized, for example, by applying the second-order Maclaurin expanding of
each element of the transfer matrix. Therefore, one obtains the following expression:

1 + Z (s)·Y (s)
Z (s)
[TT L ] ≈ 2
(s) , (2.34)
Y (s) 1 + Z (s)·Y
2
with:
Z (s) = R + L · s, (2.35)
and
Y (s) = G + C · s. (2.36)
Therefore, according to the theory of electronic circuit and system, the overall
transfer matrix of the system schematized in Fig. 2.6 can be assimilated as:
⎡ ⎤
1 + 21 RG + s(LG + RC) + s 2 LC R + sL
[T ](s) = Tin · ⎣ ⎦ · [Tout ] (2.37)
G + sC 1 + 21 RG + s(LG + RC) + s 2 LC
where

1 Zs
[Tin ] = , (2.38)
0 1
and

1 0
[Tout ] = 1 , (2.39)
ZL
1
represents, respectively, the transfer matrices of the series impedance Z s and the
output shunt impedance Z L .
2.3.4 VTF Modelling
From the transfer matrix [T (s)] expressed in (2.37), one can demonstrate easily that
the overall VTF H (s) can be formulated as follows:
1 1
H (s) = = , (2.40)
[T11 (s)] a0 (s) + a1 (s) · s + a2 (s) · s 2
where
(2 + R · G + 2G · Z s ) (2 + R · G)
a0 (s) = ZL + Z s + R, (2.41)
2 2
(R · C + L · G + 2C · Z s )Z L (R · C + L · G)
a1 (s) = +L+ Zs , (2.42)
2 2
L ·C
a2 (s) = (Z L + Z s ). (2.43)
2
To confirm the efficiency of this transfer function model, time-domain responses
computed with MATLAB and then compared with the results from the SPICE ADS®
simulations are discussed in Sect. 2.5.1 and 2.5.2. Thus, we will evaluate the examples
of interconnection transient parameters as rise-/fall-times and the 50% propagation
delay.
2.4 S-Parameter and Time-Domain Convolution Applied

to Microstrip-Based Chain Structure
2.4.1 Topological Analysis
The basic configuration of the interconnect system will be examined. This latter is
composed of a source and load having impedances, respectively, denoted Z s and Z L .
Figure 2.7 depicts the schematic diagram of the system under consideration. It is
mainly comprised of an interconnect TL hypothetically having physical length d,
characteristic impedance Z c and propagation constant γ .
For the mathematical analysis of the system introduced in Fig. 2.7, the interconnect
line is assumed as its distributed RLCG model. So, the circuit under study will be
transformed as shown in Fig. 2.8.
Ru , L u , C u and Gu are, respectively, the per-unit-length resistance, inductance,
capacitance and conductance of the TL.
Source Interconnect line Load
vin Zs (d, Zc, ) ZL vout
Fig. 2.7 Illustration circuit diagram of the whole interconnect system under consideration, driven
by a voltage source with impedance Z s loaded by Z L
Interconnect line
Source Ru x Lu x Ru x Lu x Load
vin Zs Cu x Gu x Cu x Gu x ZL vout
Fig. 2.8 Distributed RLCG model of the interconnect system shown in Fig. 2.7
2.4.2 S-Parameter Modelling of PCB Microstrip

Interconnect [35]
According to microwave theory, the scattering- or S-matrix is a mathematical concept

that quantifies how RF or microwave energies propagate through a multi-port net-
work. The S-matrix is what allows us to describe the properties of electrical/electronic
networks as simple black boxes. For a typical microwave signal incident on one port,
some fraction of the signal bounces back out of that port, some of it scatters and
exits other ports (and is perhaps even amplified), and some of it disappears as heat
or even electromagnetic radiation. The S-matrix for an n-port contains a n2 coeffi-
cients (S-parameters), each one representing a possible input–output path. During
the calculation of the S-parameter matrix, the reference impedance is denoted Z 0 .
In this subsection, for the sake of analytical simplicity, we propose here the ana-
lytical study of S-parameters of the RLCG line without considering the source and
load impedances. Thanks to the ABCD- to S-matrix relationships and because of the
symmetry, the corresponding S-parameter elements are expressed as [35]:

Z c2 (s) − Z 02 · sinh γ (s) · d
S11 (s) = S22 (s) = ,
2Z c (s) · Z 0 cosh γ (s) · d + Z c2 (s) + Z 02 · sinh γ (s) · d
(2.44)
2Z c (s) · Z 0
S12 (s) = S21 (s) = .
2Z c (s) · Z 0 cosh γ (s) · d + Z c2 (s) + Z 02 · sinh γ (s) · d
(2.45)
So, according to the circuit and system theory [36], the voltage transfer function
associated with the ABCD-matrix can be written as:
Vout (s) 1
G(s) = = .
Vin (s) Z c (s)
+ Z s (s)
· sinh γ (s) · d + 1 + Z s (s)
· cosh γ (s) · d
Z L (s) Z c (s) Z L (s)
(2.46)
2.4.3 Time-Domain Convolution Methodology
To illustrate the functioning of the present modelling technique, let us consider a

classical microstrip PCB interconnection. As explained in the next section, the latter
is supposed to have geometrical length d, width w, metallization thickness t, dielectric
substrate with height h, relative permittivity εr and loss constant tan(δ). Knowing
these physical characteristics, the methodology enabling us to generate the transient
response of the interconnect circuit, depending on the excitation input voltage, can
be proposed via the flow work depicted in Fig. 2.9 [34].
The computation method suggested consists of three main steps. First, the calcu-
lation of the per-unit-length parameters Ru , L u , C u and Gu is performed according to
the physical characteristics of the interconnect line. Afterwards, the determination
of the ABCD-matrix and Z- or S-matrices is achieved. Then, one can easily compute
the output of the Interconnect Under Test (IUT) versus the given input excitation
signal vin via fast Fourier transform of the interaction between the ABCD-matrix
and the realistic or measured input signal under consideration. To do so, the exact
transfer function expression without polynomial approximation is considered. It is
important to note that compared to the method introduced in [37], a more general
concept taking into account the high-frequency responses is developed in the present
subsection.
W, h, t, r, tan , , d
Reflections, transmission and

transfer impedances
Per unit length parameter
calculation
Ru, Lu, Cu, Gu
Voltage transfer function ABCD Matrix Z and S Matrices
Input signal and

Zs,ZL
Impedances
Vin
FFT
SI Parameters (Delay,
Transient
over/under-shoot and
attenuation) Response Model
Output signal
Fig. 2.9 Flow diagram summarizing the methodology of the modelling method [34]
Fig. 2.10 3D design of the

simulated microstrip
interconnection line [37]
driver gate
TL
load gate
FR4-substrate
Table 2.1 Physical characteristics of the tested microstrip line

w h t εr tan(δ)
500 μm 625 μm 35 μm 4.4 0.012
2.5 Illustrative Applications
2.5.1 Application with R-Source and C-Loaded Microstrip

Single Line
2.5.1.1 POC Description
To give evidence to the relevance of the previous theoretical concepts, let us con-
sider the arbitrarily folded microstrip interconnection line pictured in Fig. 2.10 [37].
This microstrip device was simulated in SPICE schematic environment of standard
microwave electronic tool ADS® from AgilentTM . This structure was printed on
the FR4 substrate having physical characteristics and arbitrary chosen geometrical
parameters summarized in Table 2.1.
By applying the RLCG model extraction formulations introduced earlier in
Sect. 2.2, one obtains the following per-unit-length values: Ru = 16.6 /m, L u =
464.7 nH/m, C u = 74.7 pF/m and Gu = 5.6 mS/m.
2.5.1.2 Time-Domain Analysis
With this numerical value, we have implemented the above transfer function into
MATLAB program. Then, to generate the transient responses of the structure, a
periodical trapezoidal pulse presenting the temporal characteristics (t r : rise time, t f :
fall time, T p : period, t w : pulse time duration) with steady states V low = 0 V and V high
normalized at 1 V addressed in Table 2.2 was considered as the input.
Table 2.2 Parameters of the considered input excitation signal

tr tf Tp tw V low V high
100 ps 100 ps 1 ns 400 ps 0V 1V
Since the rise-/fall-time of the considered input signal is about 100 ps, according to
(2.33), the maximum frequency required for the proposed polynomial model response
has been estimated of about 3.5 GHz. We verify that it enables to generate transient
response taking into account the propagating TEM modes through the structure under
test which is compliant with the second-order transfer function expressed in (2.20). In
order to demonstrate the adaptability of the proposed modelling method for various
types of the load impedance, let us analyse the computed results first, for the resistive
load:
Z L = RL , (2.47)
and then, for the capacitive load:
Z L = 1/(C L · s), (2.48)
in the next paragraphs. As aforementioned, the comparative results are referred

to SPICE simulations run in ADS® transient simulations regarding the physical
parameters summed up in Table 2.1.
Transient Responses for Z L = RL [37]
It is interesting to note that the static gain of the overall understudy system is equal
to:
H (0) = R L /R S , (2.49)
when the source and load impedances are purely resistive. In the present case, we
have changed the value of the resistive load RL = {10, 500 } and the length of the
microstrip line d = {8.5, 13.5 mm}. So, one gets the comparative results plotted in
Figs. 2.11. The proposed model responses are plotted in full lines, and the ADS®
simulation results are in dashed lines.
One can see that the transient response generated from the proposed model agrees
very well with the SPICE simulations. One observes that through the microstrip inter-
connection, the pulse signal is significantly degraded. Here, with the two computation
processes, one evaluates rise-/fall-times of about t r ≈ 0.14 ns for RL = 500 and t r
≈ 0.43 ns for RL = 10 . Then, one evaluates rise-/fall-time relative errors of about
1%.
Fig. 2.11 Transient (a)

responses of the microstrip
structure shown in Fig. 2.10 2 Vs RL=10 RL=500
for different values of the 1.5
load gate resistance RL for
a d = 8.5 mm and b d = 1
voltage (V)
13.5 mm
0.5
-0.5
-1
0 0.5 1 1.5 2 2.5 3
time (ns)
(b)
2
Vs RL=10 RL=500
1.5
1
voltage (V)
0.5
-0.5
-1
0 0.5 1 1.5 2 2.5 3
time (ns)
Transient Responses for Z L = 1/(CL · P) [37]
In this case, Z L is assumed as a capacitive load C L . In order to show the interaction

between these load values and the interconnect line, we have changed the values of
the capacitive load C L = {1, 10, 30 pF} and the lengths of the microstrip line d =
{8.5, 13.5 mm} to demonstrate the flexibility of the proposed modelling process. As
consequence, one gets the comparative results displayed in Figs. 2.12. The proposed
model responses are plotted in full lines, and the ADS® simulation results are in
dashed lines.
One can see that the output is completely distorted for the capacitive load C L
higher than 1 pF. One evaluates here a 50% propagation delay of about T p50% = {80,
240, 440 ps}, respectively, for C L = {1, 10, 30 pF}.
For the both examples of the performed validation results, one points out that the
computation time with the proposed method is in order of tens microseconds. The
presented circuit-based modelling method is practically simpler than most of 3-D
EM full-wave solvers commercially available [38–42].
(a)
2 Vs CL=1pF CL=10pF CL=30pF
1.5
1
voltage (V)
0.5
-0.5
-1
0 0.5 1 1.5 2 2.5 3
time (ns)
(b)
2 Vs CL=1pF CL=10pF CL=30pF
1.5
1
voltage (V)
0.5
-0.5
-1
0 0.5 1 1.5 2 2.5 3
time (ns)
Fig. 2.12 Transient responses of the microstrip structure shown in Fig. 6 for different values of the
capacitive load C L : a d = 8.5 mm and b d = 13.5 mm [37]
2.5.2 Application with Microstrip Structure Based

on Capacitive Loaded Distributed RLC Line
Figure 2.13 represents the 3D design of the considered millimetre length structure
[43]. It is composed of microstrip interconnect line under test (LUT) having phys-
ical width w = 20 μm, variable length d driven by as voltage source with internal
resistance Rs = 10 and loaded by a capacitance C L = 1 pF.
This conductor formed by Cu metallization was printed on the alumina substrate
with relative permittivity εr = 9.6 and thickness h = 250 μm. By using the extraction
Fig. 2.13 Design of the line

under test (LUT) driven by a Source Interconnect line
source with internal impedance
resistance Rs and loaded by a
capacitance C L [43] Load
Alumina Via
Substrate ground
method developed in [16], one calculates the following per-unit-length parameters:

Ru = 1.02 /mm, L u = 86.5 nH/mm, C u = 71.6 fF/mm and Gu = 88 μS/mm.
2.5.2.2 Frequency-Domain Analysis [43]
By substituting these parameters into the reduced transfer function models expressed
in (2.5) and (2.7), one gets the results reported in the following subsections which are
performed with the electronic microwave circuit simulator ADS® from AgilentTM .
In this paragraph, frequency computation results of the circuitry shown in Fig. 2.13
are compared with those of the first- and second-order reduced model established in
previous section. For that EM and circuit SPICE co-simulations were carried out with
the LUT including the source and load parameters from DC to 40 GHz. Therefore,
one gets the magnitude and phase plotted in Fig. 2.14.
It can be seen that beyond 3 GHz base bandwidth the first-order model presents
magnitude relative errors of about 100% . However, very good agreement between the
SPICE simulations and the calculations made with the model established in previous
section is found for the second order. To get further insights about the accuracy of the
polynomial models in function of the LUT physical length, comparative computa-
tions between the frequency results from the models and the test circuit were made.
Therefore, one gets the maximum relative errors on the magnitude and the phase of
the transfer function up to 40 GHz displayed in Figs. 2.15. By varying the length of
the LUT from 1 to 10 mm, one finds that the magnitude relative errors change from
about 70% to above 200% for the first-order model, whereas the second-order model
permits to achieve relative error lower than 1%.
As shown in Fig. 2.15b, one remarks that the first-order model presents phase
relative errors going up to 80%. This latter is only lower than 4% for the second-order
model.
Fig. 2.14 Comparison (a)

between the frequency 10
Transfer function
simulation of the structure LUT
magnitude, dB
schematized in Fig. 2.13 and 1st order m odel
0 2nd order m odel
the proposed model:
a magnitude in dB and
-1 0
b phase in degree
-2 0
-3 0
0 10 20 30 40
(b) Frequency, GHz
0
Transfer function
phase, °
-1 0 0 LU T
st
1 order m odel
nd
2 order m odel
-2 0 0
0 10 20 30 40
Frequency, GHz
Fig. 2.15 Frequency (a)

maximum relative errors of
relative errors, %
the transfer function model 200 1st order

2nd order
Magnitude
proposed: a magnitude and

b phase
100
1 4 7 10
Length d, mm
(b)
100
relative errors, %
80
Phase
60 1st order
2nd order
40
20
0
1 4 7 10
Length d, mm
In order to evidence the accuracy of our models in function of the SI parameters (rise-
time, propagation delay, settling time, over-/under-shoot), one realizes time-domain
computations by injecting RF-/digital-or square wave pulse voltage with rise-/fall-
times equal to 5 ps. So, by using 10 Gbits/s rate analog–digital input signal, one gets
the results displayed in Fig. 2.16.
Once again, one can see that the second-order model presents relative errors lower
than 1% compared to the SPICE computation. However, the first-order one does not
enable to predict the interconnect line transient responses notably the overshoot. This
statement was also confirmed with lower rate test digital signal of 1 Gbit/s. Therefore,
one gets the transient responses displayed in Fig. 2.17.
These transient results confirm that with the reduced second-order model, one can
predict effectively the behaviour of the degradation of the digital/analog or mixed
signal for the high-speed data.
Fig. 2.16 Comparison of 2

time-domain computation input
responses from the LUT and LUT
st
the proposed models for the 1 order m odel
1
Voltage, V
nd
ultra-high-speed 2 order m odel
analog-digital input with
10 Gbits/s rate
0
-1
0 .0 0 .2 0 .4 0 .6
Time, ns
Fig. 2.17 Comparison of 2

time-domain computation input
responses from the LUT and LUT
the proposed models for the st
Voltage, V
1 1 order m odel
nd
ultra-high-speed 2 order m odel
analog-digital input with
1 Gbits/s rate
0
-1
0 1 2 3
Time, ns
2.5.2.4 Conclusion
Polynomial models of high-speed interconnect lines for the SI predictions are inves-
tigated theoretically and numerically. The model proposed is based on the exploita-
tion of the distributed RLCG line defined from the transmission line theory. By using
Maclaurin polynomial expanding, approximation of the transfer function was real-
ized. To verify the relevance of the models, microstrip interconnect line with 20 μm
width was considered and simulated in EM and circuit environments. Then, one
extracted the per-unit-length parameters of the equivalent RLCG line by using the
technique introduced in [16]. As results, it was shown that only with the first-order
model, relative errors higher that 100% were found via both frequency and time-
domain analyses. However, with the second-order model, relative errors lower than
1% were evidenced. This illustrates that this second-order model is useful for the
fast prediction of SI parameters.
2.5.3 S-Parameter and Time-Domain Convolution Analysis

[37]
To verify the relevance of the previous theoretical concepts, prototypes of microstrip

interconnects presented in Figs. 2.18 and 2.19 were modelled, simulated, imple-
mented and tested. Figures 2.18 depict the 3D design of the first IUT performed
in EMDS® environment of the standard ADS® microwave/electronic simulation
tool from AgilentTM and its photograph. Then, Figs. 2.19 represent the second IUT
composed of serpentine interconnect. We emphasize that these microstrip devices
were first designed and simulated in frequency domain. Then, with the equivalent
black box of the S-parameters, time-domain computations were carried out in SPICE
schematic environment of ADS®.
These prototypes, IUT1 and IUT2 , correspond to the field of applications of sim-
ple PCB traces as the case of PLL feedback of the DDR2 clock generation and a
delay compensation line for the data distribution of DDR2 [44]. These IUTs were
printed on a lossy FR4 substrate having physical characteristics and arbitrary chosen
geometrical parameters w = 500 μm, h = 1.6 mm, t = 35 μm, εr = 4.3, tan(δ) =
0.012, and lengths d 1 = 45 mm for IUT1 and d 2 = 92.5 mm for IUT2 . To validate the
methodology under consideration that was introduced in the previous section, these
IUTs are tested both in frequency and in time domains.
(a)
w
d h
(b)
Fig. 2.18 a 3D design of the IUT1 and b its photograph [37]
Fig. 2.19 a 3D design of the tested serpentine interconnect line (IUT2 ) and b its photograph [37]
Fig. 2.20 Per-unit-length
Gu (mS.m-1) Cu (pF.m-1) Lu (nH.m-1) Ru ( .m-1)

400
parameters extracted from
the model investigated 200
versus frequency 0
0 1 2 3 4 5 6
650
600
0 1 2 3 4 5 6
56
54
52
0 1 2 3 4 5 6
40
20
0
0 1 2 3 4 5 6
Frequency (GHz)
2.5.3.2 S-Parameter Analyses
Frequency-Dependent RLCG Parameters
By applying the RLCG model extraction formulations described earlier in Sect. 2.2,
the following per-unit-length parameters are obtained at 1 GHz: Ru = 32.22 /m,
L u = 621.26 nH/m, C u = 53.69 pF/m and Gu = 2.8 mS/m.
The variation of per-unit-length parameters versus frequency is sketched in
Fig. 2.20. As expected, mainly due to the skin effect, we find that the resistance
and conductance parameters are relatively sensitive to the frequency change.
Experimental Set-up Description
With these parameters, we have applied the technique indicated by the flow work
shown in Fig. 2.15 into MATLAB program to determine the ABCD-, S- and Z-
matrices of the IUTs by considering the source and load with impedances as Z 0 =
50 . Then, in order to demonstrate the accuracy of the model, comparisons with
EM ADS-Momentum ® simulations and measurements with the fixture shown in
Fig. 2.21 were performed [37]. It is worth noting that the S-parameter measure-
ment was realized with the Agilent network analyser ENA E5071C through SOLT
calibration.
Fig. 2.21 Photograph of the

employed universal substrate
fixture [37]
Fig. 2.22 Comparison M od e l

between the S-parameters S21 ADS
from the model proposed M e a s u re m e nt
S-param eters (dB)
(grey full line), ADS 0

simulation (dashed line) and -8
measurement (black full S11
line) [37] -1 6
-2 4
-3 2
-4 0
0 1 2 3 4 5 6
F re q u e n c y (G H z )
Frequency-Domain Analyses
As a result, the S-parameters plotted in Fig. 2.22 were obtained with the IUT1 . It
turns out that the model developed is in excellent agreement with the simulations
and measurements here in UWB (from DC to 6 GHz). It is important to note that
the models permit to predict the periodical aspects specific to broadband responses
of the S-parameters which cannot be done with the classical polynomial model. By
referring to the measurement results, a maximal absolute error of insertion loss S 21
of about 0.4 dB can be estimated here. Thus, compared to the simulations, due to
the numerical inaccuracy of S-parameters notably at the high frequencies, it is about
1 dB with ADS® simulation results.
By using the S-to-Z transform, the access and transfer impedances of the intercon-
nect lines including the source and load impedances are plotted. Then, comparisons
with ADS simulations and measurements were made. Once again, as illustrated in
Figs. 2.23, IUT impedance frequency responses in very good correlations were found
with the possibility of ripple effect predictions. Due to the numerical errors related
Fig. 2.23 Input/output M odel

(a) and transfer ADS
(b) impedances of the whole (a) M e a su re m e n t
im pedances (k )
system computed from the 0 .3
model proposed (grey full
Access
line), ADS simulation 0 .2 Z11
(dashed line) and
measurement (black full 0 .1 Z22
line) [37]
0 .0
0 1 2 3 4 5 6
F r e q u e n c y (G H z )
M odel
ADS
(b) M e a su re m e n t
150
im pedances ( )
Transfer
100
50
0
0 1 2 3 4 5 6
F re q u e n c y (G H z )
to the parameter S 11 , the input impedance Z 11 presents a maximal relative error of

about 7% that is noticeably close to the relative error of ADS® simulation results.
In order to prove the functionality of the model for the prediction of the high-speed
SI, time-domain analyses were performed.
2.5.3.3 Time-Domain Analyses
This subsection is dealing with the time-domain validations for the high-speed appli-
cations by considering the measured and modelled S-parameters. Then, transient
computations were conducted for the input square wave pulse with 0.5 Gbits/s rate
having 50 ps rise- and fall-times including the noise effects. It is worthy of note that
the source is represented by impedance Z s = 50 and the load is a parallel RC
network composed of a 500- resistor and a 4-pF capacitor. Therefore, one realizes
the transient responses of IUT1 and IUT2 plotted in Fig. 2.24 have been obtained.
As expected, the model allows an achievement of a good prediction of the transient
responses from the measured S-parameters.
In addition to this time-domain verification, more realistic computations were
made by injecting an arbitrary binary sequence of 8-bit data “10100100”. This test
signal corresponds to mixed square wave signal with 1-Gigasymbol/s rate. So, the
time-domain results displayed in Fig. 2.25 are recorded for the IUT1 and in Fig. 2.26
for the IUT2 .
Fig. 2.24 Time-domain

Vin
results of the IUT1 and the
IUT2 for 0.5 Gbits/s input Model
square wave signal [37] SPICE
IUT2
Voltage (V)
V0
V 0 /2 IUT1
0 2 4 6 8
Time (ns)
Fig. 2.25 Time-domain V in

results of the IUT1 for M odel
1-Gigasymbol/s binary S P IC E
sequence input [37]
V0
Voltage (V)
V0 /2
0 5 10
Time (ns)
Fig. 2.26 Time-domain V in

results of the IUT2 for M odel
1-Gigasymbol/s binary S P IC E
sequence input [37]
V0
Voltage (V)
V0 /2
0 5 10
Time (ns)
It must be pointed out that here a relative accuracy lower than 1% between
the models proposed and SPICE computations from the measured S-parameters is
assessed.
2.5.3.4 Conclusion
A simple, fast and accurate technique of PCB interconnect modelling is developed.

The model established can be used during the design process of high-speed cir-
cuit, notably for the prediction of SI and EMC degradations. A theoretical approach
enabling us to determine the reduced ABCD-, Z- and S-matrix models was proposed.
The algorithm enabling to compute the frequency- and time-domain responses of the
interconnect lines was established.
To validate the concept suggested, UWB comparisons of S-parameters and input
and transfer impedances (Z-matrices) with EM ADS® simulations and measurements
were realized in frequency domain. As a result, an excellent agreement between the
frequency-characteristics of the PCB microstrip interconnect with tenth millimetre
lengths was proved. Compared to the existing methods proposed in [6–9], the reduced
model introduced in this chapter does not depend on polynomial approximations. So,
the prediction from DC to 6 GHz was made with a computation time of only some
milliseconds. To gain more insight about the feasibility of the method investigated,
advanced transient analysis based on the 1-Gigasymbol/s mixed data was also real-
ized. So, once again, excellent correlations of the IUT transient responses were found
through the prediction of mixed signal distortions. It is noteworthy that the method
proposed is not able to straightforwardly perform an accurate transient simulation
with nonlinear loads because of the aliasing effect [45]. However, suitable methods
to cope with this issue which meet the usual requirements of the SI in high-speed
digital systems have been recently introduced [46, 47].
2.6 Conclusion of this Chapter
A transfer function modelling method of the millimetre interconnection for the high-
speed integrity analysis in the RF-/digital PCB is investigated. The established model
is based on the exploitation of the electrical RLCG model transfer matrix which was
assumed as its second-order polynomial linear model.
To evidence the functionality of the introduced method, a microstrip intercon-
nection TL driven and loaded by the logic gates was considered and analysed. It
was described that the per-unit-length equivalent model parameters were determined
from the TL physical and the geometrical parameters as the substrate permittivity
and height, and the line width and length. Then, the equivalent transfer function lin-
ear model of the overall system composed of a TL combined with the logic gates is
mathematically established. Thus, for the testing process, it was excited with a peri-
odical trapezoidal pulse voltage with 2 Gbits/s rate. So, good agreement between the
transient responses from the established transfer function calculated with MATLAB
and those from SPICE simulations of the overall structure was found. It was shown
that the microstrip interconnection responses are completely degraded. Then, after
the sweep of the load impedance values assigned as resistance and capacitance loads,
one observes also that the calculated transient results remain well correlated to the
simulations.
One emphasizes that the design and the simulation of this type of microwave-
digital interconnections become very difficult to carry out when the circuit is com-
posed of thousands of logic gates. For this reason, it seems important to exploit the
proposed modelling method for the prediction the analog–digital signal behaviours
along the interconnections. Thanks to the accuracy and the computation time gain,
we think that the proposed method can be a good candidate for the modelling of
the complex structure of the interconnection circuitry in the high-density integrated
circuit as the clock distribution networks.
In the continuation of this work, one plans to improve this method for the esti-
mation of the RF microwave and digital electronic device interconnection effects
by taking into account the non-uniformity of the TL and the eventual crosstalk with
the neighbourhood TLs. Then, we would employ the proposed method to the devel-
opment of the equalization technique with the NGD circuit for the reduction of
the correction of the digital signal degradation with MMIC and digital integrated
systems.
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Chapter 3
Discrete Periodical Model of Microstrip
Line with Cascaded Elementary L-Cells
Blaise Ravelo and Lala Rajaoarisoa
3.1 Introduction
The mankind society and way of life become more and more dependent on electronic
equipments. This technological dependence manifests, in particular, with the strong
needs of personal computers at work, mobile phones (2.5G, 3G and 4G) of population
anytime and anywhere around the world and boom of video games [1, 2]. This
modern daily habit change creates a motivation source of microelectronic industries
to improve with no limit the technical performances of their products. According
to the ITRS road map reports [3, 4], this development can be evaluated mainly by
decrease of device feature sizes and the increase of the operating data speed. This
renders the microelectronic system interconnections more and more complex.
With several Gigasymbols/s rates of operating data in the modern microelectronic
systems [5–9], the interconnection influences can create a severe malfunctioning of
electronic systems. In fact, interconnection lines are susceptible to generate signifi-
cant delays and losses which can be a source of signal desynchronization at different
stages of the microelectronic systems as the clock tree networks [10–12]. To over-
come this problem, deep investigations on the SI propagating in the interconnection
networks have been conducted [13–18]. Moreover, methods enabling improving the
performance optimization were also proposed [19, 20]. Till now, most of the exist-
ing methods are based on first- [10, 21, 22] or second-order [23–27] polynomial
approximations of interconnection transfer functions. In order to enhance the signal
quality, an equalization method based on the use of negative group delay circuits was
also introduced [28–30]. The interconnect models [31–34] are generally considered
and implemented for the approximation of the SI parameters such as signal delays,
rise time, overshoot/undershoot and also the attenuation. But in certain use cases,
B. Ravelo · L. Rajaoarisoa (B)

Centre de Recherche, IMT Lille-Douai, 764 Boulevard Lahure, 59500 Douai, France
e-mail: lala.rajaoarisoa@imt-lille-douai.fr

36 B. Ravelo and L. Rajaoarisoa
because of the increase of the operating signal bandwidth, the second-order models
of interconnection networks are not sufficient.
3.2 Modeling of Periodical Lumped RC-Network

Microstrip Line Structure
3.2.1 Topological Analysis
For starting, let us consider the periodical discrete model of TL based on the RC-
network presented in Fig. 3.1. It is formed by n-elements or segments cascaded which
are constituted by lumped circuits with total resistance:
R = Ru x, (3.1)
and capacitance:
C = Cu x, (3.2)
where the length:
x = d/n. (3.3)
Logically, if the integer number of cells n is higher, the discrete model is more
accurate.
As aforementioned, one assumes that the RC-cells constituting the discrete
network schematized in Fig. 3.1 consist of lumped resistance and capacitance,
respectively, defined as R and C.
1 st-cell n th -cell
Ru Δ x Ru Δ x
vi(t) Cu Δx Cu Δ x RL
vo (t)
Fig. 3.1 Discrete RC-line formed by n lumped elements with resistance R = Ru · Δx and capacitance
C = C u · Δx [33]
3 Discrete Periodical Model of Microstrip Line with Cascaded … 37
3.2.2 T-matrix Modeling
It means that the transfer matrix governing a unique cell is given by:

1+ R·C ·s R 1 + Ru · Cu · (Δx)2 · s Ru · Δx
[M RC ] = = . (3.4)
C ·s 1 Cu · Δx · s 1
In this case, the total transfer matrix of the interconnect network shown in Fig. 3.1
should be calculated analytically from the matrix product representing the RC-cell
transfer matrices and the load resistance RL :

n 1 0
[Mn ] = [MRC ] × 1 . (3.5)
k=1
RL
1
Let us denote this matrix as:

Mn11 Mn12
[Mn ] = . (3.6)
Mn21 Mn22
For the sake of simplification, one assumes the following assignment:

n
M RC11 (n) M RC12 (n)
[MRC ] = . (3.7)
M RC21 (n) M RC22 (n)
k=1
After substitution of the RC-cell matrix into Eq. (3.37), we obtain the relations
between the elements of the whole matrix [Mn ] and those of the transfer matrix:

n
[Mx ] = [M RC ], (3.8)
k=1
of cascaded periodical RC-network:

M RC12 (n)
M RC11 (n) + M RC12 (n)
[Mn11 ] = RL
M RC22 (n) . (3.9)
M RC21 (n) + RL
M RC22 (n)
3.2.3 Input Impedance and VTF Modeling
The input impedance of the RC-network in Fig. 3.1 is written as follows:

Mn11 (s) R L · M RC11 (n) + M RC12 (n)

Z n (s) = = . (3.10)
Mn21 (s) M RC12 (n) · M RC21 (n) + M RC22 (n)
As the circuit network under study is constituted only by RC linear passive elec-
trical components, the global transfer function must behave as a linear polynomial
expression defined as follows:
1 1
Tn (s) = = n , (3.11)
Mn11 (s) k=0 ck (n)s
k
where ck (n) (k = {1…n}) are real coefficients corresponding to the circuit network.
By delimiting to the second-order approximation, one establishes the following recur-
sive relations between the three first coefficients, c0 , c1 and c2 which are defined
as:
c12,0 (n)
c0 (n) = c11,0 (n) + , (3.12)
RL
c12,1 (n)
c1 (n) = c11,1 (n) + , (3.13)
RL
c12,2 (n)
c2 (n) = c11,2 (n) + , (3.14)
RL
where cpq,k (n) with (pq) = {(11), (12), (21), (22)} are the element coefficients of the
transfer matrix [Mx ] defined as:

n
M RC( pq) (n) = c pq,k (n)s k . (3.15)
k=0
Thanks to the linear algebraic property, one can write:

n+1
n
[M RC ] = [M RC ] × [M RC ]. (3.16)
k=1 k=1
The identification of matrix elements M RC11 (n + 1), M RC12 (n + 1), M RC21 (n + 1)

and M RC22 (n + 1) applied to each side of this matrix equality implies below iterative
equations:
⎧
⎨ c11,0 (n + 1) = c11,0 (n) = · · · = c11,0 (1) = 1
c11,1 (n + 1) = R · Cc11,0 (n) + c11,1 (n) + C · c12,0 (n) , (3.17)
⎩
c11,2 (n + 1) = c11,2 (n) + R · C · c11,1 (n) + C · c12,1 (n)
⎧
⎨ c12,0 (n + 1) = R · c11,0 (n) + c12,0 (n) = (n + 1)R
c12,1 (n + 1) = R · c11,1 (n) + c12,1 (n) , (3.18)
⎩
c12,2 (n + 1) = R · c11,2 (n) + c12,2 (n)
⎧
⎨ c21,0 (n + 1) = c21,0 (n)
c (n + 1) = R · C · c21,0 (n) + c21,1 (n) + C · c22,0 (n) , (3.19)
⎩ 21,1
c21,2 (n + 1) = R · C · c21,1 (n) + c21,2 (n) + C · c22,1 (n)
⎧
⎨ c22,0 (n + 1) = R · c21,0 (n) + c22,0 (n)
c (n + 1) = R · c21,1 (n) + c22,1 (n) , (3.20)
⎩ 22,1
c22,2 (n + 1) = R · c21,2 (n) + c22,2 (n)
where n is an integer higher than 1. The initial parameters of the iterative operation
can be determined toward the identification of [M RC (1)] with the matrix expression
shown in equation:
⎧
⎪
⎪ c11,0 (1) = 1, c11,1 (1) = R · C, c11,2 (1) = 0
⎨
c12,0 (1) = R, c12,1 (1) = 0, c12,2 (1) = 0
. (3.21)
⎪
⎪ c (1) = 0, c21,1 (1) = C, c21,2 (1) = 0
⎩ 21,0
c22,0 (1) = 1, c22,1 (1) = 0, c22,2 (1) = 0
By considering the polynomial transfer function T n (s) expressed in (3.15), the

static gain or the final value corresponding to the time domain unit step response is
equal to:
1
Tn (0) = . (3.22)
c0 (n)
This VTF can be rewritten as:

1 1
Tn (0) = c12,0 (n)
= Ru ·d
. (3.23)
c11,0 (n) + RL
1+ RL
One points out that at any given time t 0 higher than the system settling time t s , this
static gain can be approximated as the output voltage attenuation corresponding to
the unit step response. Toward the previous iterative operations expressed in (3.18)–
(3.21) combined with the three expressions of c0 (n), c1 (n) and c2 (n) introduced,
respectively, in (3.14), (3.15) and (3.16), one dresses the transfer function expressions
summarized in Table 3.1. It represents the simplified model of the discrete lumped
RC-network consisted of n-cells in cascade with the arbitrarily chosen values of n =
{3, 7, 10, 15, 20}.
Table 3.1 Expressions of the

n T n (s)
second-order approximation
of loaded discrete RC-model 3 Tn=3 (s) = 1
transfer function 1+3 RR +2RC 3+2 RR s+ 5+ RR (RCs)2 +O(s 3 )
L L L
7 Tn=7 (s) =
1
1+7 RR +28RC 1+2 RR s+126 1+ RR (RCs)2 +O(s 3 )
L L L
10 Tn=10 (s) =
1
1+10 RR +55RC 1+3 RR s+99 5+8 RR (RCs)2 +O(s 3 )
L L L
15 Tn=15 (s) =
1
1+15 RR +40RC 3+14 RR s+476 5+13 RR (RCs)2 +O(s 3 )
L L L
20 Tn=20 (s) =
1
1+20 RR +70RC 3+19 RR s+1463 5+18 RR (RCs)2 +O(s 3 )
L L L
3.3 Discrete Modeling with Cascaded Periodical RLC-Cells
To develop the model, let us consider the interconnect system comprised of TL with
characteristic impedance Z c , propagation constant γ and physical length d driven
by a voltage source vi and loaded by an impedance Z L represented in Fig. 3.2. The
voltage across the output load of this circuit is denoted vo .
In order to investigate the integrity of mixed or analog–digital signals propagating
through the interconnection system, authentic and confident knowledge about the
analytical behavior of the equivalent transfer function is indispensable. This allows
(Zc,d )
(a)
Ii(t)
vi(t) interconnect line ZL vo(t)
(b)
1 st-cell k th-cell n th-cell
Ruδ x Luδ x Ruδ x Luδ x Ruδ x Luδ x
vi(t) Cuδ x Cuδ x Cuδ x ZL vo(t)
Interconnect line
Fig. 3.2 Interconnect line with characteristic impedance, Z c , and physical length, d, driven by a
voltage source, vi , loaded by Z L [33]
the extraction of different time domain parameters, in particular the mathematical

expression appropriated to the interconnection system unit step response. For that,
in this chapter, one proposes to proceed with the theoretical analysis based on the
exploitation of the equivalent ABCD matrix of each elementary block (TL in cascade
with a shunt impedance Z L ) constituting the overall system shown in Fig. 3.2a. The
equivalent model of the TL including the distributed infinite cells in cascade with
infinitesimal small length δx is depicted in Fig. 3.2b (here the integer k < n).
In fact, the elaboration of the SI parameters of the distributed interconnect system
under study from its own transfer function [31] is mathematically very complicated:
Vo (s) ZL
T (s) = = , (3.24)
Vi (s) Z L cosh(γ · d) + Z c sinh(γ · d)
where γ represents the propagation constant of the TL. For this reason, a charac-
terization method based on the discrete model of interconnection line constituted
by periodical lumped RLC-cells is introduced in this subsection. For the clarity, it
is organized in three different paragraphs. Paragraph 3.3.1 develops the theoretical
analysis of the periodical structure composed of lumped RLC-network. In this case,
the formulations enabling to extract the parameters R, L and C of the interconnection
lines which can be assumed as a microstrip interconnection are used. To verify the
effectiveness of the proposed theoretic concepts, validation results are presented in
Paragraph 3.3.2. Then, the last section is the conclusion of the chapter.
3.3.1 Modeling Methodology
According to the current microelectronic applications with the operating data of

about some Gigasymbols/s rate [3, 4, 6, 27, 31, 32], the per-unit length conductance
parameter Gu of the interconnect TL is usually negligible. For this reason, in this
chapter, we propose to exploit the discrete modeling method limited to the periodical
RLC-network shown in Fig. 3.2.
3.3.2 RLC-Cell-Based Microstrip Line Structure

Discretization
This circuit is formed by n-elements of identical discrete RLC-cells in cascade which

are constituted by lumped circuits with total resistance R and capacitance C defined,
respectively, in (3.1) and (3.2) and inductance:
L = L u x, (3.25)
for the piece physical length Δx defined in (3.3). Ru , L u and C u are the per-unit length
parameters of the interconnect TL. Logically, higher is the integer number of cells
n, more accurate is the discrete model.
3.3.2.1 T-Matrix Model
To analyze strategically the network introduced in Fig. 3.3, let us consider the period-
ical network comprised of n identical L-cells cascaded having ABCD matrix written
as:

1 + (R + L · s) · C · s R + L · s
[M R LC ] = , (3.26)
C ·s 1
where s is the Laplace variable. With the per-unit length parameters, this transfer
matrix is written as:

1 + (Ru + L u · s) · Cu · (x)2 · s (Ru + L u · s) · x
[M R LC ] = . (3.27)
Cu · x · s 1
According to the circuit and system theory, the ABCD matrix of the circuit
consisted of n-RLC-cells cascaded can be written as the matrix product:

n n

1 + (R + L · s) · C · s R + L · s
[M(n)] = [M R LC ] = . (3.28)
C ·s 1
k=1 k=1
It is important to note that the expression of [M RLC ] does not depend on the
parameter k because the elementary RLC-cells constituting the TL are identical. For
the simplification, we denote:

M11 (n) M12 (n)
[M(n)] = . (3.29)
M21 (n) M22 (n)
1 st-cell k th-cell n th-cell

RuΔ x LuΔ x RuΔx LuΔx RuΔx LuΔx
vi(t) CuΔ x CuΔx CuΔx ZL vo(t)
Interconnect line
Fig. 3.3 Proposed discrete model formed by n segments of periodical lumped RLC-cells [33]
So, it can be demonstrated that the recursive expressions connecting the four
elements comprising the consecutive matrices [M(n)] and [M(n + 1)] are expressed
by:
M11 (n + 1) = [1 + (R + L · s) · C · s]M11 (n) + C · s · M12 (n), (3.30)
M12 (n + 1) = (R + L · s) · M11 (n) + M12 (n), (3.31)
M21 (n + 1) = [1 + (R + L · s) · C · s]M21 (n) + C · s · M22 (n), (3.32)
M22 (n + 1) = (R + L · s) · M21 (n) + M22 (n), (3.33)
where the four elements constituting the initial matrix [M1 ] are also the ABCD matrix
of the elementary RLC-cell:

1 + (R + L · s) · C · s R + L · s
[M(1)] = . (3.34)
C ·s 1
In this case, the total ABCD matrix of the whole RLC-network shown in Fig. 3.3
should be calculated analytically from the following matrix product:

n
1 0 MT 11 (n) MT 12 (n)
[MT (n)] = [M R LC ] × = . (3.35)
1
ZL
1 MT 21 (n) MT 22 (n)
k=1
Substituting expression (3.29) into the latter matrix relation, one gets the relations
between the elements of the whole matrix [MT (n)] and those of ABCD matrix:

n
[M(n)] = [M R LC ], (3.36)
k=1
defined as:

M12 (n)
M11 (n) + M12 (n)
[MT (n)] = ZL
M22 (n) . (3.37)
M21 (n) + ZL
M12 (n)
3.3.2.2 VTF Model
According to the circuit and system theory, the transfer function is the inverse of the
first element of the ABCD matrix. It means that the transfer function of the system
under study can be written as:
1
Tn (s) = M12 (n)
, (3.38)
1
T0n (s)
+ ZL
where T0n (n) is the transfer function of the open-ended periodical RLC-network
comprised of n-elements in cascade. The recursive relation of the transfer function
of the open-ended discrete RLC-line is given by:
1
T0(n+1) (s) = . (3.39)
1+(R+L·s)·C·s
T0n (s)
+ C · s · M12 (n)
For example, by assuming the load as a resistance RL in parallel with a capacitance

C L , analytically expressed as:
RL
Z L (s) = , (3.40)
1 + RL · C L · s
the global transfer function of the circuit introduced in Fig. 1 will become:
1
Tn+1 (s) = 1+(R+L·s)[C·s+(1+R L ·C L ·s)/R L ]
, (3.41)
Tn (s)
− (R+L·s)(1+R L ·C LR·s)[1+R
2
L ·(C+C L )·s]
M12 (n)
L
with the initial value:

1
T1 (s) = . (3.42)
1+ R
RL
+ (C + C L ) · R · s + (C + C L ) · L · s 2
As the interconnect circuit under study is constituted by elementary R-, L- and

C-linear passive networks, the global transfer function must behave as a linear
polynomial function written as:
1
Tn0 (s) = n , (3.43)
k=0 ck (n)s
k
where ck (n) (k = {1…n}) are real coefficients depending on the periodical RLC-
network parameters. We can remark that this interconnect system transfer function
can be considered for determining the frequency and time domain responses of the
system in simple way compared to the relation introduced in (3.43). One can establish
the recursive relations between the element coefficients of ABCD matrix [M(n)] by
using this polynomial relation:

n
M pq (n) = c pq,k (n) · s k , (3.44)
k=0
where cpq,k (n) with (p, q) = {(1, 1), (1, 2), (2, 1), (2, 2)} and k = {1…n}. For example,
the two first coefficients are given by the recursive formulae:
c11,2 (n) = c11,2 (n − 1) + R · C · c11,1 (n − 1) + L · C · c11,0 (n − 1)

+ C · c12,1 (n − 1), (3.45)
c12,1 (n) = R · c11,1 (n − 1) + L · c11,0 (n − 1) + c12,1 (n − 1), (3.46)
c12,2 (n) = R · c11,2 (n − 1) + L · c11,1 (n − 1) + c12,2 (n − 1), (3.47)
c21,2 (n) = c21,2 (n − 1) + R · C · c21,1 (n − 1) + L · C · c21,0 (n − 1)

+ C · c22,1 (n − 1), (3.48)
c22,1 (n) = R · c21,1 (n − 1) + L · c21,0 (n − 1) + c22,1 (n − 1), (3.49)
c22,2 (n) = R · c21,2 (n − 1) + L · c21,1 (n − 1) + c22,2 (n − 1). (3.50)
By identification with the matrix expression shown in (3.34), we obtain the

following definition of initial parameters:
⎧
⎪
⎪ c11,0 (1) = 1, c11,1 (1) = R · C, c11,2 (1) = L · C
⎨
c12,0 (1) = R, c12,1 (1) = L , c12,2 (1) = 0
. (3.51)
⎪
⎪ c (1) = 0, c (1) = C, c21,2 (1) = 0
⎩ 21,0 21,1
c22,0 (1) = 1, c22,1 (1) = 0, c22,2 (1) = 0
In order to confirm the relevance of this theoretic concept, in the next section, one
proposes to analyze an example of application based on the numerical experiment
of microstrip interconnection line.
3.4.1 Application of Periodical Lumped RC-Network

Microstrip Single Line
To demonstrate the relevance of the established numerical modeling method, let us

see validation results run in SPICE schematic environment of the ADS® simulation
software from AgilentTM . For that, one proposes to estimate transient parameters for
the SI prediction such as propagation delay, settling time and the voltage attenuation
prior to the second-order polynomial approximations in Table 3.1.
RC-line
TRANSIENT
vi(t) (Ru ,Cu,d) vo(t) RL
Fig. 3.4 ADS schematic of the interconnection network under investigation comprised of RC-line
driven by square-wave voltage source and loaded by RL -resistance [33]
Figure 3.4 represents the schematic of the numerical test interconnection network
under investigation in this section. One can see that it consists of distributed RC-
network model (available in ADS library) with the per-unit length resistance Ru =
5 /mm, capacitance C u = 1 pF/mm, physical length d = 5 mm and loaded by a
resistance RL = 100 . The whole circuit is excited by a square-wave pulse voltage
source (with normalized amplitude V M = 1 V) and time duration t 0 = 100 ps or
10-Gbits/s rate. In order to take into account the realistic effects, this source was
assumed as a trapezoidal signal with rise/fall times equal to 10 ps.
Then, analyses of the interconnection parameter influencing the proposed numer-
ical modeling method are made in the next paragraphs and compared with SPICE
results.
3.4.1.2 Analysis of High-Speed Square-Wave Transient Responses
In this subsection, the transient voltage responses of the circuit depicted in Fig. 3.5
are compared with the responses of the polynomial VTF models summarized in
Table 3.1 (by taking n = 20). Through time domain simulations run from t min = 0
to t max = 500 ps and step Δt = 0.2 ps, one gets the comparison results of the output
voltages displayed in Fig. 3.5 for different values of the load resistance RL = {20,
60, 100 }.
Fig. 3.5 Comparison of

square-wave transient RL=20Ω
1 .0
voltage responses from RL=60Ω
RL=100Ω
voltage,V
SPICE computations and the

proposed discrete model for
0 .5
Ru = 5 /mm, C u =
1 pF/mm, d = 5 mm and RL SPICE
dsc model
= {20, 60, 100 } [33]
0 .0
0.0 0.1 0.2 0.3 0.4 0.5

time, ns
As displayed in Fig. 3.5, the transient responses from the reference SPICE compu-
tation are plotted in gray full line and those ones computed from the proposed discrete
RC-model are plotted in black dashed line. So, very good agreement between the
transient responses was observed. One evaluates here relative errors which are mainly
due to the numerical inaccuracy of about 2%.
3.4.1.3 Analysis of the Proposed Model Accuracy in Function

of the Employed Segment Number N
To highlight the accuracy of the proposed numerical model in function of n, we rely

on the SI parameters, propagation delay T p and signal attenuation α(t 0 ). As evidenced
in Figs. 3.6 and 3.7, one finds that the propagation delays T p and the transient voltage
attenuation α(t 0 ) at the instant time t 0 = 100 ps obtained from the proposed model
are more and more close to the reference SPICE model when n is higher.
These results highlight the effectiveness of the discrete modeling method, notably
for the assessment of the different SI parameters in time domain for the high-speed
data rate applications.
As shown in Fig. 3.8, the relative errors from T p calculated from the proposed
model vary, respectively, from 80 to 5%. Moreover, it decreases from 30 to 1% for
the voltage attenuation α(t 0 ) when n is swept between 1 and 20.
Fig. 3.6 Propagation delays 100

T p versus number of discrete
cells n for Ru = 5 /mm, C u 80
= 1 pF/mm, d = 5 mm and
60
Tp, ns
RL = 100 [33]
40
20 SPICE
dsc model
0
0 5 10 15 20
Number of cells n
Fig. 3.7 Output attenuation 1

α(t 0 ) at t 0 = 100 ps versus
number of discrete cells n for 0.8
Ru = 5 /mm, C u =
0.6
1 pF/mm, d = 5 mm and RL
α (t0)
= 100 [33] 0.4 SPICE

dsc model
0.2
0
0 5 10 15 20
Number of cells n
Fig. 3.8 Relative errors of (a) 1

the calculated propagation
p pSPICE pSPICE
delays a and attenuations 0.8
b versus number of cells
n [33]
|/T
0.6
0.4
|T -T
0.2
0
0 5 10 15 20
(b) Number of cells n
0.5
(t )
SPICE 0
0.4
(t )|/α
0.3
SPICE 0
0.2
|α (t )-α
0.1
0
0
0 5 10 15 20
Number of cells n
These numerical experiment results confirm that the established VTF expressions
of the interconnection discrete model converge to the ideal case of the distributed
circuit when n goes to infinity.
3.4.1.4 Influences of the Interconnection Per-Unit Length Parameters

on the Proposed Model
To complete the above study, in this subsection, one proposes to analyze the influences
of the tested interconnect per-unit length parameters Ru and C u to the model under
investigation.
3.4.1.4.1 Analysis of the Per-Unit Length Resistance Influence
By varying the per-unit length resistance Ru = {5, 10, 15, 20 /mm} of the inter-
connection circuit shown in Fig. 3.4 via sweep/transient co-simulations, one gets the
time domain results displayed in Fig. 3.9.
Fig. 3.9 Unit step transient

results for the sweep values Ru=5Ω/mm
1.0
of Ru = {5, 10, 15, Ru=10Ω/mm
20 /mm}, C u = 1 pF/mm, Ru=15Ω/mm
voltage,V
d = 5 mm and RL = 300 Ru=20Ω/mm
0.5
[33] SPICE
dsc model
0.0
0.0 0.1 0.2 0.3 0.4 0.5

time, ns
Fig. 3.10 Unit step transient

Cu=1 pF/mm
results for the sweep values 1.0 Cu=4 pF/mm
of Ru = 5 /mm, C u = {1,
Cu=7 pF/mm
voltage, V
4, 7, 10 pF/mm}, d = 5 mm Cu=10 pF/mm

and RL = 300 [33]
0.5 SPICE
dsc model
0.0
0.0 0.1 0.2 0.3 0.4 0.5

time, ns
Once again, a very good correlation between the SPICE computations and the
proposed numerical modeling method is evidenced. One underlines that when the
pulse time duration t 0 is higher than the settling time, one can estimate in more easy
way the attenuation as the system final value. Although, this latter can be deduced
in function of the parameters Ru , d and RL directly via formula (3.23).
3.4.1.4.2 Analysis of the Per-Unit Length Capacitance Influence
The same transient simulations as in previous paragraph were made by increasing

the capacitance per-unit length parameter C u = {1 pF/mm, 4 pF/mm, 7 pF/mm, 10
pF/mm}. So, one gets the results depicted in Fig. 3.10. Once again, one finds that
the calculated voltage responses are much close to the SPICE computations.
Figure 3.10 shows that the attenuation is stronger when C u is higher. Meanwhile,
these interconnection lines cannot be useful for the operating data with rate higher
than 10 Gbits/s for C u > 3 pF/mm because the voltage cannot attain the threshold
voltage if it is set at V max /2. Therefore, to preserve the output voltage amplitude
as higher as possible, one should operate with signals having pulse time duration
absolutely higher than the settling time of the interconnect network system.
Finally, it is noteworthy that the presented computation results were executed with
the scientist standard tool MATLAB. So, one finds that the elapsed computation times
during the calculation process were only of some tens of microseconds.
3.4.1.4.3 Conclusion
A numerical modeling method of the microelectronic interconnection network for

the SI analysis was successfully investigated. The developed model is based on the
exploitation of the high-speed TL network consisted of segments of identical lumped
L-cells in cascade. To concretize the feasibility of the method, the study was focused
on the interconnect TL comprised of RC-networks essentially characterized by its
per-unit electrical parameters and its physical length. Thanks to the manipulation of
the elementary system transfer matrices, the analytical approximation of the global
transfer function of the overall interconnect network was established. Then, this
developed model was used to evaluate in fast and easy way the SI parameters. In
order to highlight the relevance of the introduced concept, simulations of circuitry
comprised of RC-line with millimeter length loaded by a shunt resistance were carried
out. Then, comparisons of SPICE computations were also performed by considering
an input square-wave pulse voltage having 10-Gbits/s rate versus the per-unit length
TL parameters. The accuracy of the proposed modeling method in function of the
discrete cell number n constituting the interconnection line was demonstrated. It was
shown that this allows to state that the propagation delay from the proposed model
is less than 5% for n higher than twenty cells. So, it was shown that the proposed
modeling method permits to characterize efficiently the SI parameters. Furthermore,
it was found that the investigated method algorithm consumes very less computation
times and generates with confident accurate results.
It is interesting to note that the main benefits of the presented modeling method lie
on its simplicity and its flexibility to integrate into any simulation computation tools.
Meanwhile, it can be adapted to computer-aided designs for mixed or analog–digital
electronic systems. In addition, it enables the prediction of the layout trace signal
fidelity for the PCB or the chip-to-chip interconnect networks in particular for the
high-speed application. In the next step of this work, the application of the introduced
modeling method for the SI prediction especially for the complex analog–digital
module interconnections as the distributed clock tree networks is outlined.
3.4.2 Application with Cascaded RLC Periodical Cells
Figures 3.11a, b represents the circuit diagram of the interconnection system under
study. It is essentially composed of a microstrip line printed on the FR4 epoxy
substrate characterized by a relative permittivity εr = 4.4 and thickness 0.8 mm. The
(a)
Data source Interconnection line Load
w
vi (t) RL CL
d
(b)
1 st -cell k th-cell n th -cell
Ru Δ xLu Δ x RuΔ xLuΔ x RuΔ xLuΔ x
vi(t) Cu Δ x Cu Δ x Cu Δ x RL CL
Inter connect line
Fig. 3.11 a Diagram of the interconnection circuit under study comprised of a microstrip line driven
by square-wave source and loaded by RC parallel impedance and b the considered equivalent circuit
[33]
metallization consists of a copper conductor with thickness 35 µm with geometrical

width defined in the next part denoted w and physical length equal to d = 3 mm. This
interconnection line is driven by a high-rate voltage source representing the mixed
data and loaded with an impedance formed by a resistance RL and capacitance C L
connected in parallel.
By applying the calculation method reported in [31, 32], with various values of
width w = {50, 100, 150, 200 µm}, we determined the per-unit length parameters
Ru , L u and C u . Therefore, one gets the results summarized in Table 3.2 [31, 32]. One
remarks that the resistance and inductance TL per-unit length parameters increase
with the interconnect metallization width and inversely for the capacitance.
By employing these extracted parameters, comparisons were made between the
frequency and time domain computations with the SPICE and Momentum environ-
ments of ADS® simulator from AgilentTM . So, the interesting results exposed in the
next paragraphs are obtained.
Table 3.2 Per-unit length

w (µm) Ru (/m) L u (µH/m) C u (pF/m)
parameters extracted from the
tested microstrip line for 50 111.8 1.00 30.7
various values of the width w 100 74.6 0.90 34.6
150 57.6 0.83 37.7
200 47.4 0.79 40.3
3.4.2.2 Frequency Domain Analysis
It is worth noting that the microstrip line under study is supposed used in the context of
the high-speed mixed or digital–analog data. In this case, the digital data exciting the
interconnect line under study can be assumed as analog baseband signal delimited by
the frequency f lim inversely proportional to its rise/fall times t r defined in Eq. (2.33)
of Chap. 2.
Analytically, it means that for the microelectronic applications operating around
some Gigasymbols/s, the considerable analog bandwidth of input signals is limited
to about 6 GHz. In other words, the effectiveness of the model proposed can be
validated up to the frequency given by f lim .
So, the relevance of the proposed discrete model can be evaluated via S-parameter
simulations in baseband frequency up to 6 GHz for different values of the metalliza-
tion width w. The TL was tested with EM and circuit co-simulations. These simu-
lations consist of the global simulation of the structure shown in Fig. 3.11 by using
the full-wave EM S-parameter model of the microstrip line computed in Momentum
environment of ADS®. As consequence, by considering a discrete model comprised
of n = 10 RLC-cells in cascade, a very good agreement between the return loss S 11
and the transmission loss S 21 of the TL tested displayed in Fig. 3.12 is realized. One
can see that the TL loss is inversely proportional to the interconnect width w.
3.4.2.3 Time Domain Analysis
To carry out this transient analysis, the interconnection network depicted in Fig. 3.11
was excited by a square-wave pulse voltage having normalized amplitude and time
symbol duration T = 200 ps which corresponds to 5 Gigasymbols/s rate. To take into
account the practical imperfections of this high-speed signal generation, the rise/fall
time of this data source was set at 20 ps. Then, comparisons were made between the
transient responses from the EM and circuit co-simulation of the TL for w = 100 µm
presented in Fig. 3.11 and the lumped RLC-networks comprised of n = 10 RLC
segments in cascade. After transient simulations run from t min = 0 to t max = 1 ns, by
varying the load resistance RL = {100, 200, 300 } via sweep co-simulations, the
results are displayed in Fig. 3.13.
The responses from the reference SPICE computation are plotted in black dashed
line and those computed from the proposed discrete RLC-model are plotted in gray
full line. So, once again, the transient responses from the transfer function model
introduced in Sect. 3.3.4.1 are very well correlated with the EM and circuit co-
simulations of the piece of microstrip interconnect TL.
One can remark that as predicted in theory, due to the interconnection effects, the
operating signal is completely degraded. One evaluates here relative errors of about
1%, which are in fact mainly due to the numerical inaccuracy. The same numerical
investigations performed with various load capacitance values C L = {0.5, 2.5, 4.5 pF}
generate the transient results displayed in Fig. 3.14. One can see that the obtained
computation results are in very good agreement between the model proposed and
0 0
|S 2 1 m o d e l |, d B
|S 2 1 T L |, d B -1 -1
w=50µ m w=50µ m
-2 w=100µm -2 w=100µm
w=150µm w=150µm
w=200µm w=200µm
-3 -3
0 2 4 6 0 2 4 6
Freque ncy, G H z Freque ncy, G H z
p h a s e (S 2 1 m o d e l ), °
P h a s e (S 2 1 T L ), °
0 w=50µ m 0 w=50µ m
w=100µm w=100µm
w=150µm w=150µm
w=200µm w=200µm
-30 -30
-60 -60
0 2 4 6 0 2 4 6
0 0
|S 1 1 m o d e l |, d B
|S 1 1 T L |, d B
-10 -10
w=50µ m w=50µ m
-20 w=100µm -20 w=100µm
w=150µm w=150µm
w=200µm w=200µm
-30 -30
0 2 4 6 0 2 4 6
Fig. 3.12 Comparison of the proposed model S-parameters and those of the TL depicted in Fig. 3.11
for w = {50, 100, 150, 200 µm} [33]
Fig. 3.13 Transient 3 R L= 1 0 0 Ω

responses for input data: RL
= {100, 200, 300 }, C L = 2 R L= 2 0 0 Ω
2 pF and w = 100 µm [33] R L= 3 0 0 Ω
Voltage, V
-1 model
TL
-2
0.0 0.2 0.4 0.6 0.8 1.0
Time, ns
the EM and circuit SPICE simulations. It is noteworthy that with the circuit under
study, the quality of the analog–digital signal propagating through the interconnect
line is more and more degraded when C L increases.
Fig. 3.14 Transient 2

responses for T = 0.2 ns, RL CL=0.5pF
= 100 , C L = {0.5, 2.5, CL=2.5pF
4.5 pF} and w = 100 µm
Voltage, V
1 CL=4.5pF
[33]
0
model
TL
-1
0.0 0.2 0.4 0.6 0.8 1.0
Time, ns
According to this numerical test, we point out that the main novelty of the modeling
method presented in this chapter is based on its flexibility to operate in frequency and
time domains. It is shown with this realistic structure composed of 3D interconnect
that compared to the full-wave simulators as Momentum-ADS [34–37], the model
developed is simpler and can be executed with ten times less computation time.
3.4.2.4 Sensitivity of the Proposed Model in Function of the Model

Segment Number and the Tested Interconnect Length
To achieve more concluding numerical experiments about the accuracy of the pro-
posed model, relative error analysis about the transient voltage responses in function
of the proposed model segment number for the various values of w is proposed in this
paragraph. For that, unit step source data with rise time of about 10 ps was injected in
the circuit under test. By taking arbitrary values of the load impedance (RL = 100
and C L = 1 pF), and for the physical length d = 5 mm, the results plotted in Fig. 3.15
are obtained. It is worth noting that the transient responses from the proposed model
Fig. 3.15 Relative errors of 60

the unit step transient
w=50µm
relative error, %
responses for n varied from 1

to 10 [34] w=100µm
40
Voltage
w=150µm
w=200µm
20
1 2 3 4 5 6 7 8 9 10
Number of cells, n
Fig. 3.16 Relative errors of 40

unit step transient responses
Relative errors, %
w = 50µm
for d varied from 0.5 mm to w = 100µm
30
20 mm [34] w = 150µm
w = 200µm
20
10
0
0 5 10 15 20
Length d, mm
converge rapidly to the reference results which is considered absolutely achieved for
infinity of cells cascaded when n = 15.
For different values of the metallization width w, the transient results present
relative errors lower than 1% when n is higher than 10. As illustrated in Fig. 3.16,
it can be underlined that the proposed model presents relative errors lower than 4%
when the TL length d is varied between 1.5 mm and 17 mm.
Moreover, one can see that the sensitivity is higher when the width w is lower. It
is interesting to note that the accuracy of the model versus d depends also on the rise
time of the operated signal data.
3.4.2.5 Conclusion
An efficient modeling technique of the microelectronic interconnection lines ded-

icated to high-speed operating data processing up to the microwave frequencies is
presented. Due to the complexity growth of the TL transfer function expressions,
it becomes very difficult to determine the exact formulation of transient responses
of interconnection networks in the integrated microelectronic systems. To pass this
technical limitation, a discrete model comprised of periodical lumped RLC-cells
in cascade is introduced, investigated analytically and validated numerically in this
chapter. Theoretic analysis enabling to establish the equivalent polynomial formula of
the transfer function in function of the considered RLC-cell number connected in cas-
cade is developed. To verify the relevance of the theory, validations with EM/circuit
co-simulations regarding millimeter microstrip line were performed. As a result, a
very good agreement between the S-parameters of the proposed model and the tested
millimeter microstrip line was found in baseband frequency up to 6 GHz. In addi-
tion, transient analyses with various parameters of the considered interconnection
load were realized. Therefore, results presenting relative errors almost negligible
were obtained when the number of cells is very high. It was evidenced also that the
presented numerical analysis shows that the precision of the method in function of
the cell numbers in cascade is better than 1% when the number of discrete RLC-cells
is higher than 10. These numerical results confirm the method usefulness notable for
the SI prediction.
A discrete lumped circuit modeling of microstrip interconnect line is developed in

this chapter. The modeling concept is elaborated with consideration of identical L-
shape topology elementary cells. As fundamental network constituting the model,
RC and RLC elementary cells defined from the microstrip line physical parameters
are used. The recursive analytical expressions of the microstrip line in function of
the number of cells are established. The present model can be used to analyze the
behavior of the microstrip line in the frequency domain and also in the time domain
by using high-speed input signal.
The relevance of this periodical cell-based model is verified with SPICE simu-
lations. Frequency and time domain computations are performed. As expected, the
VTF and the transient responses computed with the periodical cell-based model and
SPICE simulations are in good agreement.
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negative group delay active circuits, in Proceedings of 11th IEEE Workshop on SPI, Genova,
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Chapter 4
Modelling of the Signal Delay Induced
by PCB Interconnect SISO Structure
Blaise Ravelo and Thomas Eudes
4.1 Introduction
In the late 1950s, thanks to the deep scientific and physical analyses on the semicon-
ductor materials, the mankind discovers the era of microelectronics. This industrial
period was born with the invention of the integrated circuits (ICs) by Jack S. Kilby
from Texas Instruments [1]. The impact of this invention was awarded with the
Nobel Prize in physical discipline in 2000. In the middle of the 1960s, the Intel
Co-founder Gordon Moore who is one of the pioneers in Silicon Valley [2, 3] formu-
lated an empirical law stating that the performance of ICs, including the number of
components on it, doubles every 18–24 months with the same chip price. With this
spectacular progress, the understanding of the physical effect in the components is
fundamental. Then, one of the most developed mathematical predictions enabling to
foresee the progress of the microelectronic circuits’ performance known as Moore’s
law was proposed [4].
Till now, the electronic technology develops with higher integration scale accord-
ing to this analytical prediction which manifests with the increase of the operating
frequency and the integration density [5–7]. For the better understanding in the mat-
ter of the basic functioning of this technology, a large scientific background on the
physical approach permitting an accurate analysis of the circuit and system equiva-
lent behaviours or electrical modelling, EM effects on the wave propagation, and also
the mathematical approach for the signal theory are necessary [8–13]. The synergy
of all these multiphysics fields constitutes the particularity of the SI discipline which
is one of the major steps for investigating the analog and digital high-speed systems.
Despite the spectacular technological progress of microelectronic systems, the
complexity of the IC structures including the increase of their interconnect density,
which link several million of logic gates, becomes more and more sophisticated.
B. Ravelo (B) · T. Eudes

Graduate Engineering School, Rouen, France

60 B. Ravelo and T. Eudes
Beyond the unintentional perturbation phenomena as the electromagnetic interfer-

ence (EMI) and electromagnetic compatibility (EMC) emissions [8, 9], this elec-
tronic PCB and IC design complexity can generate systematically a serious problem
in terms of SI and power integrity (PI) of the interconnection networks [10–13].
To cope with this issue, the design research engineers must innovate their tech-
niques by taking into account the electrical interconnection influences. Usually, the
mathematical predictions enabling to model the undesired physical aspects (loss,
distortion, delay, overshoot, etc.) induced by the interconnect structures are based on
the electrical model defined by the per-unit-length parameters RLCG [14–16]. Till
now, the most popular theory used for the analytical investigations of the intercon-
nect structure is based on the Elmore [17] and Wyatt [18–20] models named also
as lumped RC model is used by most industrial semiconductor designers for esti-
mating the typical linear system transient responses. In fact, the models introduced
and used in [17–20] are fundamentally developed with the first-order approximation
of the interconnect system operating voltage transfer function. Despite this simplic-
ity, since the late 1990 s, it has been underlined that with such an approximation,
compared to second-order lumped models [21–28], the transient response parame-
ters as the rise/fall times and the propagation delay can present relative errors more
than 30-%. Furthermore, the first-order model is not sufficient for analysing certain
phenomena as the current or voltage under-and overshoots. For this reason, with
the current electronic systems operating frequency, which achieves some GHz, the
second-order parameters as the inductance effect becomes more and more significant
in the high-speed interconnect networks as PCBs, ICs packages, and even connec-
tors. One of the simplest existing delay models recently proposed [23, 25, 28–30] is
based on the linear systems with canonical transfer function written as:
T0
T (s) = , (4.1)
s2 + 2ζ · ωa · s + ωa2
with T 0 is a real constant, and ωa and ζ are, respectively, the undamped natural
angular frequency and damping ratio. But this model is valid only for the transfer
function with linear polynomial forms. So, further and deeper analysis is necessary
for the complex systems governed by typically nonlinear transfer functions as the
distributed TL. To do this, an example of technique for compensating the degradation
induced by interconnect lines is introduced in [24, 25, 28, 31]. More recently, inter-
connect effects’ equalization technique, particularly, for reducing the signal delays
[32, 33] based on the use of the negative group delay circuit whose the principle
is developed in [34, 35] has been introduced. Moreover, accurate, optimized, and
also easy to implement models enabling the prediction of these unwanted effects are
indispensable [36–39]. In this scope, new generations of design strategies and com-
mercial numerical tools for simulation and characterization of various 3D structure
geometries permitting to ensure the signal fidelity at Gbits/s speeds were recently
reported [40–44]. But, the computed results with these tools remain critical when the
designed structure like entire systems (SiP, SoC, PoP, BGA packages, etc.) presents
4 Modelling of the Signal Delay Induced by PCB Interconnect SISO … 61
many levels of integration. Nowadays, easier and more relevant modelling method
of electronic circuit interconnect network is still needed.
For this reason, a modelling method based on the distributed interconnection
network is developed in this chapter. For the clearance of readability, this chapter is
structured in three sections. Section 4.2 describes the fundamental approach enabling
to determine the transfer function of the distributed electronic network interconnec-
tion system. Then, basic matrix theory applied to the generalized periodical lumped
circuit constituting the assumed interconnect system will be proposed. In addition,
a mathematical analysis of the established model unit-step response enabling to the
calculation of the SI parameters as the propagation delay, rise/fall times, settling
time, and even the attenuation will be carried out. Hence, validations through com-
putations with the reference tool SPICE environment will be offered in Sect. 4.3.
Lastly, Sect. 4.4 is the conclusion.
4.2 Modelling Methodology
4.2.1 Description of the Tx-Rx Chain Microstrip

Interconnect-Based Structure
Figure 4.1 depicts the considered interconnect system comprised of a TL having

characteristic impedance Z c and physical length d driven by a voltage source vi (t)
having internal impedance Rs and loaded by an impedance RL C L parallel. The voltage
across the output load of this circuit is denoted vo (t).
In order to investigate the integrity of the mixed or analog–digital signals propagat-
ing through the whole interconnection system shown in Fig. 4.1, a relevant knowledge
about the analytical behaviour of equivalent transfer function is essentially indispens-
able. In fact, this allows the extraction of different transient or time-domain parame-
ters. For that, one can proceed with a theoretical approach based on the exploitation
of the equivalent transfer matrix of each circuit block constituting the whole system.
(Zc,d)
Ii(t)
Rs
vi(t) interconnect line vo(t) RL CL
Fig. 4.1 Interconnect line with characteristic impedance, Z c , and physical length, d, driven by a
voltage source, vi (t), with internal impedance, Rs , loaded by RL C L parallel network
4.2.2 VTF Model
By using the interconnect input impedance according to Ohm’s law, the input current
I i (s) injected in the circuit shown in Fig. 4.1 should be written as:
Vi (s) Vi (s)
Ii (s) = = ZL cosh(γ ·d )+Zc sinh(γ ·d )
. (4.2)
Rs + Zin (s) Rs + Zc ZL sinh(γ ·d )+Zc cosh(γ ·d )
In order to achieve more explicit analytical development, the VTF T (s) must be
expressed in function of the basic Laplace variable s. This leads us naturally to the
examination of the transfer function regarding the distributed TL model with the
per-unit-length parameters R, L, and C.
According to the microwave and TL theories, by taking into account the implicit
resistive metallic loss, and the inductive and capacitive effects of the interconnect
line, the lossy line introduced in Fig. 4.1 can be assumed as a distributed RLC network
model schematized in Fig. 4.2. The parameters Ru , L u , and C u represent, respectively,
the per-unit-length resistance, inductance, and capacitance of the interconnect line,
and δx is an infinitesimal small physical length.
In this case, the transfer function expressed is transformed as follows:
√
d (Ru + Lu · s) · Cu · s · RL
T (s) = . (4.3)
d (Ru + Lu · s) · Cu · s RL + Rs (1 + RL · C · s) cosh(d (Ru + Lu · s) · Cu · s)

+ d 2 (Ru + Lu · s) · Cu · s(1 + RL · C · s) + Rs RL sinh(d (Ru + Lu · s) · Cu · s)
By replacing s by jω, due to the presence of the terms cosh(.) and sinh(.), the
transmittance of the structure under study can be determined. From there, we can
deduce the time-domain response through FFT. But the accuracy of the FFT and
IFFT remains critical when the bandwidth of the input signal is larger than 10 GHz.
In addition, the exploitation of the frequency response to deduce the transient charac-
teristics of the transfer system (as overshoot, rise time, time response) is impossible.
For this reason, a polynomial approach permitting the extractions of these transient
parameters is developed in the next section.
d
Rs Ruδx Luδx Ruδx Luδx
vi(t) Cuδx Cuδx RL CL vo(t)
Fig. 4.2 Distributed circuit equivalent of the RLC model of the system shown in Fig. 4.1
4.2.3 Transient Response Modelling
In fact, the assessment of the SI parameters suited to the distributed TL under-

study from this non-polynomial transfer function is mathematically very compli-
cated because the transient response is relatively complicated to express analytically.
For this reason, one proposes to exploit the distributed RLC network described in
Fig. 4.2. Thanks to the Maclaurin polynomial expanding of the denominator, the
transfer function can be approximated as:
1
T (s) = , (4.4)
c0 + c1 · s + c2 · s2 + O(s3 )
with:
Rs + Ru · d
c0 = 1 + , (4.5)

RL
Ru · Cu 6Lu + 3Rs · Cu · Ru + R2u · Cu · d
c1 = + d 2 + (Rs · Cu + Ru · CL )d , (4.6)
2 6RL

R2u · Cu · d 2 Lu Ru · L u · d R3 · Cu · d 3
c2 = + + + u · Cu · d 2
24 2 3RL 120RL

Ru · Cu2 · d Ru · Cu · CL Lu · Cu R2 · C 2 · d 2
+ Lu · CL + Rs · d + + + u u d. (4.7)
6 2 2RL 24RL
By identification between the second-order approximation of transfer function

expressed in (4.4) and the canonical form introduced earlier in (4.1), one can write
the following parameters:
1
T0 = , (4.8)
c2

c0
ωa = , (4.9)
c2
c1
ζ = √ . (4.10)
2 c0 · c2
According to the damping ratio value ζ , one distinguishes three different cases
of unit-step responses which enable to determine the transient response parameters
prior to the evaluation of the output SI parameters.
It is interesting to note that the limit of the model presented here depends on
two parameters. First, by denoting f max , the maximal operating frequency, and v, the
speed of the signal propagating along the interconnect line, the rise time of the input
signal which must be higher than [15] is given as follows:
0.35 2.8d
tr ≥ = . (4.11)
fmax v
Then, according to the limited polynomial expansion, the inaccuracies of the

model can be evaluated with the high-order terms of the transfer function expressed
in (4.3). For example, the influence of the dominant third term can be considered with
the series Maclaurin expansion by the third-order coefficient expressed as follows
for the RLC interconnect model:
⎡ ⎤
Rs CL R2u Cu d 2 +
Cu d 2 ⎢
⎢ ⎥
⎥.
c3 = 2
24 ⎣ 2Lu 2Rs Cu d + 6Rs CL + 4Ru CL d + Ru Cu d 2 + Rs Ru Cu d + 2Lu d ⎦
(4.12)
RL
In difference with the model established in [45], here, the root of the equation
vo (t) = 0 with the direct calculation enabling achieving more accurate and precise
mathematical expressions is considered. So, in the remainder of this section, the
detailed formulae on the different SI parameters are offered.
4.2.3.1 Case 1: ζ < 1
It is well known that in this case, the under-consideration system behaves as a classical
overdamped system. Clearly, it should present an overshoot here denoted by ξ at the
time, Tξ which are, respectively, expressed as:
√−πζ
ξ =e 1−ζ 2 if ζ < 1, (4.13)
π
Tξ = . (4.14)
ωa 1 − ζ 2
Hence, the ±5-% settling time is defined as:
3
ts±5% ≈ . (4.15)
ζ · ωa
More importantly, the 50% propagation delay is estimated as:
0.5Tξ
Tp ≈ √−πζ
. (4.16)
1+e 1−ζ 2
In the present case, by approximating the output voltage vo (t) as its tangential
line passing through its unique inflection point, one demonstrates the here below
rise-time formulation:
√
ωa √ ζ arctan ζ −2 −1
tr ≈ 0.8 e 1−ζ 2 . (4.17)
T0
4.2.3.2 Case 2: ζ = 1
In this case, the normalized output unit-step response is literally written as:
vo (t) = 1 − (1 + ωa · t)e−ωa ·t . (4.18)
For the better understanding, one denotes t = T λ the root of the equation vo (t) = λ
(λ is real constant positive lower than 1). With this expression, this parameter can be
extracted easily by considering a singular mathematical function. The corresponding
solution can be expressed as:
2
λ·ω
LW e−1 T0 a − 1 + 1
Tλ = , (4.19)
ωa
where L W (x) expresses the mathematical Lambert function of x, which is defined as

a mathematical function satisfying the following equation [46, 47]:
LW (x) · eLW (x) = x. (4.20)
Nevertheless, simpler formulations of the 50-% propagation delay and the rise
time are estimated as:
1
Tp ≈ , (4.21)
ωa
√
ln(9) 2
tr ≈ . (4.22)
ωa
4.2.3.3 Case 3: ζ > 1
In this case, it is obvious that T (s) behaves as an underdamped system with two real
poles:
1
ω1 = = ωa ζ + ζ 2 − 1 , (4.23)
τ1
1
ω2 = = ωa ζ − ζ 2 − 1 . (4.24)
τ2
Moreover, by exploiting the dominant term (here based on the contribution of

the pole ω2 ) of the normalized unit-step response for high value of the temporal
parameter t, the ±5-% settling time is established as:
ts±5% ≈ τ2 [3 + ln(τ2 ) − ln(τ2 − τ1 )]. (4.25)
Similar to case 1, by approximating the output vo (t) as its tangential line passing
through its unique inflection point, the propagation delay demonstrated is written as
follows:

ω2
[λ2 + 1]τ2 − [λ1 + 1]τ1 0.5(ω1 − ω2 ) ln ω1
Tp ≈ + + , (4.26)
λ2 − λ1 T0 (λ2 − λ1 ) ω2 − ω1
with
ω ω−ω
1
ω2 1 2
λ1 = , (4.27)
ω1
ω ω−ω
2
ω2 1 2
λ2 = . (4.28)
ω1
Finally, knowing that in this case of underdamped system, the whole transfer
function is formed by the product of transfer function having rise times:
τa = ln(9) · τ1 , (4.29)
and:
τb = ln(9)τ2 , (4.30)
the overall rise time can be estimated as:

tr ≈ ln(9) τ12 + τ22 . (4.31)
In general way, regarding the three cases cited previously, it is clear that the
normalized unit-step response voltage attenuation α(t0 ) at the given instant time t =
t 0 is explicitly defined as:
⎧ T0
⎪
⎪ 1 − (1 + ωa t0 )e−ωa t0 if ζ = 1
⎪
⎪ ⎧ ωa2
⎪
⎪ ⎡ ⎤⎫
⎪
⎪ ⎨ ⎬
⎪
⎨ T0 1 − e−ωa t0 ⎣cosh ω t ζ 2 − 1 + ζ sinh ω t ζ 2 − 1 ⎦ if ζ > 1
a 0 a 0
α(t0 ) = ωa2 ⎩ ζ 2 −1 ⎭ . (4.32)
⎪
⎪ ⎧ ⎡ ⎛ ⎞⎤⎫
⎪
⎪ ⎨ ⎬
⎪
⎪ −ζ ωa t0 2
⎪
⎪ T0
1 − e
1−ζ
sin⎣ωa t0 1 − ζ 2 + arctan⎝ ζ ⎠⎦ if ζ < 1
⎪
⎩ ωa2 ⎩ 1−ζ 2 ⎭
4.3.1 Application with Ω-Line Structure
To validate the concept of the modelling method presented, realistic prototypes of

microstrip interconnects are analysed and compared with ADS simulations and vali-
dated with measurements. In that case, the metallic conductor of Fig. 4.2 was assigned
as a copper.
The verification results presented in this subsection are obtained from a microstrip
line with width w = 0.3 mm and various lengths d = 17 mm printed on the FR4 epoxy
substrate having relative permittivity εr = 4.4. Figure 4.3a represents the schematic
diagram of the circuit tested by considering an interconnection with complex form.
Fig. 4.3 a Schematic (a)

diagram (Rs = 10 , RL = Rs
150 and L L = 1 nH), b 3D
design of the structure, and RL
c photograph of the vi(t) vo(t)
prototype tested [48] LL
EM-model of the
interconnect line
(b)
mm 16
11 mm
(c)
At noted that this interconnect corresponds to the type of PCB interconnections for
mixed-circuit as PLL or command boards using microcontrollers [19]. Figure 4.3b,
c are respectively the 3D design of the line and the photograph of the fabricated
prototype. Then, EM full-wave simulations of the 3D structure represented by the
black box of Fig. 4.3a were performed with the ADS® simulation in the EDMS®
environment.
4.3.1.2 Comparative Results
By applying synthesis relations (4.6)–(4.8), we evaluate the per-unit-length param-

eters: R = 15.7 /m, L = 712 nH/m, and C = 44.6 pF/m. Then, comparisons of the
frequency- and time-domain responses from the EM and circuit co-simulations with
the ADS® SPICE tool and the EDMS® simulations, measured prototype, and the
model established are realized. Therefore, results from the model, in excellent agree-
ment with measurements, are confirmed both in frequency and in time domains as
confirmed by Figs. 4.4a, b. From DC to 1.4 GHz, an absolute difference, lower than
0.7 dB, is performed between the model and the measured transfer function mag-
nitudes for various values of Rs . For the time-domain analysis, a trapezoidal input
signal with 1-Gbit/s rate and rise time of about 0.33 ns was injected into the circuit
(a)
10
Vo/Vi magnitude (dB)
R s =10 Ω Simulation
R s =30 Ω Meaurement
R s =50 Ω Model
0
-10
0.0 0.7 1.4
Frequency (GHz)
(b)
Vi
1.0 V omeasurement
Voltage (V)
V omodel
0.5
0.0
0 2 4 6
Time (ns)
Fig. 4.4 Magnitude responses of the structure tested (a) and time-domain responses (b) [48]
shown in Fig. 4.3a. Therefore, T pmeasured ≈ 166 ps and T pmodel ≈ 159 ps meanwhile
relative error lower than 5% are achieved.
We underline that for the considered metal thickness t = 35 µm, the skin depth
is of about δ Cu (f = 1 GHz) ≈ 2.08 µm instead of δ Al (f = 1 GHz) ≈ 2.47 µm for
the aluminium. Obviously, for higher frequencies generally more than 4 GHz and
narrower lines, the interconnect resistance R is relatively important, so the frequency-
dependent R(f ) from skin depth effects should be taken into account.
4.3.1.3 Numerical Analyses Versus the Interconnect Lengths
In this subsection, microstrip lines with width w = 0.3 mm, and various lengths
d = {d 1 , d 2 , d 3 } are analysed. It is noteworthy that these lengths have been cho-
sen considering real cases of typical TLs for PLL circuits of DDR2 applications as
reported in [19]. According to formulations (4.10)–(4.12), we can calculate the aver-
age value of the per-unit-length parameters of these TLs up to their specific frequency
bandwidth f max (i), i = {1, 2, 3}. So, we get the results summarized in Table 4.1 for
different lengths of the line d i . During these simulations, rise times of the presented
signals are kept higher than 340 ps.
From these parameters, we compare the 50% propagation delays with the pro-
posed modelling method and the results from the standard electronic simulation tool
SPICE. For that we take the source and load parameters, respectively, as Rs = 10 ,
and L L = 1 nH. By varying the RL value, one gets the 50% propagation delays plotted
in Figs. 4.5. It is interesting to note that in each case, the symbol durations T s (i) of
the input data are assumed as a trapezoidal pulse with rise/fall times t r (i) = T s (i)/10.
These rise/fall times were set accordingly to the TL lengths d i .
We point out that the computation time duration with the proposed model was
lower than some ms by using a MATLAB program. As shown in the figures above,
we find that the computed propagation delays present very accurate values close to
SPICE simulations. We underline that the relative error over RL is higher than 5% for
the lengths d lower than 3 mm and higher than 10 mm. For this later, the error increases
considerably when RL is higher than 150 . It is interesting to note that when the load
impedance is very high, the reflections from the impedance mismatch would also
impact the 50% propagation delay. This is probably the reason for the difference
between the SPICE simulation and the polynomial approximation. Moreover, to
Table 4.1 Calculated RLC parameters of the TLs

Total R × d i () L × d i (nH) C × d i (pF) f max (GHz) T s,min
d 1 = 4 mm 0.164 3.13 0.161 5.28 670 ps
d 2 = 6 mm 0.204 4.68 0.242 3.52 1.00 ps
d 3 = 8 mm 0.237 6.23 0.322 2.64 1.33 ns
d 4 = 10 mm 0.26 7.88 0.403 2.17 1.61 ns
Fig. 4.5 Comparisons of 100

50% propagation delay SPICE
T (ps)
computed with SPICE model our model
50
and the proposed model for:
p
a d 1 = 4 mm, b d 2 = 6 mm,
c d 3 = 8 mm, and d d 4 = 0
0 100 200 300 400 500
10 mm for various values of
RL (Ω )
RL [48]
(a) d = 4 mm
100
SPICE
T (ps)
50 our model
p
0
0 100 200 300 400 500
RL (Ω )
(b) d = 6 mm
150
SPICE
T (ps)
100
our model
50
p
0
0 100 200 300 400 500
RL (Ω )
(c) d = 8 mm
400
SPICE
T (ps)
our model
200
p
0
50 100 150
RL (Ω )
(d) d = 10 mm
achieve more accurate delays, we must take into account frequency variations of
parameters R(f ), L(f ), and C(f ) which will be the next step of this study.
4.3.1.4 Conclusion
A modelling method of microelectronic interconnection networks with RL load

is successfully investigated in this article. By considering the second-order linear
model of this network, it was established how to determine the second-order equiva-
lent transfer function with first-order numerator. As an application, microstrip inter-
connections with different lengths and various values of the considered load were
investigated. After computations of the per-unit-length parameters R, L, and C, one
estimates also the 50% propagation delays by using the Elmore formulation [10]. As
a consequence, very accurate results were obtained with relative errors of about 5%
for interconnect lines having lengths between 4 mm and 10 mm. To achieve more
accurate, per-unit parameters versus frequency should be considered with high-order
approximation of the transfer function [20, 21]. Compared to the standard tools for
the SI analysis [24, 25], here the analysis of the structure can be performed with less
computation time and easy to implement for complex structures.
Thanks to its simplicity and its accuracy, the presented method can be useful
for the estimation of the complex structure as the tree networks constituting the
microelectronic integrated systems where the value of propagation delays needs to
be evaluated during the design process [26, 27].
4.3.2 Applications with RC and RLC Line Structures
This section focus is on the comparisons of time-domain results computed from RC

and RLC network-based interconnect transmission chain. The proposed modelling
method is compared with SPICE simulations. It is interesting to note that the SPICE
which uses mainly computation technique based on the nodal calculation method
is the industry standard for electrical simulation because of its accuracy and the
availability of free source code.
4.3.2.2 Distributed High-Speed RC Line (Particular Case of RLC Line

with Lu = 0)
Figure 4.6 depicts the design schematic of the simulated interconnection network. It
consists of the distributed RC model available in ADS library with per-unit-length
resistance Ru = 5 /mm, capacitance C u = 0.5 pF/mm, and physical length d = 5 mm,
which is loaded by RL = 100 and C L = {0.1 pF, 1 pF, 2 pF}. This interconnection
circuit is excited by a normalized square waveform pulse voltage with amplitude
V M = 1 V having internal impedance Rs = 5 and time duration t 0 = 100 ps. It
corresponds as well to a digital data source with 10 Gbit/s rate.
A-meter
Rs RC-line vo(t)
Ii(t) TRANSIENT
vi(t) (Ru,Cu,d) RL CL
Fig. 4.6 ADS schematic of the tested circuit comprised of RC line-driven by square wave source
having 10-Gbits/s rate and loaded by RL C L network [49]
4.3.2.3 Verification Results with RC Line
After transient simulation run from t min = 0 to t max = 300 ps and step Δt = 0.1 ps,
one gets the comparative results displayed in Fig. 4.6a for the output voltage and
shown in Fig. 4.6b for the time-dependent input current regarding the normalized
unit-step input.
The transient response from the reference SPICE computation regarding the dis-
tributed RC line model is plotted in grey full line, and those computed from the
proposed model are plotted in black dashed line. So, one observes a very good
agreement between the transient responses from the ADS model and the proposed
model responses. One evaluates here relative errors which are mainly due to the
numerical inaccuracy of lower than 5-%. In the case where Rs and C L negligible and
by varying the per-unit-length resistance Ru = {5, 10, 15 /mm} of the circuit shown
in Fig. 4.6 through ADS sweep simulation, one gets the transient results displayed in
Fig. 4.7 with the normalized unit-step input voltage. We can remark that as predicted
in theory, the 50-% propagation delay and the output attenuation increase when Ru
increases.
Furthermore, to check the effectiveness of the mathematical analysis on the tran-
sient response parameters detailed in subsection 4.4.3.1, comparisons with SPICE
computations were realized. Therefore, the results summarized in Table 4.2 are
obtained. It shows the assessments of the proposed different transient parameters
as the propagation delay, rise/fall times and also the voltage attenuation at the given
instant time t 0 (Fig. 4.8).
One points out that the results presented were calculated by implementing the
formulation established with the scientist standard tool MATLAB. The attenuation
Fig. 4.7 Transient result V model(C L=0.1pF)

comparisons from ADS and (a) V spice (C L=0.1pF)
from the model proposed(Ru 1.0 V model(C L=1pF)
V spice (C L=1pF)
= 5 /mm, C u =
Voltage, V
V model(C L=2pF)
0.5 pF/mm, d = 5 mm, and 0.5 V spice (C L=2pF)
RL = 100 ) [49]
0.0
0 100 200 300

Time, ps
(b)
100
ISPICE(CL =1pF)
Input current, A
Imodel(CL=1pF)
-100
0 100 200 300
Time, ps
Table 4.2 Comparison

Ru SPICE Proposed model
between the SI parameter
calculated with the proposed 5 /mm T p = 30 ps T p ≈ 27 ps
model and SPICE t r = 49 ps t r ≈ 51 ps
computations α(t 0 ) = 0.79 α(t 0 ) ≈ 0.76
10 /mm T p = 64 ps T p ≈ 59 ps
t r = 86 ps t r ≈ 89 ps
α(t 0 ) = 0.60 α(t 0 ) ≈ 0.54
15 /mm T p = 119 ps T p ≈ 101 ps
t r = 113 ps t r ≈ 120 ps
α(t 0 ) = 0.45 α(t 0 ) ≈ 0.40
Fig. 4.8 Unit-step responses

for Ru = {5, 10, 15 /mm}, 1.0
C u = 0.5 pF/mm, d = 5 mm Ω
=5
R u =10 Ω
Voltage, V
and RL = 100 [49] 0.5 Ru
5Ω
R u=1 SPICE
0.0 Mo del
0 50 100 150 200 250

Time, ps
can be estimated as the final value when the given pulse duration t 0 is higher than the
settling time. The steady-state final values are T (0) = {0.80, 0.67, 0.57} according
to Ru = {5, 10, 15 /mm}.
As the settling time for Ru = 5 /mm is of about t s ≈ 76 ps then lower than
the input pulse duration t 0 = 100 ps, the attenuation α(t 0 ) can be considered as
equal to T (0). As confirmed by Table 4.2, the results from the proposed model are
much closer to the SPICE computation. It means that to preserve the output voltage
amplitude as higher as possible, one should operate with digital signal having pulse
duration absolutely higher than the TL network settling time t s . In the next section,
the investigation of the RLC model by taking into account the inductive parameter
of the TL is presented.
4.3.2.4 Distributed High-Speed RLC Line
With the same configuration as in the previous subsection, an RLC model inter-
connection network as presented earlier in Fig. 4.6 was designed and simulated.
So, the results depicted in Fig. 4.9 are realized. Similar to the former study, these
simulations were performed with the equivalent distributed network comprised of
the RLC model having per-unit-length resistance Ru = 5 /mm with various sweep
inductance values L u = {0.2, 0.4, 0.6 nH/mm} and capacitance C u = 0.5 pF/mm
and with physical length d = 5 mm. The tested RLC line is driven by a voltage
Fig. 4.9 Transient unit-step

simulation results from the 1.0
proposed RLC model for Ru
Voltage, V
= 5 /mm, various sweep 0.5
inductances L u = {0.2, 0.4, L u=0.2nH
0.6 nH/mm}, and L u=0.4nH
capacitance C u = 0.5 pF/mm 0.0 L u=0.6nH
with physical length d =
5 mm loaded by RL = 100 0.0 0.1 0.2 0.3 0.4 0.5
[49] Time, ns
Table 4.3 Comparison of the

L u (nH/mm) SPICE (ps) Proposed model (ps)
RLC line propagation delays
calculated with the proposed 0.2 T p = 57 T p ≈ 56
model and SPICE 0.4 T p = 78 T p ≈ 75
computations
0.6 T p = 95 T p ≈ 89
source delivering a unit-step signal having amplitude V M = 1 V and loaded by RL =

100 . After transient simulation run from t min = 0 to t max = 500 ps step Δt = 2 ps,
the time-domain computation results’ model is displayed in Fig. 4.9. In difference
with the case of RC lines, here, overshoot phenomena and significant pure delays
have occurred. It is underlined that the inductive effects increase with the length of
interconnects. Despite these effects, we can find that once again, as forecasted in
theory, the signal 50-% propagation delay increases with the per-unit inductance L u .
In addition, according to the comparative results with respect to the calculation
of the propagation delay parameter, the numerical values addressed in Table 4.3 for
different values of per-unit-length inductance L u are realized. Compared with the
results presented in [45], we emphasize that for the interconnect line with 5-mm
length, better values of propagation delay relative errors are confirmed.
4.3.2.5 Conclusion
The relevance of microstrip interconnect analytical modelling is verified with cen-

timetre length line. The model can be applied to typically RC and RLC network-based
structure. Predictions of very high-speed signals with rise and fall time lower than ps
and periodical signal with 10 Gbps rate are presented. The behaviours of the transient
responses calculated with the proposed model and the propagation delay formulas
are well correlated to the SPICE simulations.
A modelling method of distributed interconnection network for the high-speed SI

analysis was investigated. The developed model is based on the interconnect TL
comprised of RLC network. For that, the TL is essentially characterized by its per-unit
electrical parameters R, L, and C and its physical length.
Thanks to the exploitation of the system transfer matrix under consideration, the
second-order analytical approximation of the global transfer function was estab-
lished. Then, it was demonstrated mathematically how to determine accurately the
transient response parameters such as rise time, 50-% propagation delay, and settling
time. It was found that the developed model provides an easy way for the SI parameter
evaluations whose exact and usually nonlinear interconnect system transfer function
remains analytically very complicated to explore. In order to evidence the relevance
of the introduced theoretic formulations yielded from the developed model, simu-
lations of circuitry comprised of loaded RC and RLC lines were carried out. Then,
comparisons with SPICE computations were also performed by considering input
square-wave pulse voltage having 10-Gbits/s rate in function of the TL parameters.
The main benefits of the presented modelling method lie on its simplicity, its
flexibility for the integration in the computation tools for the prediction of the layout
trace as the PCB or typical chip-to-chip interconnection. Furthermore, the following
remarks were found out:
(1) The proposed modelling method enables to extract efficiently transient param-
eters.
(2) This generates attenuation permitting to predict the level of the output voltage
according to the input signal time duration.
(3) The programming implementing the investigated method algorithm executed
with MATLAB was run during very less computation time only in the order of
ms for generating considerably accurate results.
(4) The developed discrete model can be adapted to the computed-aided design of
all mixed or analog–digital electronic system dedicated in particular to the SI
characterization.
In the next step of this work, the application of the validated modelling method
for the prediction of the high-frequency analog–digital module operating at several
Gbits/s is outlined. In addition, the perturbation SI effects as reflections, ringing, and
crosstalk will be investigated by considering the total transfer matrices of systems
comprised of multi-conductor interconnect lines.
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Chapter 5
Analytical Modeling Methodology
of Single-Input Multiple-Output (SIMO)
Symmetric Tree Interconnects by Using
Lumped Element L-Cell
Blaise Ravelo
5.1 Introduction
Since the invention of the ICs by Jack S. Kilby from Texas Instruments [1], the
mankind way of life has been increasingly conditioned by the evolution of electronic
systems toward the use of personal computers and multifunction mobile gadgets.
To meet this spectacular progress, high-performance reconfigurable processors and
ultra-high-speed wired and wireless communicating systems operating up to tens of
GHz were deployed [2–9]. Due to the unceasing increase of the electronic system
integration, the modern high-speed electronic equipment meets different techno-
logical roadblocks due to the interconnect complexity [10–15]. In addition to the
investigation on the apparition of EMI and EMC, many works stating the power
loss and the interconnect delay effects, for example, in the RF/digital devices were
done [6, 16–23]. Because of the undesired interconnection perturbations, it has been
evidenced that the interconnect delays of high-speed digital IC dominate widely gate
delays [5]. During the data stream transmission, these technological issues can be
sources of signal distortions, asynchronous effects of the transmitted analog signals
and erroneous symbols. So, intensive researches were performed on the modeling
of the interconnect networks in order to predict the signal integrity (SI) [9, 11–15,
17–24]. In order to minimize the cost and energy consumption, and also the quality
of shared data and clock signals, multipath circuits play a fundamental role for the
packaged IC system design of ICs packaged in different levels this later is fundamen-
tal [25–28]. In this optic, different topologies as a typical H tree interconnect [17, 25]
were investigated. Figure 5.1 shows the implementation of the H tree structure with
four levels as a typical surface layout used in Caltech score [4] and Quicksilver’s
ACM [8].
B. Ravelo (B)

80 B. Ravelo
(a) Yn
Zn
Yk+1 Yn-1
Zk+1
Yk
Zk
Zn
Zk+1 Yn
Y2
Z2 Yk+1
N0 Z1 N1
N2
v0 Y1
Z2 Yk+1
Y2 Zk+1
Yn
Nk Zn
Zk Nk+1 Nn-1
Yk Zk+1 Nn
Yk+1 Yn-1 Zn
Yn vn
(b) N0 Z1 N1 Z2/2 N2 Zk/2k-1Nk Zn/2n-1 N

n
v0 Y1 2Y2 2k-1Yk 2n-1Yn vn
Fig. 5.1 Symmetrical tree network composed of different cells formed by Z k -series impedance
and Y k -parallel admittance (k = {1, …, n})
In order to deal with the bottleneck caused by the interconnect imperfection, inten-
sive researches for the enhancements of on-chip interconnect have been conducted
[29–36]. Different techniques enabling VLSI interconnect optimization have been
deployed. For example, with various topological approaches for wire sizing and cross
talk optimizations, signal path algorithms (Steiner tree algorithm, Greedy BST/DME
algorithm, planar clock routing) and classical models have been explored [24]. By
exploiting the moment matching of the transfer response, simulation technique of the
high-speed clock tree is presented by considering buffer insertions. But as reported
succinctly in [29], such a technique is more adapted to the lumped tree network with
few numbers of cells. Moreover, topologies of on-chip interconnects with arbitrary
numbers of levels are presented [30]. Thus, by deeming with MOS distribution net-
works, optimized computation techniques of clock tree level have been introduced
for mixed system [31]. On the other hand, based on the investigation of row and
input flit width in compiled message, a modeling method of hardware performance
analysis with Hamming product codes is presented in [32] for the improvement of
on-chip interconnect energy. Moreover, new characterization method of serial link
bus delay in mobile terminal antennas operating at multi-gigabits speed is described
5 Analytical Modeling Methodology of Single-Input … 81
in [33]. Furthermore, a correction method of interconnect degradation by using active

circuits with negative group delay is introduced in [34–36].
To estimate the SI parameters as the interconnect delay, the most popular method
is based on the use of RC-models as introduced by Elmore in 1948 [37]. The main
advantage of this model lies on its simplicity and its possibility for fast delay estima-
tion when considering sophisticated signal paths of integrated system. However, its
drawback consists of its high imprecision compared to other high-order delay mod-
els. It was reported that Elmore model can involve more than 30% relative errors
[38, 39]. For this reason, more accurate approximated second-order RLC model was
developed in [39–41]. Furthermore, as developed in [39, 40], authors determine the
step unit response of lumped RLC-tree networks via second moments of the polyno-
mial transfer function. The main advantage of this second-order delay model is that
it enables to investigate the signal delay with good accuracy even for non-monotone
time domain responses. Till now, most of employed algorithms and modeling meth-
ods for computing the transient responses induced by lumped tree mesh networks
are calculated from the sum of the estimated polynomial transfer function between
the branches of different nodes [17, 25, 41–48]. In [48–50], more general modeling
approach enabling to predict the ultra-wideband responses of microstrip interconnec-
tions is proposed. With the increase of the circuit complexity, the interconnections
are more and more complex as the case of tree networks [41–48]. But accurate and
more relevant models are still needed for the multi-level T-tree interconnections as
proposed in [51–53].
In order to face out this technical limitation, an accurate reduced method for
extracting the behavioral transfer function of multi-level T-tree networks is developed
in this chapter. It is organized in four different sections. In Sect. 5.2, a general
topology of symmetrical T-tree networks consisted of lumped L-cells is analyzed.
The transformation of this typical SIMO circuit to SISO networks is established.
By using the transfer matrix operation and analysis, the mathematical expression
of the whole network transfer function is developed. Section 5.3 is focused on the
particular application based on the characterization of the T-tree networks comprised
of different and identical RLC-cells. With the transfer function model, an estimation
of the whole tree signal attenuation will be provided. To check the efficiency of the
developed theory, comparative studies between the models developed and SPICE
computations based on realistic examples of T-tree interconnect structures will be
made in Sect. 5.4. Lastly, concluding remarks will be drawn in Sect. 5.5.
5.2 General Lumped Symmetric Tree Modeling
Before the examination of the most important parts of this chapter which is mainly
focused on the T-tree electrical network modeling methodology, the clarification of
the preliminary fundamental theory used along the study is presented in the following
subsection.
82 B. Ravelo
5.2.1 General SIMO Configuration
Along this chapter, the topological analysis of multi- or n-level symmetrical lumped
T-tree distribution as a SIMO-type system is focused on the representation introduced
in Fig. 5.1a.
One can see that at each node Nk (k = {1, . . . , n − 1}), two identical L-cells are
connected in parallel. So, according to the voltage division rule, the input equivalent
impedance Z eq (k) seen at node N k is the half of the input impedance of the next
branch:
Zeq (k) = Zin (k)/2. (5.1)
It means that the equivalent admittance is equal to the double of the input
admittance of the next branch:
Yeq (k) = 2Yin (k). (5.2)
This finding explains the electrical equivalence between the branch N 0 N n of

Fig. 5.1a as traced in gray dashed path and the SISO-type circuit depicted in Fig. 5.1b.
5.2.2 SIMO–SISO Transform
This finding explains the electrical equivalence between the branch N 0 N n of Fig. 5.2a
as traced in gray dashed path and the SISO-type circuit depicted in Fig. 5.2b.
As highlighted in Fig. 5.3, between the consecutive planes (Pk ) and (Pk+1 ), the
piece of circuit connected in the branch (N k N k+1 ) is formed by L-cell having:
Zs = Zk+1 /2k , (5.3)
series impedance and:
Yp = 2k Yk+1 , (5.4)
parallel admittance. For the sake of simplification, the input current and the input
impedance seen at the plane (Pk ) are, respectively, denoted by I k and Z in (k).
By considering the circuit of Fig. 5.3b, the input impedance seen at the node N n
which is located at the whole network termination is equal to:

Zin (n) = 1/ 2n−1 Yn . (5.5)
Based on the equivalent impedance calculation applied to the basic cell shown in
Fig. 5.3, it is known that the input impedance Z in (k) seen at the node N k is equal to:
(a) Yn
Zn
Yk+1 Yn-1
Zk+1
Yk
Zk
Zn
Zk+1 Yn
Y2
Z2 Yk+1
N0 Z1 N1
N2
v0 Y1
Z2 Yk+1
Y2 Zk+1
Yn
Nk Zn
Zk Nk+1 Nn-1
Yk Zk+1 Nn
Yk+1 Yn-1 Zn
Yn vn
(b) N0 Z1 N1 Z2/2 N2 Zk/2k-1Nk Zn/2n-1 N

n
v0 Y1 2Y2 2k-1Yk 2n-1Yn vn
Fig. 5.2 Reduced electrical SISO circuit equivalent to the gray dashed signal path
(Pk) (Pk+1)
Ik Nk Ik+1 Zk+1/2k
2k-1Yk Zin(k+1)
Zin(k)
Fig. 5.3 Basic cell at the kth stage of the reduced circuit shown in Fig. 5.2b

Zin (k) = 21−k /Yk // Zk+1 /2k + Zin (k + 1) . (5.6)
So that, for k = {1, …, n}, the partial input impedance can be expressed as:

2−k Zk+1 +Zin (k+1)
1+2k−1 Yk [2−k Zk+1 +Zin (k+1)]
, if k ≤ n − 1
Zin (k) = . (5.7)
1
2n−1 Yn
, if k = n
The current divider principle applied again to the piece of circuit shown in Fig. 5.4
enables to write the expression of current I k flowing through electrical branch N k −1 N k
for k = {2, …, n}. For the initial case k = 1, I 1 can be determined directly with Ohm’s
84 B. Ravelo
Cn
Ck
Rn
Rk Rn
Rk
C2 Cn
Ck
N0 R1 N1 R2
R2 N2
vin(t)
C1 Ck
C2 Cn
Rk
Rk Nk Rn
Rn Nn
Ck
vout(t)
Cn
Fig. 5.4 Circuit diagram of n-level RC-tree network under study
law. Therefore, the general expression of the current, I k , is given by:

Vi
Zin (1)+Z1
, if k = 0
Ik+1 = . (5.8)
Ik
1+2k−1 Yk [2−k Zk+1 +Zin (k+1)]
, if k ≥ 1
5.2.3 T-Matrix Modeling
By denoting [T k −1 ] the elementary transfer matrix of the (k − 1)th cell in the branch
N k −1 N k , similarly to the basic equation of L-cell transfer matrix expressed earlier in
(5.7), one surmises the following formulation:

1 + Z · Y Zk
Tk−1 = k−1 k k 2k−1 . (5.9)
2 Yk 1
Subsequently, the association of n-cells in cascade represented in Fig. 5.4 should

generate a global whole transfer matrix equal to the product of [T k −1 ] when k =
{1, …, n}. In the remainder of the chapter, the whole transfer matrix corresponding
to the reduced matrix of the first branch of a n-branch clock tree is denoted [T 1,n ].
According to the equivalent reduced circuit of Fig. 5.3b, it is mathematically defined
as:
k=n
1 + Zk · Yk 2Zk−1
k
T1,n = . (5.10)
2k−1 Yk 1
k=1
This matrix product explains that the voltage global transfer function denoted
H n (s) corresponding to this matrix must be calculated recursively from the last ele-
mentary matrix [T k,n ]. Though, the latter can be determined progressively via the
following matrix recursive relation:

[Tk ] for k = n
[Tk−1,n ] = . (5.11)
[Tk,n ] · [Tk−1 ] for k < n
For more explicit representation of literal expressions, in the next part of this
chapter, [T 1,k ] will be expressed as follows:

T11 (k) T12 (k)
T1,k = . (5.12)
T21 (k) T22 (k)
By combining former Eqs. (5.9), (5.11) and (5.12), and varying the integer k from
0 to (n − 1), the following recursive relations between the two elements T 11 and T 21
of matrices [T 1,k −1 ] and [T 1,k ] are established:

(1 + Zk · Yk )T11 (k + 1) + 21−k Zk · T21 (k + 1) for 1 ≤ k < n

T11 (k) = , (5.13)
1 + Yn · Zn for k = n

k−1
2 Yk T11 (k + 1) + T21 (k + 1) for 1 ≤ k < n
T21 (k) = . (5.14)
2n−1 Yn for k = n
5.2.4 Modeling of Different RC-Cell-Based Symmetric Trees
To achieve a better insight into the present theoretic approach, let us consider a
multi-level T-tree network comprised of different lumped L-cells shown in Fig. 5.4.
5.2.4.1 Topological Description
After the examination of this tree network configuration, we will determine the
reduced transfer function of the whole system including the load effect. Then, the
calculation formula of the high-order linear propagation delay will be elaborated.
In this case, it was introduced in Chap. 2 that for high-order structures composed
of n elementary systems in cascade as depicted in Fig. 5.4, the total propagation
delay was approximated by:
86 B. Ravelo

n
Tp = Rk · Ck . (5.15)
k=1
But this estimation presents relative errors higher than 35% compared to SPICE
simulations. This finding motivates me to develop a novel mathematical model with
higher accuracy.
5.2.4.2 SIMO–SISO Transform
For starting, Fig. 5.4 represents the tree network diagram investigated in this chapter.
It is composed of L-form lumped elements having n-levels. We can see that at each
node N k (k = {1, …, n}), two L-cells are connected in parallel. According to the
circuit theory, the input equivalent impedance at this node is the half of the input
impedance of the next branch. This finding explains the chain of electrical equivalent
circuit of the branch traced in gray path of the circuit diagram displayed in Fig. 5.4
and that one depicted in Fig. 5.5.
As highlighted in Fig. 5.6, we find that between the consecutive plans (Pk )
and (Pk+1 ), the network represented by the branch (N k N k+1 ) is formed by a series
resistance:
Rs = Rk /2k−1 , (5.16)
and a parallel capacitance:
Cp = 2k−1 Ck . (5.17)
For the sake of simplification, the input impedance seen at the plan (Pk ) is denoted
Zk.
N0 R1 N1 R2/2 N2 Rk/k Nk Rn/n Nn

vout(t)
vin(t)
C1 C2/2 Ck/k Cn/n
Fig. 5.5 Electrical equivalent network of the gray path of tree circuit diagram shown in Fig. 5.4
Fig. 5.6 Piece of elementary (Pk) (Pk+1)

circuit equivalent to the tree
network for the iterative Ik Rk/2 k-1
Nk Ik+1
calculation of the input
impedance at each node of 2k-1Ck Zk+1
the tree Zk
Through simple equivalent impedance calculation, we can establish the input

impedance, Z k seen at the node, N k in function of Z k+1 which is expressed as:

Zk+1 (s)
21−k Rk + 1+2k−1 Ck ·s·Zk+1 (s)
, if k ≤ n − 1
Zk (s) = , (5.18)
1
2n Cn ·s
, if k = n
where s is the Laplace variable.
5.2.4.3 T-Matrix Model
This subsection focus is on the modeling of the linear network introduced in Fig. 5.4.
Being given that this lumped network is a linear circuit, its transfer equation should
be governed also by a linear differential equation. This finding leads us to suppose
the elements of the ABCD matrix:

M11,n (s) M12,n (s)
[Mn (s)] =
M21,n (s) M22,n (s)
n
= MABCD,k (s) . (5.19)
k=1
n 1 + Rk · Ck · s 2Rk−1
k
= 1
k=1 2k−1 Ck ·s
1
as polynomial expressions having real coefficients. For the simplification, one adopts
that the initial matrix is defined as:

1 + R1 · C1 · s R1
[M1 (s)] = MABCD,1 (s) = . (5.20)
C1 · s 1
It means that:
M11,1 (s) = 1 + R1 · C1 · s, (5.21)
M12,1 (s) = R1 . (5.22)
So that, the first two elements of the global ABCD matrix [Mn (s)] can be written
as:

n
M11,n (s) = 1 + ak · sk , (5.23)
k=1

n
M12,n (s) = bk · sk , (5.24)
k=0
88 B. Ravelo
where ak and bk are real coefficients. For k = {1, …, n}, the above ABCD matrix of
the whole tree network can be determined with the successive matrix multiplication:

1 + Rk+1 · Ck+1 · s Rk+1
Mk+1 (s) = [Mk (s)] · 1
2k . (5.25)
2k Ck+1 ·s
1
5.2.4.4 VTF Model
It is interesting to recall that the physical system transfer function can be determined
from the first element of the ABCD matrix via the following expression:
1
Fn (s) = . (5.26)
M11 (s)
As illustrated in the previous subsection, the transfer function of the circuit shown
in Fig. 5.4 can be determined successively by the multiplication of elementary transfer
matrices corresponding to the constituting elementary cells. By considering the real
coefficients ak , it can be expressed as a linear function:
Vout (s) 1
Fn (s) = = n . (5.27)
Vin (s) 1 + k=1 ak (n) · sk
It was established that the coefficients ak are defined as:

R1 · C1 if n = 1
a1 (n) = , (5.28)
Rn · Cn + a1 (n − 1) + 2n−1 Cn · b0 (n − 1) if n ≥ 2

0 if n = 1
a2 (n) = , (5.29)
Rn · Cn · a1 (n − 1) + a2 (n − 1) + 2n−1 Cn · b1 (n − 1) if n ≥ 2
with:

R1 if n = 1
b0 (n) = , (5.30)
Rn + b0 (n − 1) if n ≥ 2

0 if n = 1
b1 (n) = . (5.31)
21−n Rn · a1 (n − 1) + b1 (n − 1) if n ≥ 2
By considering this polynomial transfer function, we can estimate more accurately

the propagation delay induced by the tree network.
5.2.4.5 Delay Propagation Model
The propagation delay calculation process developed in this chapter is deduced from
the transfer function direct poles. An example of pole extraction is proposed in [28].
For k = {1, 2}, consider the first-order systems with voltage transfer function:
1
Fk (s) = , (5.32)
1 + τk · s
where τk are time constants of elementary transfer functions. We assume T pk as the

propagation delay or the time made by the output signal to attain the 50% of F k final
value. By denoting:
λ = Tp2 /Tp1 , (5.33)
supposing that T p2 > T p1 , it is possible to express the total propagation delay T p of

the system in cascade:
F(s) = F1 (s) · F2 (s). (5.34)
A deep mathematical investigation conducts the following formula of equivalent

propagation delay:
√
√1
Tp ≈ 0.41 · Tp1 e λ + λ · e λ , (5.35)
if λ ≤ 4, and if not:
ln[2λ/(λ − 1)]
Tp ≈ λ · Tp1 · . (5.36)
ln(2)
5.2.5 Modeling of Different RLC-Cell-Based Symmetric

Trees
By taking:
Zk = Rk + Lk s, (5.37)
and:
Yk = Ck s, (5.38)
90 B. Ravelo
the modeling method of previous Sect. 5.2.2 can be transposed to the theoretical
analysis of the Rk L k C k -tree network distribution (k = {1, …, n}).
In this case, the SISO network exposed in Fig. 5.2b will become the lumped
Rk L k C k -networks in cascade presented in Fig. 5.7. Acting as a linear circuit, the
transfer matrix of this network should be typically governed also by linear differential
equations.
This finding leads us to suppose the elements of the transfer matrix, [T 1,k −1 ], as
polynomial expressions defined by the real coefficients denoted λ11,k and λ21,k for k
varying from 1 to (n − 1):
⎧
⎨
k
1+ λ11,k (l)sl for 1 ≤ k ≤ n − 1
T11 (k) = , (5.39)
⎩ l=1
1 + Rn · Cn · s + Ln · Cn · s for k = n
2
⎧ k
⎨
λ (l)sl for 1 ≤ k ≤ n − 1
T21 (k) = l=1 21,k . (5.40)
⎩ n−1
2 Cn · s for k = n
In this case, the whole transfer function of the circuit described in Fig. 5.7 can be
written as follows:
1
Hn (s) = n . (5.41)
1+ l=1 λ11,n (l)s
l
The real coefficients λ11,n can be calculated easily via substitutions of (5.39)
and (5.40), respectively, into the iterative relations expressed in (5.28) and (5.29)
introduced earlier. Hence, this yields the following iterative relations enabling the
determination of the first two coefficients corresponding to λ11,n−k (l) and λ21,n−k (l)
for l = {1, 2}:

Rn · Cn if k = 0 ,
λ11,n−k (1) =
λ11,n−k+1 (1) + Rn−k 21−n+k λ21,n−k+1 (1) + Cn−k , if k ≥ 1
(5.42)
N0 R1 L1 N Rk/2k Lk/2k Nk Rn/2n Ln/2n Nn

1
vin C1 2 kC k 2nCn vout
Fig. 5.7 Schematic of the reduced SISO circuit equivalent to n-level RLC-tree network
⎧
⎪
⎪ L C if k = 0
⎨ n n
λ11,n−k (2) = λ11,n−k+1 (2) + Rn−k Cn−k λ11,n−k+1 (1) + 21−n+k λ21,n−k+1 (2) .
⎪
⎪
⎩ +L 2 1−n+k λ (1) + C if k ≥ 1
n−k 21,n−k+1 n−k
(5.43)
The combination of polynomial expressions (5.39) and (5.40) with iterative

expression (5.29) implies hereafter two coefficients of the element T 21 :

0 if k = 0
λ21,n−k (1) = , (5.44)
2 n−k−1
Cn−k + λ21,n−k+1 (1) if k ≥ 1

0 if k = 0
λ21,n−k (2) = . (5.45)
2n−k−1 Cn−k λ11,n−k+1 (1) + λ21,n−k+1 (2) if k ≥ 1
5.2.6 VTF Modeling
Accordingly, through successive calculations from the output termination of cascaded

network presented in Fig. 5.7, the following partial transfer function is yielded:
V [N (n)] 1
Hn−k (s) = = . (5.46)
V [N (k)] T11 (k)
As noted that this partial transfer function is also equal to the whole transfer
function of n-level tree distribution, H n (s) if k = 0. Hence, knowing [T 1,n ], the
global transfer function with the following relation can be deduced:
V [N (n)] 1
Hn (s) = = . (5.47)
V [N (0)] T11 (n)
Using the latter and by taking into account recursive relations (5.28) and (5.29),
literal analytical calculations were established for the four transfer functions corre-
sponding to n = {1, …, 4}. Therefore, the literal expressions of H n (s) are addressed
in Table 5.1 according to the lumped tree network formed by different Z k Y k -cells
for k = {1, …, n}.
92 B. Ravelo
Table 5.1 Transfer functions of L-cell tree networks for n = {1, …, 4}

n Transfer function, H n (s)
1 H1 (s) = 1
1+Z1 Y1
2 H2 (s) = 1
(1+Z1 Y1 )(1+Z2 Y2 )+2Z1 Y2
3 H3 (s) = 1
(1 + Z1 Y1 )[(1 + Z2 Y2 )(1 + Z3 Y3 ) + 2Z2 Y3 ]
+ 2Z1 [Y2 (1 + Z3 Y3 ) + 2Y3 ]
4 H4 (s) = 1
(1 + Z1 Y1 )[(1 + Z2 Y2 )[(1 + Z3 Y3 )(1 + Z4 Y4 ) + 2Z3 Y4 ]
+ 2Z2 [Y3 (1 + Z4 Y4 ) + 2Y4 ]] + Z1 [2Y2 [(1 + Z3 Y3 )(1 + Z4 Y4 ) + 2Z3 Y4 ]
+ 4Y3 (1 + Z4 Y4 ) + 8Y4 ]
5.3 Analyses of Particular Cases of Interconnect Trees
5.3.1 Modeling of Symmetric Tree Constituted by Identical

L-Cell Elements
As particular case of previous study, in this subsection, the T-tree interconnect net-
work with identical L-cells is investigated by taking Z k = Z and Y k = Y for all the
values of integer k. In this case, expression (5.7) of the input impedance, Z in (k) seen
at the plan (Pk ), becomes:

Zin (k+1)
21−k Z + 1+2k−1 ·Y ·Zin (k+1)
, if k ≤ n − 1
Zin (k) = . (5.48)
1
2n Y
, if k = n
The expression of current I k flowing through the electrical branch N k −1 N k induced

from Eq. (5.8) will be transformed as:

Vi
Z+Zin (1)
, if k = 0
Ik+1 = . (5.49)
Ik
1+2k−1 Y ·Zin (k+1)
, if k ≥ 1
Moreover, the elementary transfer matrix of the (k − 1)th cell which constitutes
the branch N k −1 N k will be simplified as:

1 + Z · Y 2k−1
Z
Tk−1 = k−1 . (5.50)
2 Y 1
It implies that the equivalent whole transfer matrix, [T 1,n ], expressed in (5.9) will
become:
k=n
1 + ZY 2k−1
Z
T1,n = . (5.51)
2k−1 Y 1
k=1
Hence, previous recursive relations (5.39) and (5.40) governing the two elements
of the [T 1,k −1 ] matrix will be expressed as follows:
T11 (k − 1) = (1 + Z · Y )T11 (k) + 2−k+1 Z · T21 (k), (5.52)
T21 (k − 1) = 2k−1 Y · T11 (k) + T21 (k). (5.53)
The elements of the last transfer matrix, [T n ], become:
T11 (n) = 1 + Y · Z, (5.54)
T21 (n) = 2n−1 Y . (5.55)
Owing to these last four expressions, literal analytical calculations were realized
for the six transfer functions of n-level tree network comprised of identical L-cells
for n = {1, …, 6}. The associated analytical VTF of the L-cell-based tree structure
for these values of n is addressed in Table 5.2.
Furthermore, according to expression (5.7), the derived literal expressions of the
associated input impedance for the same number of level n are exposed in Table 5.3.
Table 5.2 Transfer functions

of L-cell tree networks
formed by Z-series 1 H1 (s) = 1
1+ZY
impedance and Y-parallel 2 H2 (s) = 1
admittance for n = {1, …, 6} 1+4ZY +Z 2 Y 2
3 H3 (s) = 1
1+11ZY +7Z 2 Y 2 +Z 3 Y 3
4 H4 (s) = 1
1+26ZY +30Z 2 Y 2 +10Z 3 Y 3 +Z 4 Y 4
5 H5 (s) = 1
1+57ZY +102Z 2 Y 2 +58Z 3 Y 3 +13Z 4 Y 4 +Z 5 Y 5
6 H6 (s) = 1
1+120ZY +303Z 2 Y 2 +256Z 3 Y 3 +95Z 4 Y 4 +16Z 5 Y 5 +Z 6 Y 6
94 B. Ravelo
Table 5.3 Input impedances,

n Input impedance, Z in (N k )
Z in (k + 1) seen at the plan,
1+ZY
(Pk ) for n-cell tree networks 1 Zn (s) = 2n−1 Y
formed by Z-series impedance 1+4ZY +Z 2 Y 2
2 Zn−1 (s) = 2n−2 Y (3+ZY )
and Y-parallel admittance
3 1+11ZY +7Z 2 Y 2 +Z 3 Y 3
Zn−2 (s) = 2n−3 Y (7+6ZY +Z 2 Y 2 )
1+26ZY +30Z 2 Y 2 +10Z 3 Y 3 +Z 4 Y 4
4 Zn−3 (s) = 2n−4 Y [(1+ZY )(3+ZY )(5+ZY )]
5 (1+ZY )(1+56ZY +46Z 2 Y 2 +12Z 3 Y 3 +Z 4 Y 4 )
Zn−4 (s) = 2n−5 Y [31+72ZY +48Z 2 Y 2 +12Z 3 Y 3 +Z 4 Y 4 ]
6 1+120ZY +303Z 2 Y 2 +256Z 3 Y 3 +95Z 4 Y 4 +16Z 5 Y 5 +Z 6 Y 6

Zn−5 (s) = 2n−6 Y (3+ZY )(3+6ZY +Z 2 Y 2 )(7+6ZY +Z 2 Y 2 )
5.3.2 Modeling of Identical RLC-Cell-Based Symmetric Tree
The modeling method of the identical RLC T-tree network can be realized from the
former subsection analysis by taking Rk = R and C k = C. So that, the two elements
of transfer matrix [T 1,n−k ], T 11 and T 21 , are supposed written as follows:

n−k
T11 (n − k) = 1 + λ11,n−k (l) · sl , (5.56)
l=1

n−k
T21 (n − k) = λ21,n−k (l)sl , (5.57)
l=1
and
T11 (n) = 1 + R · C · s + L · C · s2 , (5.58)
T21 (n) = 2n−1 C · s. (5.59)
By identification and turning over the k-integer values, the first two real
coefficients λ11,n−k and λ21,n−k are, respectively, expressed as:

R·C if k = 0
λ11,n−k (1) = , (5.60)
R · C + λ11,n−k+1 (1) + 21−n+k R · λ21,n−k+1 (1) if k ≥ 1
⎧
⎨L · C if k = 0
λ11,n−k (2) = R · C · λ11,n−k+1 (1) + λ11,n−k+1 (2) ,
⎩ 1−n+k
+2 R · λ21,n−k+1 (2) + L · λ21,n−k+1 (1) + L · C if k ≥ 1
(5.61)
and:

2n−1 C if k = 0
λ21,n−k (1) = , (5.62)
2n−k−1 C + λ21,n−k+1 (1) if k ≥ 1

0 if k = 0
λ21,n−k (2) = . (5.63)
2n−k−1 Cλ11,n−k+1 (1) + λ21,n−k+1 (2) if k ≥ 1
To illustrate the relevance of the literal model developed in more natural point
of view, further analysis of the RLC T-tree network time domain responses will be
made in the next subsection.
5.3.3 Time Domain Analysis
During the analysis of analog–digital or mixed SI propagating through the electronic

interconnects as the T-tree networks, similar to most of mixed system investigation,
time domain analyses constitute the fundamental way. It enables, for example, to
determine the relevant expressions of the output voltage attenuation prior to transient
square wave input voltage. In this case, it is important to note that as reported in [39,
48, 49], the base bandwidth of the considered digital signal is usually linked to its
rise time t r by relation (2.33). This frequency band limitation allows the reduction
or simplification of the transfer function H n (s) denominator by proceeding with the
polynomial limited expansion. For the case of n-level RLC-tree network, the second-
order approximated transfer function associated with the whole circuit represented
in Fig. 5.7 by taking:
Z = R + Ls, (5.64)
and:
Y = Cs, (5.65)
can be formulated as follows:

1 1
Hn (s) = n ≈ . (5.66)
1+ l=1 λ 11,n (l)s l 1 + λ 11,n (1)s + λ11,n (2)s2 + · · ·
This expression represents the understudy symmetrical RLC-tree network transfer

function in function of the level number n. So, one can determine easily the tree
network SI parameters as the signal attenuation. By considering the unit step response
of the transfer function first-order model, the temporal signal attenuation at the time
t = T can be written as follows:
96 B. Ravelo

vn (T ) T
αn = = 1 − exp − . (5.67)
v0 (T ) λ11,n (1)
For the validation of all above theoretic concepts, concrete examples of application
based on the RLC-interconnect T-tree network modeling are proposed in the next
section.
To confirm the relevance of these theoretical formulae, frequency and transient anal-
yses of a lumped RC-tree network assumed as a high-order electronic circuit are
proposed in the next section.
5.4.1 Application with Microstrip Interconnect Tree Modeled

by RC-Network
The results explored in this section are run in the SPICE-ADS environment of the
electrical/electronic circuit simulator in commercial provided by Agilent™. Four-
level lumped tree distribution network was first designed, analyzed and simulated.
5.4.1.1 Proof-of-Concept Description
Figure 5.8 represents the symmetric four-level RLC-tree. Similar to the practical
cases of logic gate numerical circuit input impedances, we assume that the loads Z L
are a capacitor C L . This latter is considered as a variable parameter as a capacitance
in parallel with C 4 during the calculation. The source impedance Z s is considered as
a resistance Rs = 2 . By using the transfer function expression defined in Eq. (5.27),
the responses of the following proof of concept displayed in Fig. 5.4 was calculated.
This symmetric tree proof of concept is composed of different RC-cells cascaded
with table parameters {R1 = 3 , R2 = 20 , R3 = 60 , R4 = 160 } and {C 1
= 1 pF, C 2 = 5 pF, C 3 = 5 pF, C 4 = 1.5 pF}. After the MATLAB implementation
of the mathematical model established previously in Sect. 5.2, the responses of the
circuit under study were computed both in frequency and in time domains.
Then by varying the C L value from 0 to 9 pF, we obtain the comparison results in
frequency domain with SPICE simulation plotted in Fig. 5.9. can see that the transfer
function frequency responses from the polynomial model developed in this chapter
ZL
ZL ZL ZL
C4 Output C4 C4
C4
Vout(t)
R4 R4 R4
R4 R4 ZL ZL R4
ZL R4 R4 ZL
C4 C4
R3 C3 C3 R3
C4 R3 R3 C4
C3 C3
C2 R2 C1 R2 C2
R1
Zs
Vin(t)
Input
Fig. 5.8 Circuit diagram of the RC-tree circuit considered loaded by Z L
Fig. 5.9 Transfer function (a) 0

frequency responses: C L =0pF
|Vout /Vin | (dB)
C L =2pF
a magnitude and b phase C L =5pF
C L =7pF
C L =9pF
-40
SPICE
Model
-80
0 1 2 3 4 5
Frequency (GHz)
(b) 0
phase(Vout /Vin ) (dB)
C L (SPICE)=2pF
C L (Model) =2 pF
C L (SPICE) =9pF
-100 C L (Model) =9 pF
-200
0 1 2 3 4 5
Frequency (GHz)
are well correlated to the simulations carried out with ADS® from DC to 5 GHz.
We can see that the attenuation and the phase shift increase with the frequency. This
effect is mainly the source of the numerical signal degradation caused by the tree
network.
98 B. Ravelo
Fig. 5.10 Transient Input

responses modeled and 1.0
simulated
Voltage (V)
0.5 C L =0pF
C L =2pF
C L =5pF
SPICE C L =7pF
0.0 Model C L =9pF
0 2 4 6 8 10
Time (ns)
Fig. 5.11 Comparisons of

the propagation delays
calculated with the model
proposed and simulated with
SPICE model
To demonstrate the effectiveness of the model proposed in time domain, a high-speed

step signal with slow rise time was injected in the circuit under test. Subsequently, we
generate the transient response results plotted in Fig. 5.10. As expected, we observe
an excellent correlation between the results from transient computation tools of
SPICE-ADS (plotted in full gray curves) and the responses from the model proposed
(plotted in dashed black curves) for various values of the load capacitance C L value
from 0 to 9 pF.
The propagation delays simulated and calculated are also evaluated. As illustrated
in Fig. 5.11, a very good correlation between SPICE and model propagation delays
is realized with relative error lower than 4%.
This modeling method is particularly useful for the signal integrity investigation
through the symmetrical interconnect tree network. The model developed in this
chapter can be applied for the analysis of PCB or microelectronic interconnect effects,
and it is also helpful for the design guide of manufacturing engineering.
5.4.1.4 Conclusion
In nutshell, an analytical modeling method of high-level linear clock tree intercon-

nect networks is established in this chapter. The reduction method conducting the
calculation of the propagation delay expression through the linear transfer function
is provided. It enables to perform a very high-accuracy investigation of electronic

interconnect delay. To get a good insight into the model developed, a polynomial
model of cascaded linear circuit was considered. Then, the basic formulae enabling
to calculate the signal propagation delay in function of the transfer function charac-
teristics were established. According to the verification results, very good agreements
between the model proposed and the simulations with the standard computation tools
were observed. It was assessed that the propagation delay model developed enables
to achieve a relative accuracy lower than 4%.
In the continuation of this work, the method introduced is particularly useful
for the microelectronic signal integrity prediction. Other than the accuracy of the
delay model established, we have a promising benefit in terms of simplicity and also
the time duration compared to standard full wave computational tools [29–31]. The
integrated interconnect by taking into account the EMI and EMC environments as
the near- and far-end cross talk (as reported in [3–5]) on the delay model will be
investigated.
5.4.2 Application with Microstrip Interconnect Tree Modeled

by RLC-Network
For the verification of the developed modeling method, the routine algorithm was
implemented into MATLAB program and the results were compared with realistic
EM and circuit co-simulations with one of the standard commercial tools. Examples
of high-speed interconnect RLC T-tree networks with different levels were analyzed
in this section. The application results proposed were designed and simulated in the
SPICE and 3D EDMS environments run with electronic microwave simulators ADS
software from Agilent™.
5.4.2.1 Proof-of-Concept Description
In this subsection, validation both in frequency and in time domains with T-tree
circuits based on the lumped RLC-networks is presented. Then, predictions of the T-
tree interconnects with levels more than tens will be made also in order to demonstrate
the relevance of the expressions developed in previous section.
As depicted in Fig. 5.12, a four-level RLC T-tree distribution network was con-
sidered. To demonstrate the feasibility of the modeling method vis-à-vis the tree
network level number, n = {3, 4, 5}-level circuits are considered. Each branch of
this RLC-tree network consists of global interconnect comprised of long wires for
deep submicron technologies proposed in [15]. As an application example, the RLC
long inter-chip interconnect with per unit length parameters Ru = 76 /cm, L u =
5.3 nH/cm and C u = 2.6 pF/cm for a physical length d = 2 mm is taken in this
section.
100 B. Ravelo
Output
Vn=4(t)
C C C C C C C C
L L
L
L
L L
L
L
R R
R
R
R R
R
R
C C C C
L
L
L
L R
R
R R
C L C L C
R R
L
R
Input
V0(t)
Fig. 5.12 Schematic of the simulated RLC-tree circuit with: R = 38 , L = 2.65 nH, C = 1.3 pF
and n = 4 [54]
For 0.25-µm CMOS technology, these interconnect parameters were established

from conductor line with 2.4-µm width [15]. Meanwhile, the equivalent lumped
parameters are equal to R = Ru × d, R = Ru × d and C = C u × d. As aforementioned
earlier, by reason of symmetry, the voltages, detected at the output terminals of the
considered tree network, are the same as the output of the equivalent SISO network
(vn (t) = vout (t)) for n = {3, 4, 5}.
As depicted in Fig. 5.13, an excellent agreement between the frequency and time
domain results was realized between the models proposed from Table 5.2 computed
in MATLAB programming environment (plotted in black dashed curve) and SPICE
simulations (plotted in full gray curve). Figures 5.13 present the frequency responses
of the RLC-tree networks shown in Fig. 5.12 from DC to 14 GHz. As can be seen
here the attenuations and phase values of the isochrone transmittances:
Hn (jω) = Vn (jω)/V0 (jω), (5.68)
are obviously more important when n is greater.
To carry out the time domain analysis, the understudy RLC-tree networks were
excited by a periodical trapezoidal transient source with normalized amplitude, V max
= 1 V, pulse width, T w = 0.5 ns, rise/fall time t r = 25 ps and having a time duration, T
= 4T w = 2 ns. As illustrated in Fig. 5.14, the calculated responses with the proposed
model plotted in full gray lines coincide very well with SPICE transient responses
Fig. 5.13 Comparisons of (a)10

ADS and the proposed model
frequency results of identical ADS
dB(Vout/Vin)
0 n= Model
lumped RC-tree network for 3
n = {3, 4, 5}: a magnitude
n=
-10
4
and b phase responses [54] n=
5
-20
-30
0.0 3.5 7.0 10.5 14.0
Frequency (GHz)
(b)
Phase(Vout/Vin) (deg)
0
n=3
-360 n=
4
ADS
n=
Model 5
-720
0.0 3.5 7.0 10.5 14.0
Frequency (GHz)
plotted in dotted black lines. As predicted intuitively in theory, one observes that the
output tree networks, vn , are more and more degraded when n is higher.
These results confirm the exactitude of the established transfer function and the
effectiveness of the proposed method for the SI analysis. Compared to the method
introduced in [29, 52], the introduced global transfer function presents technical
benefits in terms of precision and its flexibility for the high-level tree networks. So, it
can be used by the microelectronic circuit designers notably for the fast and accurate
estimation of the distortions caused by the tree network whatever its level number.
By using expression (5.57), the tree network voltage attenuations α n = vn (T )/v0
were evaluated. To check the accuracy of this formula, comparison of SPICE com-
putation is also made in Table 5.4. So, the analytical results present relative errors
lower than 5% and fit very well to SPICE computation.
Fig. 5.14 Comparisons of 1.5

v3 Input
ADS and the proposed
model time domain results of 1.0 Vout_ADS
Voltage (V)
lumped RLC-tree network v4 Vout_model

for 2-Gbits/s rate input 0.5
v5
trapezoidal voltage
0.0
excitation for n = {3, 4, 5}
[54]
-0.5
0.0 0.5 1.0 1.5 2.0
Time (ns)
102 B. Ravelo
Table 5.4 Comparison of

α n = vn (T )/V max
multi-level interconnect
attenuations from SPICE n SPICE Proposed model
computations and the 3 0.994 0.996
proposed model
4 0.951 0.903
5 0.660 0.652
5.4.2.4 A Large Number of Cell Tree Analyses
In order to evidence the operability of the proposed modeling method for very high
values of tree level, n (more than 10), quantitative time-dependent analysis of the
variations of the attenuation generated by the tree network was performed. The
MATLAB implementation of the transfer function coefficients expressed in recursive
relations (5.61)–(5.67) established earlier in Sect. 5.3.2, one can evaluate easily the
temporal response parameters for very high value of n. The value of attenuation α n
in function of the number of tree level n was calculated. This enables to investigate
the influence of n, for example, when its value is widely higher than 5. To do so, by
using expression (5.67), the plot of α n (T ) versus n displayed in Fig. 5.15 is realized.
With these examples, it can be pointed out that when the RLC-level number n is
higher than 20, the output level is strongly attenuated and less than 1% of the input
amplitude. For T = 0.5 ns and n higher than 40, the output voltages are completely
negligible compared to the input one. Otherwise, it is noteworthy that this calculation
was made over the computation in order of some ms. Compared to previous studies
[28, 52], the proposed method enables to estimate the attenuations and delays in
function of level numbers which can be in order of hundreds.
Fig. 5.15 Attenuation α n =

vn /V max versus number of 1
RLC-tree level, n for T = 0.8
max
0.5 ns [54]
0.6
V (T)/V
0.4
n
0.2
0
0 10 20 30 40
Tree level, n
5.5 Conclusion of This Chapter
An innovative methodology of global behavioral modeling of the symmetrical T-tree

distribution networks constituted by lumped element L-cell four-terminal circuits is
successfully presented. The mathematical ways enabling the simplifications of the
typical SIMO T-tree circuit into its equivalent SISO circuit are investigated. Here,
described modeling method is purely based on the direct analytical calculation based
on the mathematical operations of L-cell transfer matrices in cascade. Formulations of
the voltage transfer functions and the input impedances of multi-level T-tree networks
in function of the tree level are established and simplified for the case of linear circuits.
These exact expressions representing the behavioral voltage transfer functions and
input impedances are implemented into MATLAB.
More importantly, regarding the typical RLC T-tree networks, the mathematical
recursive expressions for the determination of the considered tree characteristic equa-
tion coefficients are also established. From where, the possibility to evaluate the SI
parameters of the T-tree network as attenuation, undershoot/overshoot and propaga-
tion delays according to the existing well-known models was evidenced. Compared
to the modeling methods published in [29, 53] which are based on the moment cal-
culation of linear transfer function, the proposed method is more efficient in terms
of precision and computation time consuming, in particular, if the tree level is higher
(more than three). Moreover, by using 3D EM and SPICE schematic co-simulations
run with the commercial ADS software, a very good agreement between the simu-
lations and the proposed behavioral models is observed. The obtained results reveal
the effectiveness of the developed circuit theoretic analysis which is aimed at the
global n-level symmetrical RLC-tree network transfer function. Thus, it was demon-
strated also that the established model permits an easy and more accurate estimation
of signal distortions and losses caused by the clock tree distribution network.
Further investigation for more concrete application environment is in progress
owing to the clock tree networks comprised of distributed elements. In the future, the
tree network model can be exploited for the improvement of the clock tree distribution
network performance and also to predict the interconnects undesirable influence in
the integrated system like SiP, PiP/PoP, MCM and SoC. Finally, I plan also to correct
the signal degradation through the high-speed tree network by using the negative
group delay circuit.
104 B. Ravelo
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Chapter 6
Symmetric Tree Interconnects Modeling
with Elementary Distributed RC-Line
Blaise Ravelo
6.1 Introduction
Over the last five decades, the semiconductor technology progress manifests with
the growth of analog and digital circuit integration density and also the increase
of operating data speed. However, research works state that this development is
accompanied by braking effects due to the signaling path complexity induced by
interconnections as buses and wire interconnection systems [1–9]. For this reason,
currently, interconnect modeling plays an important role during the design process of
high-speed integrated systems. In fact, the interconnections can degrade considerably
the SI and generate frequently, the undesirable noise, clock jitter, and clock skew
phenomena [10]. In numerical area, the latter can become sources of erroneous or
inter-symbol interferences.
In order to equalize these interconnect effects, integration of buffer circuits has
been adopted by most of industrial microelectronic companies [11, 12]. But, such
solution seems limited to certain levels of attenuated and distorted signals which
should be higher than the employed buffer threshold. For this reason, another tech-
nique based on the use of NGD circuit was introduced recently [13–16]. As reported
in [16], this equalization process depends on the use of circuits exhibiting the NGD
phenomenon in wide baseband frequency range.
As introduced in [17–20], the interconnection effects can modify and can distort
considerably the signal quality propagating through wired and wireless RF devices
with physical length more than 1/10-wavelength. To control the interconnect effects,
an accurate simulator tool enabling to analyze the complete signal path, including
drivers and receivers, in both frequency- and time-domains is necessary [21–24].
For that, the design engineers use simplified models as the popular models proposed
by Elmore [25–27] and Wyatt [28]. This prominent first-order model is typically
B. Ravelo (B)

108 B. Ravelo
less execution time consuming. In fact, these models are generally well-suited to
the lumped RC-networks and susceptible to present significant inaccuracies at GHz
frequency range [29–34]. So, lumped second-order models including the inductance
effect have been deeply deployed since the late 1990s [35–39].
Recently, there was a great interest about the design of global H-tree clock dis-
tribution networks for the optimization of clock signal quality [5, 6, 40]. Though
all these results, most of studies conducted about the clock tree distribution network
focus generally, on its impact to the technology scaling. Nevertheless, few works
were made about the analytical global modeling of the high-level tree networks.
To deal with this limitation, a modeling method of symmetrical H-tree networks
composed of distributed interconnects is developed in the proposed chapter.
6.2 Modeling Approach
Recently, there was a great interest about the design of global H-tree clock distribution
networks for the optimization of clock signal quality [5, 6, 40]. Though all these
results, most of studies conducted about the clock tree distribution network focus
generally, on its impact to the technology scaling. Nevertheless, few works were
made about the analytical global modeling of the high-level tree networks. To deal
with this limitation, a modeling method of symmetrical H-tree networks composed
of distributed interconnects is developed in the proposed chapter.
6.2.1 Topological Description
To achieve more explicit analytical approach about the H-tree modeling method
proposed, let us consider the network shown in Fig. 6.1. For the better understanding,
the pieces of TL constituting the H-tree are supposed modeled by distributed RC-line
with parameters:
Rt = R · d x, (6.1)
and
Ct = C · d x, (6.2)
and dx is the infinitesimal physical length. The parameters R and C are, respectively,
the TL per-unit length resistance and capacitance. It is well-known that:

R
Z c (s) = , (6.3)
C ·s
6 Symmetric Tree Interconnects Modeling with Elementary … 109
output
(R,C,d)
(R,C,d) (R,C,d)
N2
(R ,C,d)
(R ,C,d) (R,C,d)
N 3(R ,C,d) v(N 4)=v n
vi
N4
N 0 (R ,C,d)
N1
input
(R ,C,d)
(R ,C,d) (R ,C,d)
(R ,C,d)
(R ,C,d) (R ,C,d)
(R ,C,d)
Fig. 6.1 Example of SIMO circuit: H-tree network composed of RC distributed TL for n = 4 [44]
and d expresses, respectively, the characteristic impedance and the TL physical

length. In this case, the TL propagation constant is expressed by:
√
γ (s) = R · C · s. (6.4)
6.2.2 SIMO-SISO Transform
We demonstrate that the electrical path N 0 N 4 of the typically single input multiple
output (SIMO) circuit displayed in Fig. 6.1 is equivalent to the single input single
output (SISO) circuit depicted in Fig. 6.2. This latter enables us to establish simple
expressions of the tree understudy voltage transfer function.
110 B. Ravelo
N0 N1 N2 N3 N4
vi (R,C,d) (R/2,2C,d) (R/4,4C,d) (R/8,8C,d) vo=v(N4)
Fig. 6.2 Equivalent SISO circuit of the network shown in Fig. 6.1 [44]
6.2.3 VTF Modeling
For any values of TL parameters, we established mathematically that the transfer

functions of H-trees with levels n = {2, …, 7} summarized in Table 6.1.
By applying the second-order MacLaurin series expansion to the overall voltage
transfer function with respect to the Laplace variable s, one derives the following
second-order polynomial expression:
1
Hn (s) = . (6.5)
1 + a1 (n)s + a2 (n)s 2
By denoting:
τ = R · C · d 2, (6.6)
the iterative relations between real coefficients ak (n) and the intermediary coefficient
bk (n) for k = {1, 2} are obtained. We can consider the initial values of the transfer
function coefficients:
a1 (1) = τ/2, (6.7)
Table 6.1 Transfer functions

of distributed tree networks
formed by pieces of 2 H2 (s) = 1
3 cos h 2 (γ d)−2
(Z,d)-TLs for n = {2, …, 7} 3 H3 (s) = 1
cos h(γ d)[9 cos h 2 (γ d)−8]
4 H4 (s) = 1
27 cos h 4 (γ d)−30 cos h 2 (γ d)+4
5 H5 (s) = 1
cos h(γ d)[81 cos h 4 (γ d)−108 cos h 2 (γ d)+28]
6 H6 (s) = 1
243 cos h 6 (γ d) − 378 cos h 4 (γ d)

+144 cos h 2 (γ d) − 8
7 H7 (s) = ⎧ ⎡
1
⎤
⎨ 729 cos h 6 (γ d) − 1296 cos h 4 (γ d)
cos h(γ d)⎣ ⎦
⎩
+648 cos h 2 (γ d) − 80
a2 (1) = τ 2 /24, (6.8)
√
b1 (1) = τ, (6.9)
b2 (1) = τ 1.5 /6. (6.10)
It yields the iterative relations expressed as:

√
a1 (n + 1) = τ/2 + a1 (n) + 2 τ b1 (n), (6.11)
τ2 τ τ 1.5 √
a2 (n + 1) = + a1 (n) + a2 (n) + b1 (n) + 2 τ b2 (n), (6.12)
24 2 3
√
b1 (n + 1) = τ + 2b1 (n), (6.13)
b2 (n + 1) = τ 1.5 /6 + τ 0.5 a1 (n) + τ · b1 (n) + 2b2 (n). (6.14)
It was established previously that the second order expanding allows the determi-
nations of the two lowest degree characteristic-equation coefficients. So, the expres-
sion of the signal attenuation can be estimated. By denoting vn the n-level tree network
output voltage according to the input vin , the unit step response voltage attenuation
at the instant t = T can be expressed as follows:

vn (T ) T
αn = = 1 − exp − . (6.15)
vi (T ) a1 (n)
6.3.1 POC Description
To verify the feasibility of the method developed by considering the models of transfer
functions based on the RLC-networks, H-tree IUT was considered with n = 3 levels.
Figure 6.3 represents the layout diagram of the IUT understudy, comprised of three
levels of microstrip line with geometrical parameters width w = 0.1 µm and length
d = 3 mm.
The IUT considered in this section is printed on the dielectric substrate having
permittivity εr = 4.4 and thickness h = 1.6 mm. The metallization is based on
the conductor Cu-material with thickness t = 35 µm. We underline that design
and simulations of structures presented in this section were made in Schematic and
Momentum environments of ADS software from Agilent™. By applying the RLCG
112 B. Ravelo
Fig. 6.3 Design of the three level H-tree interconnect under test (size: 8.0 × 7.1 mm) [44]
modeling technique developed in [41–43], the per-unit-length RLC-parameters of

each interconnect single line constituting the interconnect under test are Ru = 74.6 ,
L u = 9 nH, and C u = 35 pF. By using these parameters, the formulation of the global
reduced model established considered in Sect. 6.3 was applied by supposing that
the IUT is loaded by parallel RC-network Z L = RL //C L . During the simulations,
the capacitance C L was fixed to 2 pF, and the resistance RL was varied from 100 to
300 .
6.3.2 Frequency Domain Results
Figure 6.4 displays the voltage transfer function frequency responses generated from
the 3D EMDS environment of ADS and the model established from DC to 6 GHz.
Fig. 6.4 Comparisons of the R L =100 R L =200 R L =300

frequency responses of 10 200
Phase(V out /V in ) (deg)
interconnect T-tree shown in

|V out/Vin | (dB)
ADS
Fig. 6.3 simulated with ADS -10 Model 100
and from the model proposed
[44] -30 0
-50 -100
-70 -200
0 1 2 3 4 5 6
Frequency (GHz)
Fig. 6.5 Comparisons of the R L =100 R L =200 R L =300

time-domain responses of 2V m
ADS
interconnect T-tree shown in Input Model
Voltage (V)
Fig. 6.3 simulated with ADS Vm
and from the model proposed
[44]
0
-Vm
0 1 2 3 4
Time (ns)
We can see that good correlations were realized both for n = 3 levels for dif-
ferent values of the resistance load. Resonance effect can be forecasted at about
1.35 GHz. Furthermore, this resonance effect is more and more accentuated when
RL is increased.
6.3.3 Time-Domain Analysis
More illustrating representation of the validity of the behavioral analytical model

developed was also carried out by using high rate numerical data. For that, the
time-domain response of the T-tree IUT was generated by considering an arbitrary
binary 8 bits sequence “01001100” with rate 2 Gsymbols/s presenting a rise time
of about 50 ps. The amplitude of the operating data was normalized (V m = 1 V).
Figure 6.5 displays the comparative results from 3D EMDS and SPICE-schematic
co-simulations and the behavioral models established for n = 3.
We can state that very good correlations were found. We can point out that a
significant degradation of the operating data is found due to the T-trees. Moreover,
the distortion increases with the value of the load resistance RL . An overshoot voltage
more than 70% of the operating signal amplitude is generated by the IUTs.
It is interesting to note that the PC used during the simulations of the structure pre-
sented in Fig. 6.3 is equipped a single-core processor XEON 3.4 GHz and 4 GB phys-
ical memory with 32-bits Windows XP. The computation time with the co-simulation
with EDMS and SPICE schematic environments was more than five of minute against
tens seconds by using the routine algorithm summarizing the method implemented
in MATLAB. The computation time with the method proposed is hundreds less than
those carried out with the commercial tools [21–24].
114 B. Ravelo
A modeling method of clock H-tree comprised of distributed interconnect lines is suc-

cessfully investigated. It was explained that the SIMO H-tree circuit can be reduced
to an equivalent SISO system. Then, global transfer function of the overall tree net-
work is established from the transfer matrix exploitation [40]. To check the relevance
of the proposed model, examples of literal expressions of tree network function are
presented. Furthermore, an analytical method allowing to estimate the simple and
accurate formula of voltage attenuation was also proposed. This permits also to pre-
dict the voltage attenuation versus the parameters of the tree network. To verify the
effectiveness of the theoretic concepts introduced, application examples based on the
use case of distributed RC-tree network were numerically experimented. As conse-
quence, results in excellent agreement with SPICE simulations were obtained both
in frequency- and time-domains. Compared to SPICE, the modeling method devel-
oped consumes very less execution time. As expected in theory, it was shown that
by taking a tree network constituted by TLs having submillimeter physical length,
the output signal was strongly attenuated when the tree level number is higher.
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Chapter 7
Z/Y/T/S-Matrices’ Modelling
of Symmetric SIMO Structure Based
on Elementary Distributed RLC-Cell
7.1 Introduction
Over the five last decades, the semiconductor technology advance is based on the
growth of analogical and digital circuit integration density and also the increase
of operating data speed. However, research works state that this development is
accompanied by negative effects due to the signalling path complexity such as bus and
wire interconnection systems [1–9]. For this reason, interconnect modelling plays an
important role during the design process of high-speed integrated systems. Indeed,
the interconnections can degrade considerably the SI and generate frequently, the
undesirable noise, clock jitter and clock skew phenomena [10, 11]. In numerical area,
the latter can become drastically sources of erroneous or inter-symbol interferences.
In order to equalize these interconnect effects, technical solutions based on the
use of buffers have been proposed since [12–14]. But, such solution seems limited
to certain levels of attenuated and distorted signals which should be higher than the
employed buffer threshold. For this reason, another technique based on the use of
negative group delay circuit was introduced recently [15–18]. As reported in [18],
this equalization process depends on the use of circuits exhibiting the negative group
delay phenomenon in wide baseband frequency range.
According to ITRS report [19], for most of modern high-speed RF/digital hard-
ware systems, the interconnect delays dominate widely the logic gate delays. As
introduced in [20–22], the interconnection effects can modify and distort consid-
erably the signal quality propagating through wired and wireless RF devices with
physical length more than 1/10-wavelength. In digital IC operating at multi-gigabits
per second data rate, the interconnection impact presents a significant key factor for
the signal- and power- integrities [10, 11, 23–26]. To control the interconnect effects,
an accurate simulator tool enabling to analyse the complete signal path, including
T. Eudes · B. Ravelo (B)


drivers and receivers, in both frequency- and time-domains is necessary [27–30].

Till now, few solvers allow simulating correctly the integrated system containing
about thousands logic gates. For that, the design engineers use simplified models as
the popular models proposed by Elmore [31–33] and Wyatt [34] which are typically
less execution time consuming. In fact, these models are generally well-suited to the
lumped RC-networks [35–41]. So, lumped second-order models have been deeply
deployed since the late 1990s [41–46].
Nonetheless, further enhancements seem to be necessary for structures that are
more complicated as clock tree distribution topologies investigated in [41, 47–56].
Nowadays, intensive research works are conducted on this topic for electronic- [47,
48, 50] and optical- [49] submicron systems. Recently, there was a great interest
about the design of global H-tree clock distribution networks for the optimization of
clock signal quality [47, 48, 56]. Therefore, different algorithms for the modelling of
the influences of tree network parameter variations were also provided [52–54]. For
example, an H-Tree topology of Networks-on-Chips for Reconfigurable Processor
Array was also proposed for the reduction of the cross-point number of processor grid
structures [51]. It can be underlined that most of studies conducted about the clock
tree distribution network focus generally, on its impact to the technology scaling.
Nevertheless, few works were made about the analytical global modelling of the high-
level tree networks. To deal with this limitation, a modelling method of symmetrical
H-tree networks composed of distributed interconnect conductors including source
and terminal impedances is proposed in the present chapter. The originality of the
chapter lies on the simplicity and the accuracy of the mathematical global model of
tree networks in function of the line per-unit length parameters [57, 58] and the tree
level. This enables to predict easily the signal integrity [58] quality according to the
targeted applications as the high-speed numerical systems [59].
For the better comprehension, this chapter is articulated as follows. First, based
on the analysis of TL transfer matrices, a theory of clock H-tree distributed network
shown in Fig. 7.1 [60].
The equivalent transfer function of global network will be explored. Then, tree
networks composed of different and identical TLs will be examined. Section 7.2
provides the transfer function and the input impedance of the whole system by taking
into account source and terminal impedances. In order to evaluate the relevance of
this approach, a first study of a real symmetrical H-tree unbuffered distribution is
proposed by considering identical TLs with the RLCG modelling. The RLCG model
is only extracted with geometrical and electrical properties of the elementary TL
with wide-band accuracy [58]. Then, the assessment of signal integrity parameters
is established both in the frequency domain and in the time domain is made with
an example of DDR3-SDRAM (Double Data Rate Synchronous Dynamic Random
Access Memory) design [59]. Consequently, the attenuation and the time delay due
to interconnect effects are clearly exposed. Furthermore, the employment of active
NGD buffer as classical threshold buffer is also pointed out [15–18]. Finally, the
conclusion of this work is drawn in the last section.
7 Z/Y /T /S-Matrices’ Modelling of Symmetric SIMO Structure … 119
Fig. 7.1 Basic configuration Clock terminal

of symmetric network for
five levels H-clock tree
distribution [60]
Level 4 Level 4
Level 5
Level 5
Level 3
Level 3
Level 2
Level 1
Level 5
Level 5
Level 4 Level 4
Clock source
7.2 Modelling of Symmetric H-Tree Signal Distribution
For starting, let us consider the TL having a characteristic impedance Z c and physical
length d as shown in Fig. 7.2. In the remainder of this chapter, this TL will be noticed
as (Z c ,d)-TL.
According to the TL theory, it is well known that the transfer matrix of this line
is written as follows:

T11 T12 cos h(γ d) Z c sin h(γ d)
[T ] = = sin h(γ d) , (7.1)
T21 T22 Zc
cos h(γ d)
where γ is the wave propagation constant. The voltage transfer function correspond-
ing to this matrix is defined as follows:
Vo (s) 1 1
H (s) = = = , (7.2)
Vi (s) T11 cos h(γ d)
Vi Zc , d Vo
Fig. 7.2 TL with Z c -characteristic impedance and d-length and with input and output voltages,
respectively, denoted vi and vo
and the associated input impedance is expressed as follows:
T11
Z in (s) = = Z c cot h(γ d). (7.3)
T21
In the next parts of this chapter, these analytical relations will be examined for
the characterization of the distributed H-tree network.
7.2.1 Modelling of Distributed Symmetric Tree Networks

Formed by Different Pieces of TLs
For the achievement of well-synchronized high-speed analogical-numerical signal,

one can consider different types of interconnection network configurations. For that,
the symmetrical H-tree network is usually utilized for numerous advantages [56].
This is why this study is focused on the modelling of H-tree network topology.
7.2.1.1 Topological Description
The understudy n-level distributed H-tree network is depicted in Fig. 7.3. Since the
distribution network is symmetrical, the signals vo delivered at the 2n -outputs do not
depend on input vi . One can see that the branch Nk Nk+1 (k = {1, . . . , n − 1}) is
constituted by a piece of distributed TL having characteristic impedance Z k+1 and
Input Output
Nn
Zn, dn
Nn-1
Z k+1, dk+1 Z n-1, dn-1 Zn, dn
Vo
Nk
Z2, d2 Zk , dk
Z k+1, dk+1 Z n-1, dn-1
Zn, dn
Nn-1
Zn, dn
Nn
N1
Vi N0
Z1, d1
Nn
Zn, dn
Nn-1
Zk+1, dk+1 Zn-1, dn-1 Zn, dn
Nk
Z 2, d2 Z k , dk
Zk+1, dk+1 Zn-1, dn-1
Zn, dn
Nn-1
Zn, dn
Nn
Fig. 7.3 H-tree network with n-level symmetrical branches formed by distributed piece of lines
having Z k characteristic impedance (k = {1, …, n}) and d k length [60]
physical length d k+1 . By reason of symmetry, the equivalent input impedance seen in
the plan placed at the nodes N k (k = {1, …, n − 1}) is the half of the single branch
input impedance. This implies the equivalence of two (Z n , d)-TLs in parallel as a
single (2−1 Z n , d)-TL.
7.2.1.2 T-Matrix Modelling with SIMO-SISO Transform
By applying this operation successively, one derives the simplified circuit equivalent
to any branch of Fig. 7.3 represented by the cascaded distributed circuit shown in
Fig. 7.4.
In this case, each piece of TL between the nodes N k −1 and N k (k = {1, …, n})
should present characteristic impedance equal to:
Z eq = 21−k Z k , (7.4)
and a transfer matrix given by:

cos h(γ dk ) 21−k Z k sin h(γ dk )
TNk−1 Nk = sin h(γ dk ) . (7.5)
21−k Z k
cos h(γ dk )
For the sake of simplification, one denotes [T (k)] the overall transfer matrix
associated to k-pieces of (21−k Z k ,d)-TLs in cascade:

k
T11 (k) T12 (k)
[T (k)] = TN p−1 N p = , (7.6)
T21 (k) T22 (k)
p=1
with:

cos h(γ d1 ) Z 1 sin h(γ d1 )
[T (1)] = TN0 N1 = sin h(γ d1 ) . (7.7)
Z1
cos h(γ d1 )
By identification, the elements of this initial matrix are expressed as follows:
T11 (1) = T22 (1) = cos h(γ d1 ), (7.8)
N0 N1 Nk Nn-1 Nn
Vi 2 0Z1, d1 2 -1Z2, d2 21-k Zk , dk 2-k Zk+1 , dk+1 22-nZn-1, dn-1 21-nZn, dn Vo
Fig. 7.4 Equivalent circuit of any branch of the distributed network [60]
T12 (1) = Z 1 sin h(γ d1 ), (7.9)
sin h(γ d1 )
T21 (1) = . (7.10)
Z1
Thus, one can determine iteratively the other transfer matrix via the following
matrix product:

[T (k + 1)] = [T (k)] × TNk−1 Nk . (7.11)
It yields the [T (k + 1)]-elements expressed as follows:
2k−1 T12 (k) sin h(γ dk )

T11 (k + 1) = T11 (k) cos h(γ dk ) + . (7.12)
Zk
T12 (k + 1) = 21−k Z k T11 (k) sin h(γ dk ) + T12 (k) cos h(γ dk ). (7.13)

T21 (k + 1) = T21 (k) cos h(γ dk ) + . (7.14)
Zk
T22 (k + 1) = 21−k Z k T21 (k) sin h(γ dk ) + T22 (k) cos h(γ dk ). (7.15)
7.2.1.3 VTF Modelling
According to the definition of the transfer function introduced in (7.3), one derives
from [T (k + 1)], the recursive relation permitting to determine the voltage transfer
function, H k+1 (s) in function of H k (s) expressed as follows:
⎧
⎨ cos h(γ
1
d1 )
, if k = 0
Hk+1 (s) = 1
, if k ≥ 1 . (7.16)
⎩ H (k) cos h(γ dk )+
Zk
In addition, based on formula (7.4), input impedance Z in,k (s) of k-level symmet-
rical tree networks presented in Fig. 7.2 is written as follows:
T11 (k)
Z in,k (s) = . (7.17)
T21 (k)
So, the input impedance associated to last stage transfer matrix [TNn−1 Nn ] is given
by:
Z T (s) = 21−n Z n (s) cot h(γ dn ). (7.18)

Nn−1 Nn
7.2.2 Modelling of Distributed Tree Networks with Identical

Elements
This subsection presents the analysis of particular case of H-tree network investigated
in the previous one by taking Z k = Z and d k = d for k belongs in {1, …, n}.
7.2.2.1 T-Matrix of n-Level H-Tree Networks
So, the transfer matrix of k-level tree networks schematized in Fig. 7.2 can be
expressed as follows:

Z ·t12 (k)
t11 (k)
[T (k)] = 2k−1 t21 (k)
2k−1 , (7.19)
Z
t22 (k)
with:
t11 (1) = t22 (1) = cos h(γ d), (7.20)
and:
t12 (1) = t21 (1) = sin h(γ d). (7.21)
By replacing k by (k + 1), one gets the (k + 1)-level tree transfer matrix given
by:

Z ·t12 (k+1)
t11 (k + 1)
[T (k + 1)] = 2k t21 (k+1)
2k . (7.22)
Z
t22 (k + 1)
Knowing that [T (k)] and [T (k + 1)] are linked by the recursive matrix multipli-
cation:
[T (k + 1)] = [T (k)] × [T (1)], (7.23)
one establishes, thus the following expressions which enable to relate t ij (k + 1)-
coefficients in function of t ij (k)-coefficients with i, j = {1, 2}:
t11 (k + 1) = t11 (k) cos h(γ d) + 2t12 (k) sin h(γ d), (7.24)
t12 (k + 1) = t11 (k) sin h(γ d) + 2t12 (k) cos h(γ d), (7.25)
1
t21 (k + 1) = t21 (k) cos h(γ d) + t22 (k) sin h(γ d), (7.26)
2
1
t22 (k + 1) = t21 (k) sin h(γ d) + t22 (k) cos h(γ d). (7.27)
2
7.2.2.2 VTF Extraction of n-Level H-Tree Networks
It yields the corresponding transfer function, H k+1 (s) associated to [T (k + 1)] written
as follows:
1
Hk+1 (s) = . (7.28)
t11 (k) cos h(γ d) + 2t12 (k) sin h(γ d)
Moreover, the input impedance Z in (k + 1) of k-levels tree networks expressed in

(7.17) will be transformed as follows:
T11 (k + 1) Z t11 (k) cos h(γ d) + 2t12 (k) sin h(γ d)

Z in (k + 1) = = k−1 . . (7.29)
T21 (k + 1) 2 t21 (k) cos h(γ d) + 2t22 (k) sin h(γ d)
7.2.3 Modelling of n-Level H-Tree Networks with Source

and Terminal Impedances
To get more realistic effect on the proposed structure, source Z S and terminal Z L clock
impedances are taking into account, this provides the schematic sketched in Fig. 7.5
of the whole considered system. As explained previously, a n-level symmetrical H-
tree network has balanced 21−n outputs. As a result, any path of the tree can be
represented by an equivalent interconnect line with its own transfer matrix [T (n)].
Equivalent
Source interconnect line Load
ZS
Vi Zc, , d ZL Vo
Fig. 7.5 Whole system under study includes clock source and clock terminal impedances
7.2.3.1 T-Matrix Modelling
At present time, the overall transfer matrix [T T ] is given by the following relation:
[TT ] = [TS ] × [T (n)] × [TL ], (7.30)
where [T S ] and [T L ] are, respectively, the source and terminal impedance matrices
having subsequent expressions:

1 ZS
[TS ] = , (7.31)
01

1 0
[TL ] = 1 . (7.32)
ZL
1
For the sake of the mathematical simplification, one can assume that all terminal
impedances are similar to the same impedance denoted Z T . Thus, this implies that
the equivalent terminal impedance Z L is equal to:
ZT
Z Teq = , (7.33)
n out
where nout is the number of outputs, as it happens for a n-level H-tree:
Z L = 21−n Z T . (7.34)
Consequently, the whole transfer function and input impedance are obtained by
equations:
T12 (n) ZS
TT11 (n) = T11 (n) + Z S × T21 (n) + + T22 (n), (7.35)
ZL ZL
T22 (n)
TT21 (n) = T21 (n) + . (7.36)
ZL
We can recall that in the general case, the equivalent VTF between input and output
and the input impedance of the structure introduced in Fig. 7.2 can be, respectively,
written as follows:
1
HT (n) = , (7.37)
TT11 (n)
Table 7.1 Transfer functions and input impedances of distributed H-tree networks formed by pieces
of (Z c , d)-TLs for n = {2, 3}
n Transfer function and input impedance from T T11 and T T21
⎧ ⎫
2 ⎪ ZS
⎪
⎨ 3 cos h 2
(δd) × 1 + + 3 cos h(δd) · sin h(δd)⎪
⎪
⎬
2Z L
TT11 (2) =
⎪
⎪ ZS Zc ZS ⎪
⎪
⎩× + − −2 ⎭
Zc 2Z L 2Z L
TT21 (2) = 3
cos h 2 (δd) + Z3c cos h(δd) sin h(δd) − 2Z1 L
2Z L

3 ZS ZS Zc
TT11 (3) = 9 cos h 3 (γ d) × 1 + + cos h 2 (γ d) · sin h(γ d) × +
4Z L Zc 4Z L

5Z S 2Z S Zc
− cos h(γ d) × 8 + − sin h(γ d) × +
4Z L Zc 2Z L
9 cos h 3 (γ d)−5 cos h(γ d)
TT21 (3) = Z4c sin h(γ d) × 49 cos h 2 (γ d) − 21 + 4Z L
TT11 (n)
Z in (n) = . (7.38)
TT21 (n)
7.2.3.3 VTF Model of Two- and Three-Level Tree Network
By using this expression and iterative relations (7.24)–(7.27) and overall transfer
matrix relations (7.30), (7.35) and (7.36), the analytical result examples of transfer
function and input impedance formulations are summarized in Table 7.1. These
relations correspond to the tree network as shown in Fig. 7.3 for n = {2; 3}. It is
worthy of note that the transfer functions and input impedances calculated depend on
the TL propagation constant γ and the physical length d. Moreover, one can easily
assume that polynomial approximation methods of transfer functions are difficult
to implement. Therefore, analytical models ensure sufficient accuracy and allow
including coupling effects through the RLCG model.
To get more insight the proposed equations, an example of application is studied. One
assumes that the H-tree is symmetrical and has identical pieces of (Z c , d)-TLs. Thus,
the extraction of the frequency-dependent parameters γ and Z c will be straight-
forwardly obtained from geometrical and electrical properties of the elementary
TL.
Table 7.2 Geometrical

Geometrical parameters
parameters for the six-layer
PCB design of Substrate Height Width Thickness
DDR3-SDRAM standard Epoxy (εr = h = 127 µm w = 250 µm t = 30 µm
4.4)
Table 7.3 Electrical

Frequency and time parameters
parameters of the DDR3
PC3-17000 version Frequency Period Rise and fall times Bandwidth
1066 MHz 938 ps 45 ps 7.777 GHz
7.3.1 Application with Two- and Three-Level Microstrip Tree
The symmetric tree modelling concept is related to the RLCG model of TLs, so
it is proposed to use a wide-band model which includes frequency dispersion and
frequency loss effects according to [58]. Since this model is frequency dependent, it
yields that the application limits the considered bandwidth of characterization BW3 dB
defined (2.33). It depends on the rise time t r which is provided by the application
requirements.
7.3.1.1 Example of DDR3-SDRAM Requirements
The more relevant about high-speed clock distribution on PCBs is the RAM clocking
for dual inline memory module (DIMM), in particular with the DDR3-SDRAM
standard. As mentioned in [59], the DDR3 PC3-17000 version with a six-layer PCB
layout has the geometrical parameters are summarized in Table 7.2, whereas electrical
parameters are reported in Table 7.3. So, the equivalent impedance at 1066 MHz of
a piece of TL is about 46 . In addition, one assumes that value of clock source is
a pure 50 resistor, while terminal impedances are considered as a parallel 60
resistor with one 4-pF capacitor.
7.3.1.2 Extraction of the Distributed RLCG Model for the Elementary

Interconnect Line
Let us consider the elementary interconnect line of the symmetrical H-tree network
represented by its distributed RLCG model as depicted in Fig. 7.6. It is notewor-
thy that Ru , L u , C u and Gu are, respectively, per-unit length resistor, inductance,
capacitance and conductance of the interconnect line.
Elementary Distributed RLCG Model

interconnect line
Ru Lu Ru Lu
Zc, , d Gu Cu Gu Cu
du
Fig. 7.6 Considered RLCG model of the elementary interconnect line
It is well known that the characteristic impedance Z c and the propagation constant
γ of the distributed interconnect line in function of the frequency are shown. In the
remainder of this chapter, the equivalent lumped parameters of the RLCG-line are
denoted by R = Ru × d, L = L u × d, G = G u × d, C = Cu × d. It is worthy of note
that these RLCG parameters can be extracted with mathematical operations yielded
from Chap. 2. As a result, the lumped element R, L, C and G depends on the frequency.
When Z c (s) and γ (s) functions are obtained, two symmetrical H-trees, respectively,
with two-levels and three-levels, were designed within the EMDS environment of
the standard ADS microwave/electronic simulation tool from Agilent™ as shown in
Fig. 7.7. So, the RLCG model in function of the frequency was implemented within
the ADS environment in order to perform co-simulation analyses with the pure
theoretical microstrip design of ADS. The signal integrity assessment is articulated
in two steps, first simulations were run in the frequency domain from DC to 8 GHz.
Then, the time-domain response was analysed with a PC3/17000 clock signal which
meets the requirements introduced in Table 7.3.
Clock terminal
Clock source
Clock terminal
Fig. 7.7 PCB Design of the 3-level symmetrical H-tree for high-speed clock distribution [60]
(a) -6
ADS
Transfer Function (dB)

Model
-8
-10
-12
-14
-16
0 1 2 3 4 5 6 7 8
Frequency (GHz)
(b) -10
ADS
Transfer Function (dB)
Model
-15
-20
-25
-30
0 1 2 3 4 5 6 7 8
Frequency (GHz)
Fig. 7.8 a Frequency results for the two-level symmetrical H-tree [60]. b Frequency results for the
3-level symmetrical H-tree [60]
Frequency Domain Results
It is important to mention that the ADS simulation does not include dispersion mod-
els, unlike the EM ADS-Momentum tool which is a full-wave simulation. Despite
this statement, one can assume that proximity effects can distort the results, which
are not the topic of this study. For this reason, simulations with the ADS SPICE
standard were only performed in order to show the importance of the high-frequency
part.
It is worthy of note that frequency dispersion and dielectric loss effects are more
heightened for the three-level H-tree than the two-levels as shown by Fig. 7.8a, b.
A perfect correlation between ADS simulation and the proposed model for the two-
level H-tree network up to 4 GHz is made, then after dispersion and dielectric loss
affect the transfer gain of less than 0.2 dB. Due to the more important length of the
Table 7.4 Injected rise times and their equivalent bandwidths

Rise time/bandwidth relation
Rise times t r1 (ps) t r2 (ps) t r3 (ps) t r4 (ps)
45 90 180 260
Equivalent bandwidth BW1 (GHz) BW2 (GHz) BW3 (GHz) BW4 (GHz)
7.77 3.88 1.94 0.97
three-level H-tree network, these effects involve up to 3 dB of variation between the

ADS simulation and the model.
Time Domain Results
In order to focus on the impact of frequency dispersion and dielectric effect for SI
parameters, notably attenuation and time delay, different rise times were performed
as indicated by Table 7.4. So, accordingly while the frequency bandwidth is changing
with the rise time (7.36), here it yields that SI parameters of the three-level H-tree
will be changed. In this case, more the frequency bandwidth increases, the more
differences increase.
As provided by Figs. 7.9a and 7.10a, since ADS simulation and the proposed
model have very good correlation, the time-domain responses are also well correlated.
As expected, significant differences between the model and the ADS simulation for
the three-level H-tree network were found, as sketched in Figs. 7.9b and 7.10b. The
time delay is affected by 50 ps more with frequency dispersion and dielectric loss
effects for t r1 , whereas it is only affected by 20 ps for t r4 . In addition, overshoot and
undershoot effects seem to be more important for high rise times.
A modelling method of symmetrical clock H-tree network comprised of distributed

interconnect lines is introduced. It was explained that the tree network can be reduced
to a SISO system. Then, global transfer function of the overall tree network is
established.
Based on the application of four-port circuit theories to the distributed line cas-
caded, the analytical expressions of tree network transfer functions and its input
impedances versus the tree level are extracted. In addition, overall transfer functions
and input impedances were calculated by taking into account clock source and clock
terminal impedances. To check the relevance of the proposed model, examples of
literal expressions of tree network function are presented. Furthermore, an example
of high-speed sub-millimetre PCB clock application was investigated. This permits
to illustrate the relevance of using the RLCG model including frequency dispersion
Vin
ADS
Model
(a)
Vclock
Voltage (V)
Vclock /2
0 0.4 0.8 1.2 1.6 2

Time (ns)
Vin
ADS
Model
(b)
Vclock
Voltage (V)
Vclock /2
0 0.4 0.8 1.2 1.6 2

Time (ns)
Fig. 7.9 a Time domain results for the two-level symmetrical H-tree for four different rise times
[60]. b Time domain results for the three-level symmetrical H-tree for four different rise times [60]
and dielectric loss effect that cannot be neglected for high-speed clock signals. More-
over, the RLCG model is capable to ensure crosstalk effects to improve the accuracy
of this method when dimensions become very small. As consequence, the simulation
was performed both in frequency- and time-domains to point out that the high-speed
part is responsible of SI parameters degradation. As expected in theory, it was shown
that by taking an unbuffered tree network constituted by TLs having sub-millimetre
physical length, the output signal was strongly attenuated when the tree level number
is higher.
In summary, in the present chapter, we are interested to the modelling of the
global transfer function enabling to estimate accurately and fastly, the delays and
ADS
(a) Model
Normalised Voltage (V) Vmax
0 0.4 0.8 1.2 1.6 2

Time (ns)
ADS
(b) Model
V max
Normalised Voltage (V)
0 0.4 0.8 1.2 1.6 2

Time (ns)
Fig. 7.10 a Time domain results for the two-level symmetrical H-tree with a normalized voltage
[60]. b Time domain results for the three-level symmetrical H-tree with a normalized voltage [60]
attenuations. In the continuation of the present study, the effect of the interconnect
coupling as the NEXT and FEXT will be investigated. Then, impedance variations
between the branches due to the difference in return path and in vicinity to other
traces, the different types of discontinuity will be also taken into account. This con-
cept illustrates well that classical threshold buffers will not be able to compensate
propagation effects. For this reason, NGD structures can be considered in order to
reduce the number of buffers when SI parameters became deteriorated, in particular
attenuation and time delay [15–18].
One hopes that thanks to the presented modelling method, the fidelity of analogue-
numerical signal through H-tree network in the complex integrated systems can be
predicted. In the continuation of this research work, one can envisage industrial
applications of the established model to preserve the clock SI in the high-speed
RF/digital systems.
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Chapter 8
Z/Y/T/S-Matrices’ Analysis
of Non-symmetric SIMO Tree Based
on Elementary Distributed Element
Thomas Eudes, Blaise Ravelo, Thierry Lacrevaz and Bernard Fléchet
8.1 Introduction
To meet the industrial best performance with optimal ratio of cost quality, the semi-
conductor industry innovates constantly the PCB design and implementation tech-
niques. With the rapid progress of the electronic devices, the emerging technology
with reference to the wearable and connected objects becomes a new reference [1].
To follow this trend, the flexible and organic technology is announced to be one
of the best candidates for the future electronics [2]. However, preliminary research
work is currently in progress for the further understanding on the potential of organic
flexible electronics [3]. The existing electronic products implemented on the flexible
plastic substrate are still in the maturity level corresponding to the laboratory valida-
tion [4]. Nevertheless, the prototypes of passive devices as flexible sensors printed on
polyethylene naphthalate (PEN) were recently designed and fabricated [5]. Further-
more, flexible electronics on the chapter were also proposed by using a conductive
silver ink-filled rollerball pen [6]. This approach was promised to lower the printing
technics fabrication cost. More recently, further extension has been made with the
research work on the organic light-emitting diodes and transistors [6, 7].
However, in function of the material properties and design characteristics, the SI
through the interconnect TLs notably in the high-speed systems is more and more
critical with the design complexity [8–10]. The signal delay as skew constraints and
the distortion in particular through the clock interconnection tree imperfection can-
not be neglected. Therefore, basic standards have been established [11]. Moreover,
prediction method [12, 13] usually based on the fundamental principle from the
T. Eudes · B. Ravelo · T. Lacrevaz

B. Fléchet (B)
Université de Savoie Mont-Blanc, 73376 Le Bourget du Lac Cedex, France
e-mail: bernard.flechet@univ-smb.fr
IMEP-LAHC Laboratory, Le Bourget du Lac Cedex, France

138 T. Eudes et al.
microwave theory should be taken into account during the design of the high-speed
PCB. Thanks to the design simplicity and the relevance of the analytical model, the
microstrip interconnect is one of the most popular technologies used during the PCB
design [14, 15–18]. The analytical circuit approaches for the SI analyses with such
a structure are substantially built with the TL RLC and RLCG models [19–21]. The
current trend is to extend the model with respect to the complexity of the structure
as the consideration of the geometrical shape of the interconnect structure [20]. Fur-
thermore, higher level of complexity as the use of signal sharing tree network can
be found for the PCB composed of high-density components. Various topologies of
mesh and tree signal distribution network were developed [22–25]. The H- and T-tree
topologies are used generally for the best synchronization of the signal distributed
through multi-level interconnection [24, 25]. In the other cases as for the microelec-
tronic packaging or PCB, to connect the thousands of logic gates, the interconnect
structures are naturally more sophisticated than the one-level comb tree investigated.
Meanwhile, more relevant models are still required for higher levels of asymmetrical
tree interconnect networks as depicted in Fig. 8.1 [26].
Therefore, the prediction of the SI parameters is necessary for the PCB designer.
For example based on the high-order polynomial models [25, 27], the voltage transfer
functions through the RLC-tree network are established. Then, the calculations of the
attenuation, rise/fall time, propagation delays from each branch of the tree networks
were derived. Despite this tremendous progress, the SI of the electrical interconnects
on the flexible substrate in function of the electric property as resistive ink remains
so far, an open question.
Fig. 8.1 Example of complex asymmetrical tree networks [26]

8 Z/Y /T /S-Matrices’ Analysis of Non-symmetric SIMO Tree Based … 139
For this reason, the feasibility analysis of a behavioral modeling of microstrip

interconnect tree printed on plastic substrate is developed in this chapter. To do this,
the principle of the proposed behavioral modeling of the asymmetrical T-tree by
using ABCD matrix is introduced in Sect. 8.2 [28–30]. It is based on the electrical
equivalence between the SIMO and the SISO topologies. Then, the voltage transfer
functions between the asymmetrical T-tree input and the interconnect tree outputs are
proposed. The main challenge of the work proposed herein is the consideration of the
flexible asymmetrical tree metallization conductivity effects on the SI. To highlight
the effectiveness of the model, in Sect. 8.3, a POC constituted by a single-input and
three-output asymmetrical tree will be investigated. The chapter conclusion is drawn
in Sect. 8.4.
8.2 Asymmetric 1:3 Tree Modeling
To generalize the theoretical approach, the SIMO topology of the asymmetrical

T-tree under study is assumed to be constituted by electrical network having a single
input with electrical node M in and multiple n-outputs with nodes M k (k = {1, …, n}).
The behavioral model is the analytical expression of the equivalent SISO transfer
function. This transfer function is extracted based on the circuit and system theory
developed. It enables to predict the frequency- and time-domain responses of the
asymmetrical tree for any electrical path M in M k . Then, the different steps of the
modeling process routine algorithm are described.
The topology of the asymmetrical T-tree SIMO is introduced in Fig. 8.2. The pro-
posed network is represented as a SIMO network with single input and multiple
n-outputs. It is essentially comprised of distributed input access TL denoted TLin
(with characteristic impedance Z in and physical length d in ) connected to n-output
branch TLs denoted TLk with k = {1, 2, …, n}. The tree network input access is
preceded by series impedance Z s and voltage source V in . Hence, the output elemen-
tary TLs are terminated by different lumped impedances Z k . Across this output load
impedances, we have the tree output voltages V k shared at the node M k for k = {1,
…, n}.
In the rest of the chapter, for the uniformity of the mathematical notations, one
denotes:

Ru (s) + s · L u (s)
Z ck (s) = , (8.1)
G u (s) + s · Cu (s)
140 T. Eudes et al.
Fig. 8.2 Diagram of the asymmetrical distributed interconnect tree network with source series
impedance Z s and output loads Z 1 , Z2 , and Z3 [28]

γk (s) = [Ru (s) + s · L u (s)] × [G u (s) + s · Cu (s)], (8.2)
the characteristic impedances and the propagation constants of the elementary dis-
tributed TLs TLk , respectively. The TLk physical lengths are denoted d k . It is worth
noting that the electrical lengths are denoted:
θk (s) = γk (s) · dk , (8.3)
for TLk and:
θin (s) = γin (s) · din , (8.4)
for TLin .
8.2.2 SIMO–SISO Transform T-Matrix Modeling
Similar to the theoretic approach introduced in [31], the proposed behavioral model
of the asymmetrical T-tree is fundamentally built with the ABCD matrix analyses.
Indeed, according to the circuit theory, the ABCD matrix of the whole system shown
in Fig. 8.2 could be extracted by the combination of the elementary TL characteristic
matrices and the input/output load impedances. By definition, the ABCD matrices of
TLs TLk (k = {1, 2, …, n}) are written as:

cosh(θk ) Z ck · sinh(θk )
[ABC D]TLk = sinh(θk ) , (8.5)
Zc
cosh(θk )
k
with:
θk = γk · dk (8.6)
is the electrical length of the TLk . The ABCD matrix of the asymmetrical T-tree
output load impedance is defined as:

1 0
[ABC D] Z k = 1 . (8.7)
Zk
1
Therefore, the equivalent ABCD matrices of the output branches TLk -Z k are
written as:
Z

cosh(θk ) + Zckk · sinh(θk ) Z ck · sinh(θk )
[ABC D]TLk −Z k = sinh(θk ) cosh(θk ) . (8.8)
Zc
+ Zk cosh(θk )
k
In order to reduce the SIMO circuit presented in Fig. 8.2 into single output, regard-
ing the electrical branch N in to N k , the other branches of the system can be assigned
as an equivalent input admittance. This admittance is in turn connected in parallel to
the output branch of interest TLk -Z k . By means of ABCD-to-Y-matrix conversion,
the total equivalent input admittance seen at the intermediate node expected by the
TL TLk can be established with the expression:

n
1 Z ξ · sinh θξ + Z cξ · cosh θξ
Yk,node = × . (8.9)
ξ =1
Z cξ Z cξ · sinh θξ + Z ξ · cosh θξ
ξ =k
The global ABCD matrix between the general input N in and the intermediate node
can be determined from the matrix product. It implies that the input voltage transfer
function of the asymmetrical tree seen at the intermediate node is expressed as:
Vnode (s) 1
=
. (8.10)
Vin (s) Zs
sinh(θ ) + cosh(θ )
Z in in in
+[Z in sinh(θin ) + Z s cosh(θin )]

Z sinh(θ )+Z cosh(θ )
× nk=1 Z1c · Z kc sinh(θk k )+Zckk cosh(θkk )
k k
with s is the Laplace variable. It can be underlined that in the particular case:
Z s = Z in = Z ck = Z 0 , (8.11)
142 T. Eudes et al.
we have the simplified intermediate transfer function:
Vnode (s) 1
=
. (8.12)
Vin (s) [sinh(θin ) + cosh(θin )] · 1 + nk=1 Z k sinh(θk )+Z 0 cosh(θk )
Z 0 sinh(θk )+Z k cosh(θk )
8.2.3 VTF from SIMO–SISO Transform
For Z s = R, the total ABCD matrix of any M in M k electrical path of the system shown
in Fig. 8.2 can be determined with the matrix relation:

1R 1 0
[ABC D] Min Mk = × [ABC D]in × × [ABC D]k . (8.13)
01 Yk,node 1
Therefore, the four elements of the total matrix are expressed as:
[ABC D] Min Mk (1, 1) = (Z in Z ck Z k cosh(θk )cosh(θin ) + Z ck Z k Rcosh(θk )sinh(θin )

2Z Z Y
+ Z in ck k k,node cosh(θk )sinh(θin )
2 Z sinh(θ )sinh(θ )
+ Z in Z ck Z k RYk,node cosh(θk )cosh(θin ) + Z in k k in
+ Z in Z k Rsinh(θk )cosh(θin )
+ Z in Z c2k sinh(θk )cosh(θin ) + Z c2k Rsinh(θk )sinh(θin )
2 Z2 Y
+ Z in ck k,node sinh(θk )sinh(θin )
+ Z in Z c2k Yk,node Rsinh(θk )cosh(θin ) + Z in
2 Z cosh(θ )sinh(θ )
ck k in
2 Z Z ),
+ Z in Z ck Rcosh(θk )cosh(θin ))/(Z in (8.14)
ck k
[ABC D] Min Mk (1, 2) = (Z in Z ck sinh(θk )cosh(θin ) + Z ck Rsinh(θk )sinh(θin )

+ Z in
2
Z ck Yk,node sinh(θk )sinh(θin )
+ Z in Z ck Z k RYk,node sinh(θk )cosh(θin )
+ Z in
2
cosh(θk )sinh(θin ) + Z in R cosh(θk )cosh(θin ))/Z in
2
,
(8.15)
Z k Z ck cosh(θk )sinh(θin ) + Z k Z ck Z in Yk,node cosh(θk )cosh(θin )
2 sinh(θ )sinh(θ )
+Z in Z k sinh(θk )cosh(θin ) + Z ck k in
2
+Z ck Z in Yk,node sinh(θk )cosh(θin ) + Z in Z ck cosh(θk )cosh(θin )
[ABC D] Min Mk (2, 1) = , (8.16)
Z k Z ck Z in
Z ck
[ABC D] Min Mk (2, 2) = sinh(θk )sinh(θin ) + Z ck Yk,node sinh(θk )cosh(θin )
Z in
+ cosh(θk )cosh(θin ). (8.17)
This ABCD matrix is equivalent to the SISO network system corresponding to any
electrical path M in M k . To determine the voltage transfer function of this electrical
path, we can consider the five elementary ABCD matrices in cascade. The SISO
network consists of the cascaded elements: series input impedance Z s , input access
TL TLin , the shunt equivalent input impedance (of the TL TLm=k ), the output TLs
TLk , and the terminal loads Z k . It is clear that the prediction of the output voltages
V k should be easily achieved by the voltage transfer function for any input V in . For
this reason, the characterization of the asymmetrical tree stated in this chapter will
be performed via the behavioral analytical model of the asymmetrical tree for any
arbitrary signal path M in M k . Subsequently, the overall voltage transfer function can
be extracted from the first element of the ABCD matrix with the relationship:
Vk (s) 1
Tk (s) = = . (8.18)
Vin (s) [ABC D] Min Mk (1, 1)
To summarize the different phases of the proposed behavioral methodology, the

description of the routine algorithm will be introduced in the next paragraph.
8.3 Asymmetric Comb Tree Modeling
These tree topology models are not applicable for “unbalanced structures” as 1:n
comb tree network (with 1-input and n-outputs) as illustrated in Fig. 8.3. One reminds
that in the field of microwave engineering, this kind of multi-port distributed structure
is quasi-similar to the passive 1:n power divider.
For this reason, an innovative behavioral model of the particular case of unbal-
anced known as 1:n comb tree for the performance analysis of high-speed signal
distribution is dealing within the present chapter. First, the mathematical approach is
handled to figure out the analytical principle highlighting categorically the model
under consideration. More precisely, the VTFs corresponding to the electrical
response of each path interconnecting the input with each output will be determined.
This enables us to extract the frequency- and time-domain responses of the comb
trees. To materialize concretely the concept for SI prediction, we will examine a pro-
totype of comb tree network implemented on PCB with respect to the DDR3 RAM
clock distribution standard stated in [11]. After, further discussions on the ongoing
research work in the continuation of the present study will be proposed. Finally, the
conclusion summarizing the outlet of the chapter will be drawn.
Fig. 8.3 Illustrative view of

distributed 1:n comb tree
network with single input
N in and multiple output N k
(k = {1, …, n})
144 T. Eudes et al.
In order to predict the SI representing the information data propagating through

the distribution tree network, the behavioral method will be focused on the VTF
expression as reported in [29, 30]. Hence, the main proposal of the concept advanced
is the 1:n tree structure analog to an electronic system which connects a driver
gate signal, such as from a clock generator, toward n receivers, such as memory
components. Moreover, it is interesting to point out that the analytical concept stated
in this chapter is mainly based on the manipulation of the ABCD matrix by means
of the Y-matrix equivalence as suggested in [32, 33].
For the comprehensive view, let us consider the two-level interconnection 1:n tree
network presented in Fig. 8.4. This tree network is comprised of series resistance
Rs and TL access TL0 , from the single input attacked by V in and parallel TL TLk
connected to output loads Z Lk with k = {1, …, n}. Across the latter, the voltages V k
are delivered.
In this configuration, the signal is propagating through the common interconnect,
TL0 , and then split at the N 0 node through n TLs associated with each receiver. Con-
sequently, since this structure is unbalanced, the combination of reflections affects
the integrity of the delivered signals V k (k = {1, …, n}). As aforementioned, by
denoting s is the Laplace variable, in order to forecast the SI, one will proceed with
the determination of the VTF:
Receiver 1
TL1
ZL1 V1
Receiver 2
Source Gate
RS N0
TL2
ZL2 V2
TL0
V0
t Vin
Receiver n
TLn
ZLn Vn
Fig. 8.4 Schematic of unbalanced and non-symmetrical two-level tree network comprised of series
resistance Rs and intermediate TL TL0 as access input branch and parallel TLs TLk loaded by Z Lk
at the output branches (k = {1, …, n}) [29]
Vk (s)
Hk (s) = , (8.19)
Vin (s)
by considering that the intermediate node N 0 sees an equivalent total admittance

denoted Y T (N 0 ). This total admittance is the sum of the overall input admittances
connected to the intermediate node N 0 as shown above.

Nk
YT (k) = Y11x . (8.20)
x=1
In the other hand, one represents by Y 0 (k) represents the sum of admittances
connected at N 0 with the exception of the output branch k connected to the node N 0 .
8.3.2 T-Matrix Modeling
It is worth reminding that according to the TL theory, the ABCD matrix of elementary
distributed transmission line, TLx , satisfying the quasi-TEM propagation mode is
expressed as:

A x Bx cosh(γx · dx ) Z C x · sinh(γx · dx )
[TLx ] = = sinh(γx ·dx ) , (8.21)
C x Dx ZC
cosh(γx · dx )
x
where γ x and Zcx are, respectively, the propagation constant and the characteristic
impedance of the TL supposed here having physical length d x . As explored in [20],
these parameters can be extracted straightforwardly knowing the geometrical and
physical parameters of the TLs. By definition, the ABCD matrix is analog to the
lumped series resistance Rs and receiver impedance Z L k are, respectively, given by:

1 Rs
[Rs ] = , (8.22)
01
and:

1 Z Lx
Z Lx = . (8.23)
01
Acting as a cascade structure, according to the circuit theory, the equivalent

ABCD matrix of the whole system corresponding to any electrical path N in N k can
be determined for the following matrix product:

MTL11 (k) MTL12 (k)
[MTL (k)] =
MTL21 (k) MTL22 (k)
146 T. Eudes et al.
Driver Gate
TL0 N1 TL1 N2 Nn-2 TLn-2 Nn-1 TLn-1 Nn
Rs
YT1 YT2 YTn-1 YTn
Fig. 8.5 Equivalent electrical SISO circuit

1 RS 1 0 1 0
= × [TL0 ] × × [TLk ] × 1 . (8.24)
01 Y0 (k) 1 Z Lk
1
Thanks to the extension of the analytical approach of SIMO-to-SISO transform

expressed in the previous subsection, we will derive the VTF of the structure schema-
tized in Fig. 8.3. This comb tree is comprised of a driver gate symbolized by Rs series
resistance and voltage source connected to n-L-network consisted in turn of series
TL TLk −1 and overall parallel admittance Y Tk at the node N k . Similar to the con-
figuration depicted in Fig. 8.3, Y k integrate the load impedance Z Lk preceded by
its output TL. The main principle of the analytical process for this structure is that
the multi-level or n-level SIMO network is electrically assumed as a repetition of n
structures of cascaded two-level trees. Then, the VTF H k of multi-level comb tree
shown in Fig. 8.5 can be analytically extracted.
Meanwhile, the electrical SISO circuit is composed of a common TL, denoted
TL0 , and N − 1 other TLs for connecting each node. At each N k node, the equivalent
admittance Y Tk is also connected, as explained in Fig. 8.5. From this established
equivalent circuit, one indicated in the workflow depicted in Fig. 8.6 the simplified
methodology for extracting the overall ABCD matrix of this multi-level tree network.
It consists in calculating, first, each overall admittance of the branch k, denoted Y T (k).
Then, the overall ABCD matrix denoted ABC Dk+1 equivalent to the branch N in N k
of the tree shown in Fig. 8.5 can be calculated from the driver through the last branch
N. This matrix is obtained by the following matrix product:
−1
N 1 0
ABC Dk+1 = [ABC Dk ] × × [TLk ], (8.25)
YT (k) 1
k=1
where the initial matrix is defined as:

1 RS
[ABC D1 ] = × [TL0 ]. (8.26)
01
Fig. 8.6 Workflow of the

proposed behavioral
modeling
Afterwards, in order to find out the VTF H k at the targeted point N k of the network
for the input at N in , the equivalent admittance Y n (k) connected at the same node n
must be extracted by using Eq. (8.21). Finally, the ABCD matrix, denoted M n,k , at
the desired point k of the node n, can be obtained by:

1 0 1 0
Mn,k = [ABC Dn ] × × [TLk ] × 1 . (8.27)
Yn (k) 1 Z Lk
1
In order to check the validity of this behavioral analytical method, in the next
section, we will consider a proof of concept and proceed with comparisons of VTFs
obtained from simulations and measurement. To do this, the established behavioral
model and the workflow displayed in Fig. 8.6 will be implemented into MATLAB
programs. Then, for the given input signals V in , we will predict the desired output
waveform V out (N k ) for any values of k by means of convolution with the adequate
VTF.
148 T. Eudes et al.
8.4.1 Asymmetric Tree Modeling Methodology
Figure 8.6 represents the workflow of the proposed computational modeling of the
asymmetrical tree. It is executed in four main steps.
• In Step 1, the methodology is fundamentally built with the frequency-dependent
RLCG(f ) model of interconnect tree branches. The frequency-dependent per-unit-
length parameters (Ru (f ), L u (f ), C u (f ), Gu (f )) of the elementary transmission lines
(TLs) constituting the branches of the tree are extracted.
• Step 2 is the transformation of the RLCG parameters into the equivalent [Z]k (s)
and [Y ]k (s) matrices. Then, the SIMO model based on the topology introduced in
Fig. 8.4 is established based on the circuit and system theory.
• Then, via the Z/Y to ABCD transform, the transfer matrices corresponding to
each electrical path M in M k (k = {1, …, n}) are calculated in Step 3. The first
element of this transfer matrix which allows to determine the equivalent SISO
ABCD matrix is determined. Then, we can establish the voltage transfer function
of the asymmetrical tree.
• Step 4 will be the calculation of the transient voltage response by the mean of the
convolution with the input signal.
During the numerical tests, the presented routine algorithm was implemented as
a MATLAB program for an arbitrary asymmetrical tree as a POC.
8.4.2 Application with 1:3 Microstrip Asymmetric Tree

Structure
This section is focused on the proposed behavioral model validation inspired with
the use case of passive PCBs. As POC, design of the interconnect structure will be
introduced. The main aim of the numerical tests is to monitor the influence of the
metallic ink conductivity on the signal integrity propagating along the asymmetrical
tree. The POC is constituted of the single-input and triple-output network printed on
the Kapton plastic substrate described in the next paragraph.
The microstrip asymmetrical T-tree is assumed to be printed on the Kapton plastic

substrate with relative permittivity εr = 3.2, loss tangent tan(δ) = 0.008, and thickness
h = 125 µm. The different branches are laminated with deposited copper ink in thin
film with thickness t = 5 µm and with physical width w = 308 µm. It is interesting
to note that this design process will be focused on the analyses of single input and
three outputs of the considered asymmetrical T-tree. The circuit schematic of the
considered POC is displayed in Fig. 8.7. As we can see, it is comprised of two-level
asymmetrical SIMO tree network. The T-tree was excited with source having internal
resistance R = 5 and loaded by the lumped capacitors C k = 1 pF (k = {1, 2, 3}).
At the input, access of the tree was connected to an input resistance R in downstream
of the excitation voltage source V in .
Moreover, the layout of the asymmetrical tree structure is shown in Fig. 8.8. The
elementary TL branches present the physical lengths d in = 3 cm, d 1 = 2 cm, d 2
= 7 cm, and d 3 = 15 cm. Because of the laminated metallic thin layer roughness
and impurities, the strip line conductivity or resistivity can vary considerably. So,
we propose to investigate the effect of the resistivity varied with the following test
parameters ρ = {1 µ m, 2 µ m, 3 µ m, 10 µ m}.
Fig. 8.7 Schematic of the

considered asymmetrical
M1
T-tree with input resistance
R, loaded by Z 1 = C 1 , Z 2 = TL1 C1
C 2 and Z 3 = C 3 [28] R TLin M2
Min TL2 C2
vin
M3
TL3 C3
Fig. 8.8 Layout of the

single-input triple-output
asymmetrical interconnect
T-tree [28]
150 T. Eudes et al.
8.4.2.2 Frequency-Domain Analysis
After the MATLAB application of the algorithm introduced in Fig. 8.6, we realize
the frequency analyses of the thin-film single input and triple outputs’ asymmetrical
tree proposed in the previous paragraph. To do this, the frequency-dependent RLCG
parameters of each branch of the interconnect lines were extracted. A microstrip
line presenting physical width w = 308 µm and length d = 14 mm was simulated
from DC to 10 GHz in momentum environment of ADS. The EM computation
was performed by using moment method (MoM) solver. Knowing the reflection
and transmission parameters, the frequency-dependent model was extracted. The
corresponding frequency results are plotted in Fig. 8.7. As expected due to the skin
depth effect, the per-unit-length resistance plotted in Fig. 8.9a increases with the
frequency. It can be pointed out that the variation of the per-unit-length capacitance
C u and conductance Gu versus interconnect metallization resistivity is negligible.
Hence, as can be seen in Fig. 8.9c, C u is rather almost constant with the frequency
and presents the average value of about 0.1 nF/m. However, the per-unit-length
conductance Gu increases up to 45 µ−1 /m in the considered frequency band.
(a) =10µ .m =3µ .m =2µ .m =1µ .m

10
8
Ru ( /mm)
0
1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
(b) (c)
0.7
=10µ .m 0.1
0.6
=3µ .m 0.08
Lu (µH/m)
Cu , Gu
0.5 =2µ .m 0.06

0.4 =1µ .m
0.04
0.3 0.02
0.2 0
2 4 6 8 10 2 4 6 8 10
Frequency (GHz) Frequency (GHz)
Cu (nF/m) -1
Gu (m /m)
Fig. 8.9 a Frequency-dependent per-unit-length resistance of the asymmetrical tree TL branches

[28]. b Frequency-dependent per-unit-length inductance of the asymmetrical tree TL branches [28].
c Frequency-dependent per-unit-length conductance and capacitance of the asymmetrical tree TL
branches [28]
In addition, the behavioral model of the asymmetrical interconnect tree was com-
puted from DC to 10 GHz. The corresponding frequency responses are plotted in
Fig. 8.10. As expected, the asymmetrical tree behavior can be critical when ρ is
increased. For the laminated metal with the resistivity in order of 10 µ m, the inter-
connect line attenuation can be worse than 20 dB only from only 2 GHz, 0.5 GHz,
and 0.2 GHz, respectively, for d 1 = 2 cm, d 2 = 7 cm, and d 3 = 15 cm. This illus-
trates that the operated signal bandwidth should be limited to some GHz when the
TL length is in order of tens cm. In other words, for the input with bandwidth more
(a) 0
=10µ .m
=3µ .m
-10
|T1(j )| (dB)
=2µ .m
=1µ .m
-20
-30
-40
2 4 6 8 10
Frequency (GHz)
(b) 0
=10µ .m
-10 =3µ .m
|T2(j )| (dB)
-20 =2µ .m
=1µ .m
-30
-40
-50
-60
2 4 6 8 10
Frequency (GHz)
(c) 0
=10µ .m
=3µ .m
-20
|T3(j )| (dB)
=2µ .m
=1µ .m
-40
-60
-80
2 4 6 8 10
Frequency (GHz)
Fig. 8.10 a Magnitude of the transfer function corresponding to the asymmetrical tree branch
M in M 1 [28]. b Magnitude of the transfer function corresponding to the asymmetrical tree branch
M in M 2 [28]. c Magnitude of the transfer function corresponding to the asymmetrical tree branch
M in M 3 [28]
152 T. Eudes et al.
than 2 GHz, it can be pointed out that the interconnect tree output can be completely
distorted when ρ > 5 µ m.
Furthermore, the asymmetrical tree presents significant nonlinear transmission
phases through each branch. To highlight such an effect, the group delay analytically
defined by the opposite of the derivative of the transmission phase ∠Tk ( j f ) with
respect to the radian frequency:
∂∠Tk ( j f )
τk ( f ) = − . (8.28)
2π · ∂ f
was also computed. Figure 8.11 plots the frequency-dependent group delay through
the three branches M in M 1 , M in M 2 , and M in M 3 . It can be seen that significant dis-
crepancies are found compared to the ideal values τ 1 = τ (M in M 1 ) ≈ 0.26 ns, τ 2 =
τ (M in M 2 ) ≈ 0.53 ns, and τ 3 = τ (M in M 3 ) ≈ 0.95 ns. Moreover, the ripple is inversely
increased with the metallization resistivity.
=1µ .m =2µ .m =3µ .m =10µ .m

(a) 0.6
(ns)
0.4
1
M M
in
0.2
0
2 4 6 8 10
Frequency (GHz)
(b) 1
(ns)
0.8
2
M M
in
0.6
0.4
2 4 6 8 10
Frequency (GHz)
(c)
1.2
(ns)
1
3
M M
in
0.8
2 4 6 8 10
Frequency (GHz)
Fig. 8.11 Frequency-dependent delay of the asymmetrical tree branches. a M in M 1 , b M in M 2 , and

c M in M 3 [28]
The time-domain analyses were performed by considering the arbitrary digital data
“010110000”. This mixed signal presents 0.5 Gbps rate. Each bit element corresponds
to a trapezoidal signal with amplitude 1 V, pulse width 2 ns, and rise/fall time t r =
0.2 ns. The extracted per-unit-length parameters of the branches versus conductivity
from DC to 10 GHz are displayed in Fig. 8.12. It can be emphasized that the output
signals through the electrical paths M in M k (k = {1, 2, 3}) present rise times higher
than 1.5 ns. The 50% propagations’ delay can exceed the data period when the
interconnect length is more than 7 cm and the strip line ink resistive is higher than ρ
= 5 m m.
(a) =10µ .m
1
=3µ .m
=2µ .m
v1, V
0.5 =1µ .m
0 5 10 15
Time (ns)
(b)
1 =10µ .m
=3µ .m
=2µ .m
v2, V
0.5 =1µ .m
0 5 10 15
Time (ns)
(c)
=10µ .m
1 =3µ .m
=2µ .m
v3, V
0.5 =1µ .m
0 5 10 15
Time (ns)
Fig. 8.12 a Transient response of the POC asymmetrical tree branch M in M 1 for the 0.5 Gbps
rate input signal [28]. b Transient response of the POC asymmetrical tree branch M in M 2 for the
0.5 Gbps rate input signal [28]. c Transient response of the POC asymmetrical tree branch M in M 3
for the 0.5 Gbps rate input signal [28]
154 T. Eudes et al.
In order to highlight the SI influence of the asymmetrical T-tree under study,

eye diagram analyses were performed with 0.5 Gbps rate and 8-bit stream. The
same remark can be mentioned by using pseudo-random bit stream source with 8-
bit maximal sequence, and one creates the eye diagram displayed in Fig. 8.13. The
synchronous clock signal is represented by a 0.5 Gbps rate periodic signal. The
rise/fall times and threshold voltage for detecting external trigger are, respectively,
0.2 ns and 0.5 V. As can be seen in Fig. 8.13a, for the case of 0.5 Gbps rate data, the
height of the opening and the width of the cross are of about 1.5 ns. The eye pattern
confirms once again that the signal distortion due to the interconnect tree capacitive
effects in function of the input signal amplitude. By comparison of eye diagrams
shown in Fig. 8.13a–c, it can be pointed out the performance of the interconnect
structure is clearly better through the branch M in M 1 with eye opening height equal
to 100%.
Fig. 8.13 Eye diagram from (a)

0.5 Gbps data streaming
1
responses of the
vM (V)
asymmetrical T-tree
branches. a M in M 1 , 0.5
1
b M in M 2 , and c M in M 3 [28]
0
0 1 2 3 4
Time (ns)
(b)
1
vM (V)
0.5
2
0 1 2 3 4
Time (ns)
(c)
1
vM (V)
0.5
3
0 1 2 3 4
Time (ns)
8.4.2.4 Conclusion
A fast computational method of SI analysis on the asymmetrical T-tree is examined.

The mechanism of the behavioral modeling is based on the SIMO-to-SISO transform.
To do this, the elementary TLs are modeled with RLCG network. Then, the total VTF
can be extracted with the ABCD matrix analyses.
To illustrate the relevance of the behavioral model, an asymmetrical T-tree POC
with Cu-laminated plastic Kapton substrate was modeled and investigated. To illus-
trate the influence of the electrical metallization ink property, various analyses in both
frequency and time domains were conducted. The MATLAB computation illustrates
how the 0.5 Gbps digital signal be degraded notably with the interconnect length and
the ink conductivity. The influence of the interconnect asymmetrical tree on plastic
substrate on the SI parameters was discussed. Finally, eye diagram analyses were
performed to confirm the SI through the asymmetrical T-tree under investigation.
To cope with those technological limitations, more general behavioral models of
complex shape multi-level tree network will be featured in the continuation of this
study. In addition, the modeling of the electrical interconnect by taking into account
the crosstalk effects on the flexible substrate is currently in progress. Furthermore,
the principle of integrated circuit tree interconnect inter-branch with coupling effect
analysis will be considered.
8.4.3 Application with Comb Tree Structure
This section focus is on the experimental verification of the behavioral model and the
associated methodology introduced previously. A proof of concept will be designed,
modeled, and tested in order to confirm that the method exposed can be useful
for PCB comb tree. For the sake of the analytical computation and simplicity of
structure design, non-buffered high-level trees will be explored. As aforesaid earlier
in the introductive part, physical and electrical parameters for the high-speed clock
distribution such as RAM applications accorded to the standard reported in [11] will
be considered.
It is worth pointing out that the design and simulations performed along this
chapter were carried out with the standard tool for the microwave electronic simulator
Advanced Design System from Agilent™.
For the experimental analyses, we envisaged 1:8 comb tree structure for representing
structures equivalent to the distribution of clock signals to 8-input gates.
To apply the modeling concept developed, we considered the circuit schematic
sketched in Fig. 8.14. As we can see, this structure under test is devoted to interconnect
8 receivers represented by loads Z k (k = {1, …, 8}) with a single input attacked by
156 T. Eudes et al.
Fig. 8.14 3D representation

of the considered 1:8 comb
tree [29]
driver with voltage source V in (to be defined later in the next subsection for the
time-domain analysis) and internal series resistance Rs . The equivalent electrical
circuit is composed of cascaded 8-L-form-network consisted of elementary series
TLs TLix which connect two nodes together. For instance, TLi1 is located between
N 1 and N 2 . Then, each branch k is considered by an elementary parallel TLs TLnk
which is connected to the load Z k . Then, we materialized this schematic with a PCB
constituted by electric microstrip interconnect structures.
To design the proof of concept, the structure under test has been designed over
a PCB printed on a FR4 substrate of height h = 0.8 mm and relative permittivity
supposed ideally constant εr = 4.4. The dimensions of interconnects have been
determined with respect to the DDR3 standard indicated in [11]. Accordingly, the
adopted choices are summarized in Table 8.1. A 3D representation of the 1:8 comb
tree networks under test designed in the EMDS environment of ADS is displayed in
Fig. 8.14. The interconnect line is metallic conductors assigned as copper material
having thickness 35 µm etched on the FR4 substrate.
One assumes that the elementary TLs constituting the comb tree under test present
the same width w = 1 mm. Moreover, the TLik (for k = {1, …, 6}) and TLnk (for k
= {1, …, 7}) are supposed as identical with physical lengths respectively equal to
d i = 15.3 mm and d n = 8 mm.
8.4.3.2 S-Parameter Analysis
This subsection is stated on the comparison of S-parameters exhibited from simu-

lations, measurements, and the tree model. We emphasize that the MATLAB cal-
culations of the modeled S-parameters were performed via the use of frequency-
dependent RLCG(f ) model of each piece of TLs [13, 33]. Then, they were associ-
ated with means of ABCD matrices handling. Lastly, the modeled S-parameters were
obtained thanks to the ABCD-to-S-matrix transform [24, 34].
Table 8.1 Physical

TL Width w (mm) Length d (mm)
dimensions of the prototype
presented in Fig. 8.14 TL0 1.0 24.0
TLn1 1.0 8.00
TLi1 1.0 15.3
TLn2 1.0 8.00
TLi2 1.0 15.3
TLn3 1.0 8.00
TLi3 1.0 15.3
TLn4 1.0 8.00
TLi4 1.0 24.8
TLn5 1.0 8.00
TLi5 1.0 15.3
TLn6 1.0 8.00
TLi6 1.0 15.3
TLn7 1.0 8.00
TLn8 1.0 23.3
As a proof of concept, the prototype of 1:8 comb tree photographed in Fig. 8.15
was manufactured and measured. The characterization of the comb tree has been
made within the 100 kHz–8.5 GHz frequency bandwidth by using a VNA Agi-
lent EC5071C. The test was conducted under SOLT calibration. By optimizing the
number of measurements, the 9-port S-matrix has been reconstructed.
As aforementioned earlier, from these measurements, comparisons were made
with the proposed model and simulations from ADS of Agilent. It is worthy of note
that connectors are not taken into account both with the model and simulations.
Figures 8.16, 8.17, 8.18, 8.19, 8.20 are the plots of some remarkable results of
respectively S 21 , S 31 , S 41 , and S 91 . We point out that very good correlations have been
found out between measurements, simulations, and the proposed model, considering
the effects of connectors.
Nevertheless, a kind of “non-physical” behavior has been identified for the S 21
phase (Fig. 8.17a and zoom in Fig. 8.17b). Indeed, the positive slope within the 0–
100 MHz frequency band indicates a negative group delay. This behavior has been

manufactured comb tree as
proof of concept (feature size
161 mm × 46 mm) [29]
158 T. Eudes et al.
-2
-4
S21 Magnitude (dB)
-6
-8
-10
-12 Measurement
Simulation
Model
-14
-16
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
Fig. 8.16 S 21 between the input and receiver no. 1 [29]
found first in simulations using ADS and the proposed model (Fig. 8.17a) and then
also was confirmed by measurements (Fig. 8.17b).
Despite this unusual behavior, the developed model gives very good results in
S-parameters according to simulations from ADS and measurements from the VNA.
It is noteworthy that for higher frequencies, differences between the model and
simulations are heightened. This behavior comes from the RLCG model in function
of the frequency used in this proposed technique. Indeed, this extraction method
uses a frequency dispersion model for losses [20]. In addition, beyond 4 GHz the
differences with measurements are higher that shows the frequency limitation of the
FR-4 substrate. The connector effects also exaggerate this situation.
8.4.3.3 VTF Analysis
For the frequency AC analysis presented in this subsection, the comb tree outputs are
loaded at each termination by a parallel RC circuit as illustrated earlier in Fig. 8.4. The
impedance source is considered as a pure resistor Rs = 10 . The physical dimensions
of the output TLs and the realistic parameters of the output RC loads employed
connected at the terminations of the comb tree under test are recalled in Table 8.2.
As expected, this justifies once again that the tree network structure under test is
obviously typically unbalanced. The simulated VTFs are extracted straightforwardly
from the AC analysis in ADS schematic environment, while VTFs from the proposed
model were calculated by implementing the algorithm in Matlab.
(a) 100
0
S21 Absolute Phase (°)
-100
Simulation
Model
-200
-300
-400
-500
-600
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
(b) 50
40
30
S21 Absolute Phase (°)
Measurement
20 Simulation
Model
10
0
-10
-20
-30
-40
-50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (GHz)
Fig. 8.17 S 21 phase between the input and receiver no. 1 (a) and negative group delay confirmed
by measurement (b) [29]
Frequency-domain comparisons are made between simulations and the mode for
each receiver. The VTFs of H 1 and H 8 are given in amplitude and phase, respectively,
in Figs. 8.21a, b and 8.22a, b.
Next, the standard deviation was calculated for each H x VTF (with x = {1, 2, …,
8}) and for different frequency bandwidth, DC—3 GHz, 3–5 GHz, and 5–10 GHz.
The results obtained are summarized in Table 8.3.
The obtained results show an excellent correlation between the simulations and
the calculations based on the developed model. As expected, the differences are more
heightened for high frequencies due to the frequency dispersion model. Nonetheless,
the accuracy obtained will be sufficient for the SI forecasting in this network.
160 T. Eudes et al.
-6
-8
S31 Magnitude (dB)
-10
-12
Measurement
Simulation
Model
-14
-16
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)

-5
-10
S51 Magnitude (dB)
-15
-20
Measurement
Simulation
Model
-25
-30
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)
An innovative modeling method of unbalanced interconnect tree network known

as 1:n comb tree is successfully stated. In the best of the authors’ knowledge, this
study was never done before. The concept proposed can be generalized for predicting
SI. Analytical approach illustrating the mathematical interpretation of the concept
is described. The methodological routine algorithm is offered. First, the RLCG(f )
parameters of each elementary TLs constituting the interconnect tree are extracted
from geometrical and physical properties. Then, based on the handling of ABCD and
-10
-15 Measurement
S91 Magnitude (dB) Simulation
Model
-20
-25
-30
-35
-40
0 1 2 3 4 5 6 7 8 9
Frequency (GHz)

Table 8.2 Physical TL Width w (mm) Length d (mm) Loads
dimensions and RC values of
the terminations TL0 1.0 24.0
–
TLn1 1.0 8.00 R1 = 5000
C 1 = 1.0 pF
TLi1 1.0 15.3
–
TLn2 1.0 8.00 R2 = 2000
C 2 = 2.0 pF
TLi2 1.0 15.3
–
TLn3 1.0 8.00 R3 = 1000
C 3 = 2.0 pF
TLi3 1.0 15.3
–
TLn4 1.0 8.00 R4 = 6500
C 4 = 1.0 pF
TLi4 1.0 24.8
–
TLn5 1.0 8.00 R5 = 5500
C 5 = 0.5 pF
TLi5 1.0 15.3
–
TLn6 1.0 8.00 R6 = 5700
C 6 = 2.0 pF
TLi6 1.0 15.3
–
TLn7 1.0 8.00 R7 = 8000
C 7 = 0.6 pF
TLn8 1.0 23.3 R8 = 3500
C 8 = 5.0 pF
162 T. Eudes et al.
(a) 20
Simulation
10
Model
0
VTF Gain (dB)
-10
-20
-30
-40
0 1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
(b) 200
0
Simulation
VTF Absolute Phase (°)
Model
-200
-400
-600
-800
0 1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
Fig. 8.21 VTF amplitude (a) and phase (b) of H 1 [29]
Y-matrices, mathematical expressions of the VTF for different n-levels of comb tree
networks are established.
For validating the behavioral model, a proof of concept consisting of a PCB 1:8
comb tree microstrip circuit was designed, constructed, and measured. The imple-
mented prototype was intentionally chosen with respect to the DDR standardization
reported in [11]. Comparisons between the AC analyses of VTFs from simulations
and the calculated models were realized in the frequency band from DC to 8.5 GHz.
It was stated that due to substrate dispersion and loss which were not taken into
account in the behavioral modal, slight differences were occurred between the fre-
quency results at higher frequencies. The slight differences between the models,
simulations, and experimentations occurred at higher frequencies are mainly due to
the dispersion of the substrate employed. Furthermore, with time-domain investiga-
tions, the SI characteristics as propagation delay and rise/fall times are extracted. The
(a) 20
0
-20
-40
VTF Gain (dB)
Simulation
-60 Model
-80
-100
-120
-140
-160
0 1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
(b) 0
-500
VTF Absolute Phase (°)
Simulation
Model
-1000
-1500
-2000
-2500
-3000
-3500
0 1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
Fig. 8.22 VTF amplitude (a) and phase (b) of H 8 [29]
degradations of signals obtained with the considered structure justify the necessity to
forecast SI for designing high-speed interconnects’ structures. For that, 2-Gbps rate
input was considered. For the different tests performed, good agreements have been
found between simulations from a commercial tool and the results obtained with the
proposed fast modeling.
The SI prediction is indispensable especially for complex shape interconnects
in designing high-rate integrated circuits in order to preserve the quality of data
synchronization and processing. Indeed, this technological limitation is currently
a major issue for microelectronic manufacturers. As future work, the prominent
methodology explored in this chapter will also be proposed to predict the performance
of IC advanced packages based on 3D integration technology or silicon interposer
solutions recently analyzed [26].
164 T. Eudes et al.
Table 8.3 Standard deviation in amplitude and phase between the results obtained from the
simulation and the model
VTF Frequency bandwidth VTF gain standard VTF phase standard
(GHz) deviation (dB) deviation (°)
H1 0–3 0.767 5.355
3–5 3.093 22.33
5–10 3.763 24.05
H2 0–3 0.953 7.173
3–5 2.921 19.25
5–10 3.646 23.90
H3 0–3 1.113 8.570
3–5 2.856 18.99
5–10 3.715 24.42
H4 0–3 1.333 10.356
3–5 2.941 19.59
5–10 4.363 28.85
H5 0–3 1.647 12.258
3–5 3.103 21.24
5–10 3.673 23.94
H6 0–3 1.841 13.916
3–5 3.079 20.88
5–10 3.476 22.98
H7 0–3 1.844 13.160
3–5 2.583 17.23
5–10 3.205 21.00
H8 0–3 1.576 12.170
3–5 2.935 22.93
5–10 3.539 21.91
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Chapter 9
Cartographical Analyses of Reflection
and Transmission Coefficients of Shunt
Coupled Lines
Blaise Ravelo
9.1 Introduction
The high-speed PCB design performances depend naturally on the electrical multi-
conductor interconnect coupling constraints [1]. An accurate and relevant characteri-
zation method is expected to predict the unintentional degradation due to the electrical
effects as crosstalk. Predictive modelling methods can be used during the printed cir-
cuit board design phases [2]. The PCB interconnect crosstalk can affect undesirably
the digital signal bit error rate [3, 4]. Furthermore, the interconnect input/output
line coupling can generate awful electromagnetic radiating emission [5]. Tentative
roadmaps report that more accurate predictive signal and power integrity models are
needed to realize reliable high-speed electronic circuits [6].
Different circuit analysis tools [7, 8] in particular for printed circuit board link
levels were provided to help the design engineers against the degradation phenomena
due to the undesirable effects as crosstalk. But faster and easier modelling method-
ology is required when the integration density is increased [9]. Therefore, printed
circuit board TL RLCG-based modelling methods were suggested for the responses
of pre-visualization and pre-determination of the signal reflection, attenuation, delay,
differential noise and further distortions [10–12]. In addition, optimization algorithms
built with typically RC and RLC networks were also proposed for the SI and PI anal-
yses and also to improve the printed circuit board interconnect line performances
[13, 14]. One of main applications of the RLC network modelling is the accurate
prediction of clock signal distribution electrical interconnects.
Behind the developed model, the interconnect coupling effects can be occurred
for certain parameters of the clock signalling sharing topology [15]. The advanced
interconnect network is regularly used during the digital system design phase to
ensure the signal synchronization [16]. The electrical interconnect tree topologies
B. Ravelo (B)

168 B. Ravelo
are among the most popular signal distribution for the digital circuit implementation.
Furthermore, the interconnect tree network plays an important role notably to predict
the signal synchronization and attenuation [17, 18]. However, the interconnect inter-
branch coupling remains an open issue during the implementation of the interconnect
tree in the confined space. So far, time-consuming simulation techniques of inter-
connect crosstalk were proposed [19]. The most popular of the existing simulators
are using solvers based on the time domain [20] or finite-element frequency-domain
[21] approaches. The main drawbacks of such simulation tools are the necessity
to design the entire printed circuit board structures usually with complex geometry.
Such a full-wave simulation can be accurate for certain cases of symmetrical coupled
lines. An approximation method of worst-case system-level crosstalk at higher fre-
quencies with analytical formulas is developed in [22]. Then, deeper level crosstalk
between interconnect very large-scale integration CMOS and field effect transistor
circuits was suggested by virtue of TL approach [23, 24]. A computation method
of improper radiating modes (leaky modes) based on the propagation characteris-
tics of coupled microstrip TLs is presented in [25]. However, further concepts are
recently developed to predict the interconnect couplings for various cases of com-
posite right/left-handed TL [26] and complex-layout traces [27] of printed circuit
boards. Thus, a more generalized macromodel concept of high-speed interconnect
SI analyses based on full-wave time-domain was also introduced in [28]. But the
implementation of model based on rational transfer function approximated is fairly
complex.
In complementary to the digital system signal integrity analyses, the coupled
line networks are regularly used to design microwave planar circuits thanks to its
benefits in term of the compactness [29–33]. For example, the coupled line can
be employed for the bus link used to ensure the equipartitioned energy [29]. The
design and implementation of high-performance microwave coupled line filters [30–
32] constitute one of the most attractive breakthroughs for the electronic design
and research engineers. Basically, the employed topologies are based on the stub-
embedded resonators with the synthesis of the transmission zeros (TZs) and reflection
zeros (RZs). The design concept is carried out with admittance-transformer feeds
for flexible terminations [30]. A synthesis method dedicated to the dual-wideband
bandpass filters is introduced in [31]. The particularity of this filter topology is
based on the integration of source–load coupling network. The basic filter block
is built with stepped impedance resonators. To meet the multistandard demand for
wireless communication system, more complex synthesis approach for a multiband
low temperature co-fired ceramics (LTCC) bandpass filter was also implemented
[32].
Despite this diversity of coupled line applications, further investigation is still
needed for the implementation of optimum termination networks. A tentative method
was suggested based on the coupling mode and matrix approaches [33, 34]. But
such methods are not expanded enough due to the lack of analytical understanding
on the mechanism of the coupling effects as the TZ and RZ positions. A relevant
calculation method is required during the synthesis of high-density mixed circuits.
For this reason, accurate modelling methods are still needed for the particular cases
9 Cartographical Analyses of Reflection and Transmission … 169
of coupled line structures as the parallel stub resonators in function of the coupling
level.
The present chapter addresses a complete theory on the coupled-parallel-line
(CPL) used as a parallel stub including the crosstalk phenomenon. Based on the full
coupling matrix combined with the direct input–output TL, a fast and accurate CPL
model with the theoretical exact expressions of the TZs and RZs will be established.
Then, illustrative applications will be proposed to approve the established theoreti-
cal formulations. Lastly, discussion on the potential applications of the established
modelling concept will be drawn in the conclusion.
9.2 CPL Modelling Theory
The innovative modelling methodology established in this chapter is constructed with

the structure consisted of the distributed lines integrating crosstalk phenomenon. The
whole circuit is assumed as an asymmetrical CPL.
9.2.1 Description of the Asymmetrical CPL Structure
The CPL configuration including the source and load terminals represented by the
reference impedance R0 = 50 is presented in Fig. 9.1a. In other words, it acts
as a structure of parallel stub constituted by TLs ➀–➂ and ➁–➃ with different
lengths d 1 and d 2 (with d 1 > d 2 ). The two parallel stubs are supposedly separated
by space s. It is worth emphasizing that the overall structure is implemented in
microstrip technology and each stub is terminated by the arbitrary loads R1 and
R2 . Nonetheless, the extraction of the equivalent model enabling to determine the
fundamental elements as the even- and odd-mode characteristic impedance’s Z o and
Z e is required during the design phase and implementation of electronic structures.
In this way, the CPL equivalent diagram is introduced in Fig. 9.1b. This equivalent
model takes innovatively into account the interbranch coupling.
For the sake of the analytical simplification, the TLs are supposed as a lossless
structure. It can be recalled that the physical lengths dk and the resonance radian
frequencies ωk (k = {1, 2}) of the two elementary TLs are linked by the relation:
πv
dk = , (9.1)
2ωk
by denoting v the wave speed. The main technical issue to be solved in this chapter is
the influence of the stub ➀–➁ over length on the CPL TZ and RZ. Substantially, the
electrical length of the stub over length between TL1 and TL2 (d 1 > d 2 ) is analytically
defined by:
170 B. Ravelo
Fig. 9.1 a Microstrip CPL structure under study including the source and load impedances of the
CPL structure under study [35], b equivalent diagram of the CPL structure under study [35]
πω
θa (ω) = . (9.2)
2ωa
This electrical length can be rewritten as:

π ω(ω2 − ω1 )
θa (ω) = . (9.3)
2ω1 · ω2
It can be recalled that the ABCD matrix of the TL having characteristic impedance
Z c and electrical length θ is defined by:

cos(θ ) Z c · sin(θ )
[ABC D]TL = . (9.4)
sin(θ)
Zc
cos(θ )
The corresponding Z- and Y-matrices can be extracted from the ABCD-to-Z and
ABCD-to-Y transforms following the circuit and system theory.
9.2.2 Equivalent Impedance Matrix of the Asymmetrical CPL
The analytical operations performed to extract the equivalent mathematical model of

the CPL shown in Fig. 9.1a were extracted from the ABCD-to-Z matrix (to generate
the TL impedance matrix) and Z-to-Y matrix (to extract the equivalent CPL) and Y-
to-ABCD matrix transforms (to express the equivalent transfer parameters) proposed
in [35]. Subsequently, the equivalent circuit diagram considered in Fig. 9.1b can be
transformed as depicted in Fig. 9.2.
It can be found that the circuit is constituted by the octopole coupler with Ports ➀
and ➁ short-circuited, open-ended Port ➂ and Port ➃ loaded by the input impedance
of the open-ended stub. The CPL four-port Z-matrix model is defined by:
⎡ ⎤ ⎡ ⎤ ⎡ ⎤
V1 Z 11 Z 12 Z 13 Z 14 I1
⎢ V2 ⎥ ⎢ Z 21 Z 22 Z 23 Z 24 ⎥ ⎢ I2 ⎥
⎥ ⎢
[V ] = ⎢ ⎥ ⎢
⎣ V3 ⎦ = ⎣ Z 31 × ⎥. (9.5)
Z 32 Z 33 Z 34 ⎦ ⎣ I3 ⎦
V4 Z 41 Z 42 Z 43 Z 44 I4
By reason of symmetry of the CPL under study, we have Z mn = Z nm for the

subscript m, n = {1, 2, 3, 4}. By denoting Z e and Z o the even- and odd-mode
characteristic impedances respectively, the Z-matrix model of the four-port CPL
structure can be expressed as:
⎡ Z e +Z o Z e −Z o Z e −Z o Z e +Z o ⎤
2 j tan(θ) 2 j tan(θ) 2 j sin(θ) 2 j sin(θ)
⎢ Z e −Z o Z e +Z o Z e +Z o Z e −Z o ⎥
⎢ ⎥
[Z ] = ⎢ 2 j tan(θ)
Z e −Z o
2 j tan(θ)
Z e +Z o
2 j sin(θ)
Z e +Z o
2 j sin(θ)
Z e −Z o ⎥, (9.6)
⎣ 2 j sin(θ) 2 j sin(θ) 2 j tan(θ) 2 j tan(θ) ⎦
Z e +Z o Z e −Z o Z e −Z o Z e +Z o
2 j sin(θ) 2 j sin(θ) 2 j tan(θ) 2 j tan(θ)
√
with j = −1 and the TL electric length is defined by:
172 B. Ravelo
Fig. 9.2 Transformed equivalent diagram of the CPL circuit introduced in Fig. 9.1b
πω
θ (ω) = . (9.7)
2ω2
This Z-matrix can serve to the derivation of the CPL input parallel impedance and
then, the corresponding global S-parameters.
9.2.3 Analytical Expressions of the CPL Input Impedance
The load Z L constitutes the input impedance of the over length TL of the stub ➀–➂
which presents an electrical length θa . In function of the load R1 , based on the TL
theory, the input impedance of the over length stub which can be characterized by
TL (Z c , θa ) is given by:
Z c [R1 + j Z c tan(θa )]
ZL = . (9.8)
Z c + j R1 tan(θa )
Hence, the vector currents [I] of the CPL octopole network described in Fig. 9.2
are determined by inverting the generalized Ohm’s law:
[V ] = [Z ] · [I ], (9.9)
with the Z-matrix defined in (9.5). As Ports ➀ and ➁ are electrically connected,
therefore
Vin = V1 = V2 . (9.10)
Moreover, the CPL input current can be expressed as:
Iin = I1 + I2 . (9.11)
Via Ohm’s law, the CPL input impedance can be deduced via the basic relation:
V1 ( jω)
Z in ( jω) = . (9.12)
Iin ( jω)
After the mathematical analyses, we can establish the branch current relationships:
I3 − I4
I2 = I1 − , (9.13)
cos(θ )
⎡ ⎤
R1 tan(θa )(Z e (2 + tan2 (θ ) + 2/ cos(θ ))
2Z e [R1 tan(θa )−Z c ]
cos(θ)
I1 + ⎣ +Z o tan2 (θ )) ⎦ I4
− j Z c (Z e (2 + tan (θ )) + Z o tan (θ ))
2 2
I3 = , (9.14)
R1 (Z o + Z e ) tan(θ ) tan(θa ) − 2R1 Z c tan(θ )
− j Z c [2Z c tan(θa ) + (Z o + Z e ) tan(θ )]
I4 2Z e [Z c (Z o tan(θ ) + Z c tan(θa )) + j R1 (Z o tan(θa ) − Z c )]
=
,
I1 R1 R2 (Z e + Z o ) tan2 (θ ) − (2 + tan2 (θ ))Z e − Z o tan2 (θ ) Z c2 tan(θa )

R Z Z (2 + tan2 (θ )) − 2R02 R1 tan(θa )
−2 R02 + R1 R2 Z c tan(θ ) + j 1 e c 2
−Z c tan (θ )(R2 (Z e + Z o ) + R1 Z o )
(9.15)
where I 1 is the input current propagating through Port ➀. By substituting expressions

(9.13)–(9.15) in matrix relation (9.9), the input impedance of the CPL can be derived.
From this general relation, the CPL input impedance for the particular cases of port
in short-circuit R2 = 0, open-circuit R2 = ∞ and matched R2 = R0 , respectively, can
be determined as follows:
174 B. Ravelo

j Z e R1 2tan(θ) 2R02 tan(θa ) tan(θ ) − Z c (Z e + Z o )
Z in | R2 =0 =
, (9.16)
R1 Z c
(Z o tan2 (θ ) − Z e ) + 2R02 tan(θ ) tan(θa )
−Z c j Z c tan(θa )(Z e − Z o tan2 (θ )) + 2R02 tan(θ )
j Zc Ze
[2 tan(θa )Z c + tan(θ )(Z e + Z o )]
Z in | R2 =∞ = 2
, (9.17)
Z c (Z e
− tan2 (θ )Z o ) − 2Z c2 tan(θ ) tan(θa )
+ j R1 (Z e − Z o tan2 (θ )) tan(θa ) + 2Z c tan(θ )

Ze 2 tan(θa ) R0 Z c2 − R1 R02 tan2 (θ )
j 2 + Z c tan(θ )(R1 (Z e + Z o ) + R0 Z o )
Z in | R2 =R0 = . (9.18)
(R1 + R2 )Z e Z c − tan

2
(θ )(2(R1 + R2 )Z o Z c )

0 R1 R0 + Z c tan(θ ) tan(θ
a )
− 2R 2
+ j 2(R0 + R1 )R0 Z c tan(θ ) + (Z e − Z o tan2 (θ ))Z c2

+ R0 R1 (Z e − 2Z o )] tan(θa )]
For the particular case where R1 and R2 both short-circuited, it can be demonstrated
that:

j Z e tan(θ ) 2R02 tan(θ ) + Z c tan(θa )(Z e + Z o )
Z in | R1 =0 =
. (9.19)
R2 =0 4R02 tan(θ ) + 2Z c tan(θa ) Z e − 2Z o tan2 (θ )
Emphatically, the generalized formulations of the CPL input impedance can be

established from the combination of the previous expressions for R2 = 0 and R2 =
∞. Furthermore, it implies that at the quarter- and half-wave length frequencies of
the TL between Port ➁ and Port ➃ which is defined as:
ω = {ω2 , 2ω2 }, (9.20)
and the over length TL (Z c , θa ) assumed with characteristic impedance Z c defined

as:
ω = {ωa , 2ωa }, (9.21)
Therefore, the input impedance Z in will be respectively transformed as:

⎧ R Z 2 tan(θ (ω ))
⎪
⎪ Z in (ω = ω2 ) = R R −Z12 e tan(θ a(ω 2))+ j R Z
⎨ ( 1 2 c) a 2 1 c
R2 Z e Z c2 tan(θa (2ω2 ))
Z in (ω = 2ω2 ) = , (9.22)
⎪
⎪ Z e R1
R2 − Z c2 tan(θa (2ω2 ))
⎩
+ j Z c Z e (R1 − R2 ) + R2 Z c tan2 (θa (2ω2 ))
⎧ ⎡ ⎤
⎪
⎪ 2(R2 Z c2 + R1 Z e Z o tan2 (θ (ωa ))
⎪ Ze⎣ ⎦
⎪
⎪ + j R1 R2 − Z c2 (Z e + Z o ) tan(θ (ωa ))
⎪
⎪ Z in (ω = ωa ) =

⎪
⎪ 2 Z c2− R1 R2 Z e − Z o tan2 (θ (ωa ))
⎪
⎪
⎨
+⎡
4 j R1 Z e Z o − R2 Z c2 tan(θ (ωa )) ⎤ . (9.23)
⎪
⎪ 2R1 R2 + 2Z e Z o tan2 (θ (2ωa ))
⎪
⎪ Ze ⎣ ⎦
⎪
⎪ + j (Z e − Z o )(R1 − R2 ) tan(θ (2ωa ))
⎪
⎪ Z in (ω = 2ωa ) =
⎪
⎪ 2(Z e − Z o )(R2 − R1 ) tan2 (θ (2ωa ))
⎪
⎩
+ 2 j (R1 R2 − Z e Z o ) tan(θ (2ωa ))
These equation systems permit the direct calculation of the under study CPL
S-parameters in function of the particular frequencies corresponding to the physical
lengths of the structure. Substantially, the reflection and transmission parameters are
expressed as:

−R0
S 11 ( jω) = 2Z in ( jω)+R0
. (9.24)
S 12 ( jω) = 2Z in
2Z in ( jω)+R0
Acting as a passive symmetrical structure, the input and output reflec-

tion/transmission parameters are linked by:
S 11 ( jω) = S 22 ( jω), (9.25)
and
S 12 ( jω) = S 21 ( jω). (9.26)
9.2.4 CPL TZ and RZ Existence Conditions
By definition, the CPL structure under study presents TZs and RZs at the radian
frequency ω when Z in ( jω) = 0 and Z in ( jω) = ∞, respectively. Using these
conditions, the TZ and RZ existence conditions in function of the CPL parame-
ters can be established. Meanwhile, for the different configurations of R1 and R2
at the arbitrary frequency, the TZ and RZ existence conditions can be derived from
expressions (9.16)–(9.19). However, by using generalized fundamental formulations
(9.17)–(9.18), the TZ existence condition of the CPL structure introduced in Fig. 9.1a
is written as:
cot(θ)[2Z c tan(θa )+tan(θ)(Z e +Z o )]
R1 = R2 Z c2R
0 tan(θ) tan(θa )+Z c (Z e +Z o )
2
R1 tan(θ)[2R02 tan(θa ) tan(θ)−Z c (Z e +Z o )] . (9.27)

⇔R = 2 Z c [2 tan(θa )Z c +tan(θ)(Z e +Z o )]
176 B. Ravelo
Moreover, an application of algebraic invariant condition can also be established

by annihilating the coefficient of either R1 or R2 . Accordingly, it can be demonstrated
that the CPL TZ phenomenon can be occurred independently to R1 and R2 :

2Z c tan(θa ) + tan(θ )(Z e + Z o ) = 0
. (9.28)
2R02 tan(θ ) tan(θa ) + Z c (Z e + Z o ) = 0
Similarly, the RZ existence condition can be established from the equation

Z in ( jω) = ∞. It yields that the proposed CPL RZ existence condition is written
as:
⎧
⎨ (Z o tan2 (θ ) − Z e )Z c2 −
× tan(θa ) = 2 R1 R2 + R02 Z c tan(θ )
R1 R2 (Z e − Z o ) tan (θ )
2 .
⎩
(R1 + R2 )Z c Z o tan2 (θ ) + 2 R1 R02 + R2 Z c2 × tan(θ ) tan(θa ) = (R1 + R2 )Z c Z e
(9.29)
The same, the TZ existence condition can also be established when for the differ-
ence cases where R2 is short-circuited, open-ended and 50 -matched. Meanwhile,
the unified existence condition is the existence conditions which are respectively
simplified as:

tan(θ ) 2R02 tan(θa ) tan(θ ) − Z c (Z e + Z o ) = 0, (9.30)
2 tan(θa )Z c = tan(θ )(Z e + Z o ), (9.31)

2 tan(θa ) R1 R02 tan2 (θ ) − R0 Z c2 = Z c tan(θ )(R1 (Z e + Z o ) + R0 Z o ). (9.32)
9.2.5 Fundamental Characteristic Equations of TZs and RZs

in Function of the CPL Coupling Level
First, the present analytical characterization is limited to the particular cases where
R2 = 0 and R2 = ∞ for the sake of simplicity. Then, by denoting k the coupling coef-
ficient between the two branches of the CPL, the even- and odd-mode characteristic
impedances by the basic relations:
⎧
⎨ Z e = R0 1+k
1−k . (9.33)
⎩ Z o = R0 1−k
1+k
By substituting these definitions of Z e and Z o into expressions (9.33), the TZ and

RZ fundamental characteristic relations under the conditions R2 = 0 and R2 = ∞
can be rewritten in function of k. The corresponding characteristic equations of CPL

TZ for the different cases of the loads R1 and R2 are addressed in Table 9.1. It can
be found that for certain cases of R1 and R2 , TZ basic inequality conditions must be
respected in order to generate real solutions of theses characteristic equations. The
similar characteristic equations for the case of the RZ analysis are given in Table 9.2.
It is worth noting that these expressions are meaningless only if k < 0 and k > 1.
It can be understood from these trigonometrical relations also that the TZs and RZs
can be naturally occurred periodically notably related to the values of ωzero and ωa .
The illustrative numerical applications of these characteristic equations will be
explored in the next paragraph. To do this, the TZ and RZ frequency positions will
be analysed in function of the coupling level and the stub resonance frequencies.
Table 9.1 Characteristic equations of CPL TZ

R2 = 0 R1 = 0 k =1− Z c2 tan2 (θa )

R0 tan(θ ) R0 tan(θ )± R02 tan2 (θ )−Z c2 tan2 (θa )
tan2 (θ ) Z c2
Under the condition tan2 (θa )
≥ R02
R1 = ∞ k =1− 1
tan(θ ) tan(θa )
R2 = ∞ R1 = 0 R02 tan2 (θ )
k =1−
Z c tan(θa ) Z c tan(θa )± Z c2 tan2 (θa )−R02 tan2 (θ )
tan2 (θa ) R02

Under the condition tan2 (θ )
≥ Z c2
R1 = ∞ R02 tan2 (θ ) tan2 (θa )

k =1−
Zc Z c ± Z c2 −R02 tan2 (θ ) tan2 (θa )
Z c2
Under the condition tan2 (θ) tan2 (θa ) ≤ R02
Table 9.2 Characteristic equations of CPL RZ

R2 = 0 R1 = 0 Z c2 tan2 (θa ) tan4 (θ )−1 ±4R0 tan2 (θ ) R02 +Z c2 tan2 (θa )
k= 2
4R02 tan2 (θ )+Z c2 tan2 (θa )[tan2 (θ )+1]
2 tan(θ ) tan(θa )+tan2 (θ )−1
R1 = ∞ k= 2 tan(θ ) tan(θa )+tan2 (θ )+1
Under the condition 2 tan(θ) tan(θa ) + tan2 (θ) ≥ 1

R2 = ∞ R1 = 0 R02 tan4 (θ )−1 ±4Z c tan2 (θ ) tan(θa ) R02 +Z c2 tan2 (θa )
k= 2
4Z c2 tan2 (θ ) tan2 (θa )+R02 [tan2 (θ )+1]

R1 = ∞ R02 tan2 (θa ) tan4 (θ )−1 ±4Z c tan2 (θ ) Z c2 +R02 tan2 (θa )
k= 2
4Z c2 tan2 (θ )+R02 tan2 (θa )[tan2 (θ )+1]
178 B. Ravelo
9.2.6 Graphical Monitoring of the Analytical Relations

Between TZ and RZ with Stub Resonance Frequency f2
and Coupling Factor k
Based on the characteristic equations established previously in Tables 9.1 and 9.2,
the cartographies illustrating the existence areas of TZs and RZs in function of
the ratio ω2 /ω1 and the coupling factor k are elaborated. The explored numerical
computations were determined by considering that ω2 /ω1 is varied from 1 to 5. The
TZ (Fig. 3.6a) and RZ (Fig. 3.6b) radian frequencies to ω1 ratio ωzero /ω1 were also
supposedly varied from 1 to 5. As a matter of fact, the cartography of (k, ω2 /ω1 ,
ωzero /ω1 ) for the different coupled values of the loads (R1 = ∞, R2 = ∞), (R1 =
0, R2 = ∞), (R1 = ∞, R2 = 0) and (R1 = 0, R2 = 0) are, respectively, displayed
in Figs. 9.3, 9.4, 9.5 and 9.6. The RZ cartographies do not present any particular
configuration. However, TZ frequencies exist for certain range of the ratio ω2 /ω1 .
Corollary, noticeable observations on the TZ existence condition can be deduced
from:
(a) Figure 9.3a corresponds to the case (R1 = ∞, R2 = ∞); the TZs are rather
situated under the horizontal axis defined by ωTZ R1 =R2 =∞ = ω1 .
Fig. 9.3 a TZ and b RZ existence surface areas in function of the coupling factor and ω2 /ω1 for
R1 = ∞ and R2 = ∞ [35]
R1 = 0 and R2 = ∞ [35]
(b) Figure 9.4 corresponds to the case (R1 = ∞, R2 = 0); the TZ position should
belong in the half plane above the critical hyperbolic curve ωTZ R1 =∞,R2 =0 =
ω1 ω2 /(ω2 − ω1 ).
(c) Figure 9.5 corresponds to the case (R1 = 0, R2 = ∞), the TZ are situated above
the horizontal axis defined by ωTZ R1 =0,R2 =∞ = ω1 ;
(d) Figure 9.6 corresponds to the case (R1 = 0, R2 = 0); the TZ position should
belong in the half plane above the critical axis ωTZ R1 =0,R2 =0 = ω2 /2.
In all, it is revealed from these graphical analyses that the TZ and RZ cannot exist
for all value of parameters (k, ω2 /ω1 ). In addition to the exploitation of the analytical
formulations, these graphical plots could be used to predict the positions of the RZs
and TZs. More importantly, it enables to predict fast and accurately the influence
of the multiconductor line interbranch coupling in particular during the design of
high-density circuits.
To check the relevance of the previous theoretical concept, comparisons between
the calculated TZs and RZs from the established model and simulations will be
discussed in the next section.
180 B. Ravelo
R1 = ∞ and R2 = 0 [35]
R1 = 0 and R2 = 0 [35]
More practical POCs integrating the design of parametric CPLs are analysed in
order to validate the previous theory. After the description of the designed POC, the
performed simulations were run in the microwave and electronic circuit design and
simulator ADS® from Keysight Technologies® . The comparative results illustrating
the RZ and TZ frequency shifts in function of the CPL coupling coefficient will be
discussed.
9.3.1 POC Description
First, the considered POCs of the CPL are designed in microstrip technology. The
circuit parameter syntheses as even- and odd-impedance characteristics Z e and Z o
were made by using the Hammerstad & Jensen approach.
The CPL physical lengths were arbitrarily assigned corresponding to the stub
quarter wavelength resonance frequencies f 1 = 2 GHz and f 2 = 3 GHz. The POC
circuits were designed and printed on the FR4 substrate having dielectric permittivity
εr = 4.4, loss tangent tan(δ) = 0.02 and the thickness 1.6 mm. The considered sub-
strate was assumed to be Cu-laminated with metal thickness 35 µm. The CPL was
considered with the over length line characteristic impedance Z c = 50 . Therefore,
based on the Hammerstad & Jensen model, the synthesized physical width is equal
to w = 3.02 mm. The CPL lengths d 1 = 21.85 mm and d 2 = 14.53 mm correspond
to the resonances at f 1 and f 2 ‚ respectively. As aforementioned, three different cases
of coupling k = {−10 dB, −6 dB, −3 dB} are investigated. Table 9.3 summarizes
the synthesized geometrical characteristics for the test values of coupling coefficient
k.
For the further understanding on the feasibility of the analytical models established
previously in Sect. 9.2, parametric investigations with the variation of the coupling
level from −10 to −3 dB and the over length stub characteristic impedance will be
discussed in the next paragraph.
Table 9.3 Characteristics of

k (dB) −3 −6 −10
the considered CPL POCs
s (mm) 0.3 0.5 1.0
Z e () 50.44 50.50 50.65
Z o () 49.57 49.50 49.35
182 B. Ravelo
9.3.2 CPL TZ and RZ Predictions with Parametric Analyses
The numerical applications were carried out based on the MATLAB implementation
of the characteristic equations addressed in Tables 9.1 and 9.2. To do this, the calcu-
lated TZs and RZs are plotted in function of the CPL parameters R0 , Z c , f 1 and f 2 .
As practical example, by considering Z c = R0 and f 2 = 1.5f 1 , we can generate the
predictive variation of TZ and RZ versus the coupling level k displayed in Fig. 9.7.
These graphical results indicate how the TZs and RZs of the stub change. Emphat-
ically, due to the crosstalk, they are different to the initial resonance frequencies of
the stubs constituting the CPL. Moreover, the fundamental questions on the influ-
ence of the over length stub ➀–➂ on the CPL TZ and RZ can be answered with the
parametric analyses versus Z c . To do this, numerical implementation of the relations
introduced in Tables 9.1 and 9.2 for the case (R1 = ∞, R2 = ∞) was carried out by
varying the characteristic impedance Z c , from 10 to 100 . The results are depicted
in Fig. 9.8.
Fig. 9.7 Characterized TZs

and RZs versus k for f 2 =
1.5f 1 [35]
Fig. 9.8 Characterized TZs

and RZs of CPL for f 2 =
1.5f 1 , R1 = ∞ and R2 = ∞
[35]
9.3.3 Load Effects Applicative Analysis
To illustrate more explicitly the influence of the coupling on the TZs and RZs,
comparisons between the non-coupled stub resonators and CPL were made. To do
this, different values of the stub lower frequency f 1 were considered from 1 to 5 GHz.
Then, the upper frequency f 2 was swept from f 1 to 5f 1 .
9.3.3.1 Analyses of CPL with Short-Circuited Terminal M 2 : R2 = 0
The simulated transmission and reflection coefficients for the cases (R1 = ∞, R1 =
0) are explored in Figs. 9.9 and 9.10. From these results, comparisons between the
TZs and RZs from ADS simulations and the fundamental formulations provided in
Tables 9.1 and 9.2 were carried out. As expected, a good agreement between the
values of RZs and TZs with relative errors lower than 1% was found. This result
confirms the validity of the proposed theoretical concept to predict the TZ and RZ
positions notably in microstrip technology. It can be understood from Fig. 9.9 (resp.
Fig. 9.10) that the TZ is shifted in left (resp. right) for R1 short-circuited (resp. open-
ended) when the coupling level is higher. However, for both cases, the RZ bandwidth
is shortened when R2 = 0.
9.3.3.2 Analyses of CPL with Open-Ended Terminal M 2 : R2 = ∞
Once again, a good agreement between the positions of the TZs and RZs from
ADS simulations and the analytical formulations established in Tables 9.1 and 9.2
is observed. In this case, the coupling phenomenon tends to increase the bandwidth
between the successive values of TZ (Figs. 9.11 and 9.12).
184 B. Ravelo
Fig. 9.9 Simulated TZs and

RZs of the POC for R1 = 0
and R2 = 0 [35]
Fig. 9.10 Simulated TZs

and RZs of the POC for R1
= ∞ [35]

= ∞ and R2 = ∞ [35]

= 0 and R2 = ∞ [35]
186 B. Ravelo
9.3.3.3 Analysis of TZ and RZ Versus Zc for the Open-Ended

Terminals CPL: R1 = ∞ and R2 = ∞
To complete the previous analyses on the TZ and RZ, multiple cases of the analy-
ses based on the over length stub characteristic impedances were also carried out.
Figure 9.13 introduces the plots of the ADS-simulated CPL transmission and reflec-
tion coefficients by varying Z c from 10 to 100 . It is worth noting that the funda-
mental TZ position increases with Z c . As can be seen in Table 9.4, once again, a good
agreement between the TZ and RZ positions from ADS simulations and the proposed
CPL model was realized. The numerical relative errors are lower than 0.5%.

and RZs of the POC versus
Z c for R1 = R2 = ∞ [35]
Table 9.4 Considered microstrip CPL TZ and RZ versus Z c for f 2 = 1.5f 1 = 3 GHz
Z c () f Tzeros f Rzeros
Model (GHz) ADS (GHz) Model (GHz) ADS (GHz)
10 1.090 1.090 2.080 2.080
30 1.682 1.683 2.380 2.380
50 1.967 1.968 2.535 2.538
70 2.155 2.156 2.630 2.627
90 2.275 2.276 2.695 2.695
An innovative modelling methodology enabling to determine the frequency-

dependent S-parameters of the CPL is established. The fundamental formulations
of the TZ and RZ in function of the CPL coupling coefficient are developed. The
basis of TZ and RZ characteristic equations in function of the structure physical
parameters is determined. More explicit investigation was made based on the TZ and
RZ complete formulations for the different cases of CPL short- and open-ended.
The validity of the established original formulations was verified with POC of
microstrip CPL structures with 2 and 3 GHz stub resonance frequencies. As results,
the frequency-dependent analyses were performed for the coupling factor increased
from −10 to −3 dB. Therefore, an excellent correlation between the established
theory and ADS simulations was verified with various cases of CPL parametric
analyses. The maximal relative error is of about 1%. As expected, all the results
confirm and explain how the CPL resonances frequencies are shifted in function of
the coupling level linked to the crosstalk phenomenon.
The developed theory enables the deep understanding on the mechanism of the
TZ and RZ frequency shifting due to the CPL crosstalk or the interbranch coupling.
Therefore, the established model enables the RF/microwave circuit design engineers
to predict, control and optimize analytically and accurately the CPL TZ and RZ
frequency shifts. The model enables to monitor the CPL responses with significantly
reduced computation speed.
The proposed formulations are useful for multitudes of microwave engineering
applications integrating CLs. More importantly, the established theory can guide
the design engineers to predict fastly and accurately the EM phenomenon as the
interconnect tree interbranch coupling.
In the continuation of this work, the extension of the proposed modelling method
for the multipole microstrip structure with more than two CPL will be investigated.
This more complex case structure modelling can be performed in three different
steps. In first time, the Z-matrix of the m-pole CPL must be analytically established
by taking into account the interbranch coupling. In second time, the input impedance
of the equivalent topology of the CPL including the connected port can be extracted.
Last, the RZ and TZ can be expressed by assuming the input impedance in short- or
open-circuit configurations. The application for the microstrip structure with three-
and four-branch CPLs is in progress.
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Chapter 10
Analytical Modelling of Interbranch
Coupling Effect on Coupled Microstrip
Tree PCB Interconnects
Blaise Ravelo
10.1 Introduction
The EMC, EMI, SI and PI phenomena become one of the most crucial effects when
the operating frequency, processing speed and integration density of digital electronic
systems (DRAM, MPU, DIMM packages …) are increased [1–3]. Design and fabri-
cation engineers have to respect required compliances notably on the interconnection
networks as memory buses (DDR4, GDDR5, XDR, IO2 and HBM), front-side bus
(quick path interconnect and hypertransport), cable (USB, HADMI and FireWire Cat
X) and Ethernet (XAUI, XFI, CEI-6GLR and SONNET) [3]. Figure 10.1 illustrated
an example of complex signal distribution interconnect tree [4]. Such a structure in the
modern high-speed memory system is challenging on the SPI and EMC constraints
effects on interconnect lines (ILs) as channel attenuation, crosstalk, reflection, delay
and distortion [5, 6]. So, prediction methods were forwarded based on various IL
model-based approaches as RC- and RLC-lines [7, 8].
More generally, different models of interconnect tree topologies were devel-
oped [9–12]. But those models are not valid for structures presenting asymmetrical
behaviours as comb tree depicted in Fig. 10.2. So, analytical model including the
unbalanced interconnect tree was established recently in [13]. In first step, this analyt-
ical approach was initiated by assuming that the IL as equivalent to its RLCG model
by taking into account the frequency variation of per unit length parameters (Ru (f ),
L u (f ), C u (f ) and Gu (f )). In the second step, the model was fundamentally imple-
mented via the circuit equivalent approach single input multiple output (SIMO) to
single input single output (SISO) [13].
The analytical operations were handled with ABCD-to-Z matrix to generate the
IL impedance matrix, Z-to-Y matrix to extract the equivalent parallel lines and Y-to-
ABCD matrix transforms (to express the equivalent transfer parameters) proposed in
B. Ravelo (B)

192 B. Ravelo
Fig. 10.1 Electronic boards with complex interconnect tree network [2]
Fig. 10.2 Example of 8:1 comb or asymmetrical interconnect tree
[14, 15]. Then, the output responses across the different path from the single input N in
to any output N m (m = {1, …, 8}) were mathematically formulated via the voltage
transfer functions:
Vm
Hm = . (10.1)
Vin
At this stage, this modelling method was applied to perfectly isolated asymmet-
rical tree structure. Nevertheless, in the context of system as high-density PCBs,
10 Analytical Modelling of Interbranch Coupling Effect on Coupled … 193
the interconnections can be significantly localized and create unintentionally EM

coupling or crosstalk effects [16, 17].
This explains why in the present chapter, a modelling methodology enabling to
predict crosstalk on asymmetrical tree is established. The model developed herein is
the synergy of tree topology presented in [13] and the coupling model in [18].
10.2 Modelling of Parallel Type Coupled Line Structure
10.2.1 Topological Approach for Circuit Diagram Reduction
Figure 10.3a represents the circuit configuration of the 2:1 asymmetrical tree. The
single input with internal impedance Z s is excited by vin . The asymmetrical tree
outputs are loaded by impedances Z L1 and Z L2 , and the branches are essentially
comprised of pieces of input lines TL0 (connected between nodes N in and N 0 ) and
output lines TL1 (between N 0 and output node N 1 ) in parallel output lines TL21
cascaded with TL22 (between N 0 and N 2 ). We will manage a comparison between
this isolated circuit tree with the tree introduced in Fig. 10.3b in the presence of
neighbouring line TLc placed in proximity of TL21 . So, we propose to replace TL21
by piece of lines TL21 , TL21 and TL21 cascaded by choosing the length of TL21
as same as TLc here assigned as d c .
Fig. 10.3 a 2:1 comb tree (a)

topology and b comb tree Zs TL0 N0
topology including coupling Nin TL21
line TLc2 V in TL1 TL22
N1 N2
ZL1 V 1 ZL2 V2
(b)
ZL3 ZL4
TLc
Zs TL0 N0
Nin TL21' TL21" TL21'"
V in TL1 TL22
dc
N1 N2
ZL1 V1 ZL2 V2
194 B. Ravelo
10.2.2 SIMO Modelling
As described in [18], the overall coupled line impedance and admittance matrices
are denoted:
[Z ] = [R] + jω[L], (10.2)
and
[Y ] = [G] + jω[C], (10.3)
with j is the complex number and ω the radian frequency. The even and odd mode
impedances and electrical angles of coupled branches TL21 − TLc are denoted (Z e ,
Z o ) and
θe = γe · dc , (10.4)
θo = γo · dc . (10.5)
The ABC matrix [TN2 N0 ] of equivalent to N 0 N 2 is determined by the relation:

TN2 N0 = T (TL21 ) · T (TL21 ) · T (TL
21 ) · [T (TL22 )], (10.6)
where the elementary line ABCD matrices are written as:

cos h(θm ) Z cm · sin h(θm )
[T (TLm )] = sin h(θm ) . (10.7)
Zc
cos h(θm )
m m=21,22
While the ABCD matrix of the coupled lines (TL21 − TLc ≡ TL21c ) is analytically
defined as:

T (TL21c ) = eig[Z · Y ] · [Tx ] · eig[Z · Y ]−1 k,l={1,2} , (10.8)
whose four elements of matrix [Tx ] are

⎧

⎪
⎪ cos h(θe ) 0
⎪
⎪ [T ](1, 1) = [T ](2, 2) =
⎪
⎪
x x
0 cos h(θo )
⎪
⎨

Z e sin h(θe ) 0
[Tx ](1, 2) = (10.9)
⎪
⎪ 0 Z o × sinh(θo )
⎪
⎪

⎪
⎪ [Tx ](2, 1) = sin h(θe )/Z e
⎪
⎩
0
0 sin h(θo )/Z o
Then, we apply SIMO-to-SISO transform for the transfer function extraction

along electrical paths N in N m (m = {1, 2}).
10.2.3 T-Matrix Modelling Based on SIMO-SISO Transform
Figures 10.4 and 10.5 represent the SISO equivalent circuits of 1:2 tree sketched in
Fig. 10.3, respectively, for the electrical paths N in N 1 and N in N 2 .
We can see that the reduced circuits are in presence of parallel impedances Z in,m
(m = 1, 2) expressed with the classical relation between impedance and ABCD
matrices. After integration of the parallel impedances including the coupling effects,
the asymmetrical tree transfer functions are mathematically established for m = {1,
2}:
1
Hm = . (10.10)
[T (TLNm Nin )]1,1
By combining all the previous analytical elements of each piece of lines defined
before, we have the associated ABCD matrix for each output branches written as:
Fig. 10.4 Equivalent SISO (a)

circuits for extracting the Zs TL0 N0 Zin2
output V 1
Nin
V in TL1
N1
ZL1 V1
(b)
Zs TL0 N0 Zin2'
Nin
V in TL1
N1
ZL1 V1
196 B. Ravelo
Fig. 10.5 Equivalent SISO (a)

circuits for extracting the Zs TL0 N0
output V 2
Nin TL21
V in Zin1 TL22
N2
ZL2 V2
(b) TL0
Zs N0
Nin TL21c
V in Zin1 TL22
N2
ZL2 V2

1 Zs 1 1 1 1
T (TL N1 Nin ) = · [T (TL0 )] · · [T (TL1 )] · .
1 0 1/Z in2 0 1/Z L1 0
(10.11)
⎧

⎫
⎪
⎪ 1 Zs 1 1
⎪
⎪
⎨ 1 0 · [T (TL0 )] · 1/Z in1 0 · T (TL21 ) · ⎬
T (TL N2 Nin ) =
. (10.12)
⎪
⎪ 1 1 ⎪
⎪
⎩ T (TL21c ) · T (TL21 ) · ⎭
1/Z L2 0
10.2.4 Illustrative Applications
A 1:2 microstrip interconnect tree was considered as numerical proof of con-

cept examined in this section. Then, frequency- and time-domain analyses will be
managed.
Figure 10.6 displays the schematic layout illustrating the configuration of the 1:2
Fig. 10.6 Layout schematic

of 1:2 asymmetrical ZL3 ZL4
interconnect tree including
the neighbouring d1 d2
perturbation line considered
d3
w2
for the numerical analyses:
s
d 1 = 2 mm, d 2 = 4.5 mm, d 3 Zs
w1
= 1.5 mm, d 4 = 1 mm, d 5 =
Vin(t)
d6
6 mm, d 6 = 1.5 mm, d 7 =
2 mm, w1 = 0.3 mm, w2 =
d7
d4 d5
0.1 mm and s = 0.1 mm
ZL1 V1(t) V2(t) ZL2
asymmetrical interconnect tree considered for the numerical application. This struc-
ture is comprised of the microstrip interconnect tree driven by the numerical source
vin with internal impedance Z s = 25 and loaded by capacitors Z L1 = Z L2 = 10 pF.
The electrical paths N in N 1 and N in N 2 are set with physical lengths, respectively,
2.5 and 9 mm. The perturbation line presents 7.5 mm physical length and loaded
by Z L3 = 25 and Z L4 = 10 pF. Comparisons between the responses of the 2:1
tree without and with the perturbation coupling lines were performed by plotting the
outputs (v1 , v2 ) and (vc1 , vc2 ), respectively.
10.2.4.2 Substrate Parameter Frequency-Dependent Model
The model presented in this chapter can be advantageously extended to structure

including broadband frequency influences. As application tests, the interconnect tree
circuit substrate was defined with Svesson-Djordjevic model proposed in [19, 20].
In other word, the relative permittivity was expressed including frequency variation
considered. For that, the substrate permittivity was formulated as:

2π f L + jω
εrf ( jω) = εr + a · ln , (10.13)
2π f H + jω
with:
− jεr tan(δ)
a= , (10.14)
ln ffHL + j f0
+ j f0
εr = 4, tan(δ) = 0.02, frequency f 0 = 1.5 GHz at which εr and tan(δ) are

specified, low roll-off frequency f L = 0.1 GHz and high roll-off frequency f H =
10 GHz.
198 B. Ravelo
Figure 10.7 display the frequency responses of the structure presented in Fig. 10.6.
By using expressions (10.9), (10.10) and (10.12),
V1,2 ( jω)
H1,2 ( jω) = , (10.15)
Vm ( jω)
and:
Vc1,2 ( jω)
Hc1,2 ( jω) = , (10.16)
Vin ( jω)
(a)
H dB H cdB φ φc
70 100
40 -100
H 1 (f) (dB)
φ (H 1 ) (∞)
10 -300
-20 -500
-50 -700
0 2 4 6 8 10
Frequency (GHz)
(b) H dB H cdB φ φc
70 0
35 -200
φ (H 2 ) (∞)
H 2 (f) (dB)
0 -400
-35 -200
-70 -200
0 2 4 6 8 10
Frequency (GHz)
Fig. 10.7 Frequency responses of the 2:1 asymmetrical tree presented in Fig. 10.6 without (solid
lines) and with (dashed lines) coupling [21]
represent the transfer function corresponding to the electrical path N in N 1,2 without,
respectively, with the perturbation line. A significant resonance effect is occurred at
about 0.61 GHz along the path N in N 1 . This is due to the stub effect from the other
branch of the tree. As we can see, due to the crosstalk between the coupled branches
of the tree, the coupled responses are influenced notably above 5 GHz.
One emphasizes that the CPU time of the whole method implemented into MAT-
LAB runs with PC equipped by Windows 7 having Intel® Core™ i5-2467M CPU
@1.6 GHz 4 Go RAM was of about hundred milliseconds.
During the numerical test for this time-domain investigation, a high-speed mixed
signal represented by eight bits input data “01001000” was assumed as input. This
data was assigned as trapezoidal signal with 0.5 Gbps rate and 150 ps rise-/fall-times.
Figure 10.8 displays the computed results. The input is traced in solid bold blue line
and the asymmetrical tree outputs without (in solid red lines) and with (in dashed
green lines) the perturbation lines.
These results highlight and enable to predict rapidly and easily the influence of the
asymmetrical interconnect distribution tree. Emphatically, due to the asymmetrical
behaviours of the two input branches, we can see that the outputs are completely
different. In all cases, it can be underlined that the data SI was significantly degraded
with considerable distortion. Moreover, the propagation delays are of about 0.22 ns
for the electrical path N in N 1 and 0.5 ns for the path N in N 2 . A reflection effect is also
observed on the path N in N 1 which is related due to the resonance effect occurred in
Fig. 10.8a.
In inference of this study, we can emphasize that:
• The output signal shapes are rather preserved because the bandwidth of the input
data is quite lower than 6 GHz.
• The time-delay between the two responses is lower than 200 ps.
• The slight variation of the output transient voltage amplitudes of about 10% was
found when placing the perturbation at 100 µm of the tree.
200 B. Ravelo
(a)
1.0
V in
V1
V c1
Voltage (V)
0.5
0.0
0 4 8 12 16
Time (ns)
(b)
1.0 V in
V2
V c2
Voltage (V)
0.5
0.0
0
0 4 8 12 16
Time (ns)
Fig. 10.8 Eight bits data responses of the 2:1 asymmetrical tree presented in Fig. 10.6 without
(solid lines) and with (dashed lines) coupling [21]
10.2.4.5 Conclusion
Relevant investigation on high-speed SI applied to asymmetrical tree distribution per-

turbed by a coupled piece of line was performed. Analytical methodology describing
the mechanism of the used computation algorithm was established by considering
an example 1:2 asymmetrical tree topology. The analytical behavioural model of the
transfer function was conjectured via ABCD-, Z- and Y-matrices handling. It is impor-
tant to note that the model can be extended to broadband model of relative permittivity
by taking into account the dispersion effect as proposed by Svesson-Djordjevic in
[19, 20].
The numerical application via MATLAB programming enables to evaluate the
efficiency of the behavioural model. Then, proof of concept based on a microstrip
asymmetrical tree with neighbouring line was modelled and analyzed both in
frequency- and time-domains. It was found that the asymmetrical microstrip tree
degrades significantly the behaviour of the tested signal consisted of eight bits input
data with 0.5 Gbps rate. The model is beneficial in terms of flexibility, simplicity
and computation speed. Meanwhile, the present model is helpful for the design and
manufacture engineers for assessing the degradation of the sharing high-speed signal
in asymmetrical tree.
In the continuation of this work, I am looking out on the application of the
behavioural asymmetrical model proposed hereby for the miniaturized microelec-
tronic interconnect systems packaging structures. The future study will be based on
the SI and EMC/EMI modelling principle by taking into account the undesirable EM
coupling influences. The prediction of the high-density interconnect effect allows to
optimize the packaging structures and also probably establishes a post-processing
technique for the signal degradation compensation.
Furthermore, we can also foresee to extend the analysis examined in this chapter
for generalized principle of integrated circuit. The particularity of the integrated inter-
connects as 3D TSV lies on the influence of the interbranch inductive and capacitive
couplings.
10.3 Modelling of Interbranch Coupled Branch

Transmission Type Structure
For this reason, the unbalanced tree interconnects modelling with interbranch EM
coupling effect is developed in this section [22]. Section 10.3.1 describes the compu-
tational theory of interbranch coupled unbalanced single-input double-output (1:2)
tree. Section 10.3.2 is the unbalanced 1:2 tree input impedance and the VTF model
validations with ADS® simulations. Section 10.3.3 is the conclusion.
10.3.1 Theoretical Description
10.3.1.1 Topological Analysis
The proposed computational method is aimed to the determination of the input

impedance and the unbalanced tree interconnect VTFs. In difference with the exist-
ing models, the proposed one integrates the coupling phenomenon interbranch of
the unbalanced tree interconnects. In more concrete view, the tree under study is
composed of elementary TLs configured as depicted in Fig. 10.9.
The electrical network is constituted by three branches TL Ma M0 , TL M0 Mb and
TL M0 Mc . The characteristic impedances and physical lengths are, respectively, (Z a ,
d a ), (Z b , d b ) and (Z c , d c ) by supposing that d b > d c . Moreover, the output branches
TL M0 Mb and TL M0 Mc are implicit with EM coupling phenomenon.
202 B. Ravelo
Fig. 10.9 Unbalanced tree

interconnect structure [22]
10.3.1.2 Equivalent Circuit Description
The posed problem [22] can be traduced by the unbalanced 1:2 tree interconnect
modelling. It consists in the transformation of the initial tree network introduced in
Fig. 10.9 into the systemic model depicted in Fig. 10.10. The voltages across the
nodes M a , M b and M c are, respectively, denoted Va = VMa , Vb = VMb and Vc = VMc
(Fig. 10.11).
Fig. 10.10 VTF equivalent

circuit systemic view: a H a ,
b H b and c input impedance
Z in [22]
Fig. 10.11 Equivalent

circuit diagram of the
unbalanced tree interconnect
including the CTL Z-matrix
[22]
The system VTFs and overall input impedance are defined by:
VMb ( jω) Vb ( jω)

Hb ( jω) = = , (10.17)
VMa ( jω) Va ( jω)
VMc ( jω) Vc ( jω)
Hc ( jω) = = , (10.18)
VMa ( jω) Va ( jω)
Va ( jω)
Z in ( jω) = , (10.19)
Ia ( jω)
with ω is the angular frequency. The equivalent circuit diagram of the unbalanced
1:2 tree can be elaborated by considering the impedance or Z-matrix of the coupled
TL (CTL). The modelling method can be established from the equivalent circuit dia-
gram presented in Fig. 10.12. The unbalanced tree structure can be transformed as an
electrical network mainly constituted by elementary TLs. We assume that the input
is connected with the TL TL Ma M0 characterized by TL(Z a (jω), γ a (jω)). TL M0 Mb and
TL M0 Mc , respectively, characterized by TL(Z b (jω), γ b (jω)) and TL(Z c (jω), γ c (jω))
constitute the output branches. With ξ = {a, b, c}, Z ξ (jω) is the characteristic
impedance and
γξ ( jω) = αξ (ω) + jβξ (ω), (10.20)
is the propagation constant. The parameter ω is the angular frequency, α ξ is the

attenuation constant, β ξ phase constant associated with the electrical length:
θξ = βξ dξ . (10.21)
Fig. 10.12 Reduced

two-port equivalent network
of the circuit introduced in
Fig. 10.10 [22]
204 B. Ravelo
These output networks can be represented by the coupled TL matrix [Z]CTL and
the output TL TL(Z b (jω), γ (jω)) associated to the electrical length θ . This CTL
structure is assumed as an octopole with Ports ➊ and ➋ interconnected, and Ports ➌
and ➍ are connected to output loads Rb and Rc . Each access port m (m = {1, 2, 3,
4}) is traversed by branch currents I m .
Let us denote C the coupling coefficient between the coupled lines connecting
Ports ➊ and ➋ and Ports ➌ and ➍, and Z 0 (jω) is the characteristic impedance of
each elementary line. According to the TL theory, the even- and odd-characteristic
impedances Z e and Z o of the associated coupled lines constituting the unbalanced 1:2
tree is defined in (9.33). The lengths of the input and output TLs can be characterized
by the resonance angular frequencies ωξ which are linked to the physical length by
the relation:
2π v
dξ = , (10.22)
ωξ
with ξ = {a, b, c} and the wave speed v. Moreover, the physical length difference:
d = db − dc , (10.23)
between the TL M0 Mb and TL M0 Mc corresponding to the quarter wavelengths λb /4

and λc /4 is also equivalent to the electrical length analogue to the overlength TL
connecting Port ➌ and node M b . The equivalent electrical length is associated to d.
It is analytically equal to:
θ = βb d = βb (db − dc ). (10.24)
It implies the relation:
π ω(ωc − ωb )
θ = . (10.25)
2ωb · ωc
The associated input impedance, which is spontaneously related to the TL

characteristic impedance Z 0 (jω), is given by:
Z 0 ( jω)
Z ( jω) = . (10.26)
tan h γ ( jω)
10.3.1.4 Z-Matrix of the Coupled Output Branches and Access Line

ABCD or Transfer Matrices
The adopted methodology to solve the posed problem is fundamentally based on the
calculation of the branch currents. The Z-matrix of the tree coupled branches and
the access line ABCD matrices must be expressed in function of the interconnect
structure parameters. The four-port CTL structure constituting the unbalanced 1:2
tree can be represented by the equivalent 4 × 4 Z-matrix analytically expressed as:
⎡ ⎤
Z 11 Z 12 Z 13 Z 14
⎢ Z 21 Z 22 Z 23 Z 24 ⎥
[Z ] = ⎢
⎣ Z 31
⎥ (10.27)
Z 32 Z 33 Z 34 ⎦
Z 41 Z 42 Z 43 Z 44
By denoting α the attenuation constant and d the physical length, based on the
microwave theory and due to the symmetry, the matrix elements are defined as:
⎧ Z e +Z o
⎪
⎪ Z 11 = Z 22 = Z 33 = Z 44 =
⎪
⎨Z
2 tan h(αd+ jθ)
Z e −Z o
12 = Z 21 = Z 34 = Z 43 = 2 tan h(αd+ jθ)
Z e −Z o , (10.28)
⎪
⎪ Z = Z 31 = Z 24 = Z 42 =
⎪
⎩
13 2 sin h(αd+ jθ)
Z e +Z o
Z 14 = Z 41 = Z 23 = Z 32 = 2 sin h(αd+ jθ)
with
πω
θ= . (10.29)
2ωc
Furthermore, the ABCD matrices analytically equivalent to the TL connecting the

node M a -Port ➊ and Port ➌-node M b are, respectively, defined as [17, 18]:

Aa Ba cos h(γa ) Z a sin h(γa )
[Ta ] = = , (10.30)
C a Da sin h(γa )/Z a cos h(γa )

Ab Bb cos h(γ ) Z b0 sin h(γ )
[Tb ] = = . (10.31)
C b Db sin h(γ )/Z b0 cos h(γ )
The abstracted topology equivalent to the unbalanced 1:2 tree structure under
study can be represented as highlighted in Fig. 10.12. This topology enables to
realize the theorization of the problem with the analogue mathematical concept. The
branch currents [I1 , I2 , I3 , I4 , Ia , Ib ] are assumed as the unknown variables which
must be expressed in function of the input excitation source V a . Meanwhile, the
problem solution can be reformulated as the calculation of the tree branch currents
I a , I a , I 1 , I 2 , I 3 , I 4 and I b . The algebraic solution can be determined from linear
equations derived via the combination of the impedance and ABCD matrices in
(10.29), (10.31) and (10.32), and the Ohm’s laws applied to the output loads Z b and
Z c:
Vb = −Z b · Ib , (10.32)
206 B. Ravelo
V4 = −Z c · I4 . (10.33)
Moreover, at the junction node M 0 , we have the relation:
Ia = I1 + I2 , (10.34)
and
V1 = V2 . (10.35)
By taking this condition into account, the following synthetic equation system can
be deduced from the access line ABCD matrices associated to (10.30) and (10.31):
⎧
⎪
⎪ Va = Aa V1 + Ba (I1 + I2 )
⎨
Ia = Ca V1 + Da (I1 + I2 )
. (10.36)
⎪ V3 = Ab Vb − Bb Ib = −(Ab Z b + Bb )Ib
⎪
⎩
I3 = Cb Vb − Db Ib = −(Cb Z b + Db )Ib
The voltage and current vectors:
[V ] = [V1 V2 V3 V4 ], (10.37)
and
[I ] = [I1 I2 I3 I4 ], (10.38)
corresponding to the configuration of the coupled lines presented in the circuit dia-
gram of Fig. 10.12 are linked to the Z-matrix defined in (10.27) by the equation
system:
⎧
⎪
⎪ V1 = Z 11 I1 + Z 12 I2 + Z 13 I3 + Z 14 I4
⎨
V1 = Z 21 I1 + Z 22 I2 + Z 23 I3 + Z 24 I4
[V ] = [Z ]CPTL [I ] ⇔ . (10.39)
⎪
⎪ V = Z 31 I1 + Z 32 I2 + Z 33 I3 + Z 34 I4
⎩ 3
V4 = Z 41 I1 + Z 42 I2 + Z 43 I3 + Z 44 I4
10.3.1.5 VTF and Input Impedances of the Tree Input-Output

Electrical Path
The combination of (10.36) and (10.39) implies the following synthetic characteristic
equation system of the posed problem mathematical solution knowing the excitation
source V a . The main access branch currents I a and I b can be yielded from the solutions
via the ABCD matrices of TLs TL Ma M0 and TLPort➌- Mb in (10.31). Consequently, the
unbalanced 1:2 tree characteristic matrix derived from (10.30) and (10.31) can be
written as:
⎧
⎪
⎪ Z 11 + ABaa I1 + Z 12 + ABaa I2 + Z 13 I3 + Z 14 I4 = VAaa
⎪
⎪
⎪
⎨ Z + Ba I + Z + Ba I + Z I + Z I = Va
21 1 22 2 23 3 24 4 Aa ,
Aa Aa (10.40)
⎪
⎪ +B
⎪
⎪ Z I
31 1 + Z I
32 2 + Z 33 − A b Z b
Cb Z b +Db
b
I 3 + Z 34 4I = 0
⎪
⎩
Z 41 I1 + Z 42 I2 + Z 43 I3 + (Z 44 + Z c )I4 = 0

Ia = Ca Va +(Da AAa a−Ba )(I1 +I2 )
, (10.41)
Ib = Cb Z−Ib +D
3
⎡ Va ⎤ ⎡ ⎤
b
Z 11 + A Ba
Z 12 + A Ba
Z 13 Z 14 0 0 ⎡ ⎤
I1
⎢ Vaa ⎥ ⎢ ⎥
A a a
⎢ Ba
⎢ A ⎥ ⎢ Z 21 + Aa Z 22 + Aaa
B
Z 23 Z 24 0 0 ⎥ ⎢I ⎥
⎢ a ⎥ ⎥ ⎢ 2⎥
⎢ 0 ⎥ ⎢ ⎢ Z Z Z −
Ab Z b +Bb
Z 34 0 0
⎥ ⎢ ⎥
⎥ ⎢ I3 ⎥
⎢ ⎥ 31 32 33 Cb Z b +Db
⎢ 0 ⎥=⎢ ⎥ · ⎢ ⎥.
⎢ ⎥ ⎢ Z Z Z Z + Zc 0 0 ⎥ ⎢ I4 ⎥
⎢ Ca ⎥ ⎢ B 41 42 43 44 ⎥ ⎢ ⎥
⎣ A Va ⎦ ⎢
⎣ a −D
a
Ba
− D a 0 0 1 0
⎥ ⎣ Ia ⎦
⎦
a Aa Aa
0 0 0 1 0 0 C b Z b + Db Ib
(10.42)
By taking:
x = tan h(αd + jθ ), (10.43)
the VTF through the 1:2 tree electrical path M a M b can be expressed as:
√
Z b ( jω)Ib ( jω) 2Z e Z b (Z c + x Z o ) 1 − x 2
Hb ( jω) = = , (10.44)
−Va ( jω) χ2b x 2 + χ1b x + χ0b
where:
⎧

⎪
⎪ Ba ((Bb + Aa Z b ) − (Db + Cb Z b )Z c )
⎪
⎪ χ2 = 2Z o
b
⎪
⎪ −Aa (Db + Cb Z b )Z e2
⎪
⎪ ⎧ ⎫
⎪
⎪ ⎪ Aa (Aa Z b + Bb − (Db + Cb Z b )Z c )Z e2 ⎪
⎪
⎨ ⎪
⎨ ⎪
⎬
+4Ba (Bb + Aa Z b )Z c
χ1 =
b
. (10.45)
⎪
⎪ ⎪
⎪ Aa (4 Aa Z b + Bb ) − (4Ba (Db + Cb Z b ) ⎪
⎪
⎪
⎪ ⎩+ Zo Ze ⎭
⎪
⎪ +Aa Db Z c + Aa Cb Z b Z c )
⎪
⎪

⎪
⎪ Ba (Bb + Aa Z b ) + Z c (Aa Bb − Ba Db
⎪
⎩ χ0b = 2Z e Ba
+(Aa2 − Ba Cb )Z b ))
Similarly, the VTF equivalent to the electrical path M a M c can be written as:
208 B. Ravelo
√
Z c ( jω)I4 ( jω) 2Z c Z e 1 − x 2 [Z o x(Cb Z b + Db ) + Bb + Aa Z b ]
Hc ( jω) = = .
−Va ( jω) χ2b x 2 + χ1b x + χ0b
(10.46)
The overall structure input impedance can be extracted from (10.17).
10.3.2 Illustrative Applications
This section is focused on the validations of the developed unbalanced 1:2 model.
Two POCs of unbalanced 1:2 trees are designed by considering the aspects with
and without interbranch coupled branches. The POC modelled computed results are
compared with simulations run in the ADS® environment of the electronic circuit
designer and simulator. AC simulations are considered by assigning the voltage
excitation source V a with 201 frequency samples from 0.1 to 2 GHz.
10.3.2.1 Description of the POC
The POC represented in 3D view in Figs. 10.13 is microstrip passive distributed

circuits which are interconnect passive structures of unbalanced 1:2 tree networks.
The arbitrarily chosen structures with and without output interbranch coupling are,
respectively, shown in Fig. 10.13a, b.
These microstrip structures were printed on the dielectric substrate Kapton® poly-
imide film provided by DuPont® with characteristics relative to permittivity εr = 3.3,
loss tangent tan(δ) = 0.008, thickness h = 125 µm, conductivity σ = 58 MS/m and
thickness t = 17 µm. Both sides of the film were laminated with copper layer, form-
ing the ground plane for the unbalanced 1:2 tree interconnects circuit and the layer
on which the circuit was patterned, respectively.
Knowing the POC characteristics, the demonstrator circuit was designed with ele-
mentary lines presenting arbitrary physical parameters. The POCs with and without
interbranch coupling present physical sizes are, respectively, 28 mm × 75 mm and
122 mm × 29 mm. The POC structures are excited by the AC voltage source V a and
loaded by Z b and Z c connected at the output nodes M b and M c . Acting as an AC or
frequency analysis, the input voltage source was fixed equal to constant V a = 1 V
for the discrete frequency f varied from 0.1-to-2 GHz with 201 frequency samples.
10.3.2.2 POC Circuit Physical, Electrical and EM Characteristics
The POC was designed with arbitrary parameters which prove the influence of the
interbranch coupling on the two VTFs. The microstrip-line effective permittivity and
Fig. 10.13 3D design of the POC asymmetrical 1:2-tree microstrip structure a with and b without
output interbranch coupling [22]
characteristic impedances were extracted based on the microstrip TL theory. The cou-
pled branch parameters (C = −10 dB, Z e = 69.37 , Z o = 36.04 , s = 40 µm)
were extracted. The modelling and simulations were performed with these differ-
ent parameters. However, the entire proposed model-computed results were realized
with MATLAB programming. During the calculations, the ideal parameters were
supposed independent of the frequency, and the TL losses were neglected. The equiv-
alent model was developed by assuming the TL Ma M0 (wa = 227 µm, d a = 23.7 mm,
Z a = 50 ) with the frequency quarter wavelength f a = 2 GHz, and the coupled
lines TL M0 Mb (wb = 223 µm, d b = 73 mm, Z b = 56.5 ) and TL M0 Mc (wc = 223 µm,
d c = 49 mm, Z c = 56.5 ) are defined with the frequency quarter wavelengths
f b = 1 GHz and f = 2 GHz. The minimal physical width of the microstrip struc-
ture which can be fabricated with the equipment available in our laboratory is limited
to 300 µm. For this reason, the POC fabricated prototypes are not available for the
present study. The branch currents were computed.
210 B. Ravelo
10.3.2.3 Applications with Resistive Loaded Unbalanced Tree
In this case, the impedance loads are assigned as lumped resistors with nominal values
Z b = 50 and Z c = 100 . The VTF magnitudes |H a | and |H b | are, respectively,
displayed in Fig. 10.14a, b. These results illustrate the relevance and effectiveness of
the developed model for the interbranch coupling phenomenon prediction. Without
coupling, more accentuated resonance effects are observed at the terminal M a and
M b.
The interbranch coupling effects can be predicted by the proposed computation
method in good agreement with the simulations from very low frequencies to 2 GHz.
The same remark is found with the input impedance magnitude |Z in | of the overall
structure plotted in Fig. 10.15. The VTF model accuracy presents error absolute max-
imal value of about 1 dB. The highest absolute differences between the simulations
and modelled results are reasonably appeared around the resonance frequencies. The
main difference between the model and the reference simulations is caused by the
characteristics of the elementary TLs constituting the unbalanced tree structure. Fur-
thermore, these discrepancies increase at higher frequencies. Such effects are mainly
Fig. 10.14 Comparison of modelled and simulated resistive loaded tree interconnect VTF
magnitudes: a |H b | and b |H c | [22]

the modelled and simulated
resistive loaded tree
interconnect input
impedance magnitude |Z in |
[22]
due to the influence of the frequency on the TL EM and electrical parameters as the
skin depth effect and the substrate dispersion.
These computation errors are also added to the numerical computation inaccu-
racies. To generate the modelled computed results with the assigned samples, the
computation speed was less than one millisecond by using a PC equipped with
a single-core processor Intel® CoreTM i3-3120M CPU @ 2.50 GHz and 8 GByte
physical RAM with 64-bits Windows 7.
10.3.2.4 Applications with Capacitive Loaded Unbalanced Tree
In this case, the impedance loads are constituted by arbitrary chosen lumped resistor
Z b = 50 and capacitor Z c = 1 pF. The frequency simulations were carried out with
the unbalanced 1:2 tree structure by sweeping the AC source V a frequency. Then,
comparison between the simulations and computed models is realized. The obtained
VTF magnitudes |H a | and |H b | are, respectively, displayed in Fig. 10.16a, b. Once
again, without coupling, the resonance effects are occurred slightly at lower frequen-
cies. The simulated and modelled VTFs are in good agreement for the different types
of output loads Z b and Z c . A notable well-correlated behaviour of the VTFs versus
frequency is observed with simulations and the developed modelling methods in
the considered broadband frequency band. The comparison between the associated
input impedances magnitude |Z in | can be seen in Fig. 10.17. Similar to the previous
case, the interbranch coupling influences obviously, the unbalanced tree frequency
responses notably when the frequency is higher than 0.5 GHz. Despite the coher-
ent behaviour between the modelled and simulated results, numerical discrepancies
appear around the resonance frequency situated between 0.5 and 1 GHz.
This noteworthy deviation is mainly due to the approximation of the TL electrical
and EM characteristics which are assumed to be independent to the frequency during
the computation process.
212 B. Ravelo
Fig. 10.16 Comparison of the modelled and simulated capacitive loaded tree interconnect VTF
magnitudes: a |H b | and b |H c | [22]

the modelled and simulated
capacitive loaded tree
interconnect input
impedance magnitude |Z in |
[22]
10.3.3 Conclusion
A circuit theory on 1:2 tree interconnects with interbranch coupling is established.

The model is built with the combination of the coupled lines octopole impedance
matrix and the access line ABCD matrices. The equivalent topology enables to tra-
duce the system into the problem mathematical abstraction. The VTF of the tree
input-output electrical path and the overall circuit input impedance are established.
Two POCs constituted by unbalanced 1:2 tree with and without interbranch cou-
pling are designed. The modelled and simulated tree input-output VTFs and also the
input impedance are compared via AC simulations from 0.1-to-2 GHz. Good agree-
ments between simulations and the models are observed. The proposed computation
method is more efficient in terms of precision with the EM coupling influence com-
pared to the methods available in [23–25] which are dedicated to the linear tree VTF
modelling.
Analytical methodologies to model the asymmetric SIMO trees with interbranch

coupling effect are developed. The modelling concept is based on the consideration
of typical microstrip line with the coupling coefficient. The developed method is
started with the identification of the elementary blocks constituting the tree equivalent
circuit. The block elements integrating the coupling effect are represented with its
equivalent Z-matrix. Then, in function of the tree configuration (cascade, parallel,
…), the different blocks are combined in order to determine the global VTF between
the main input and the considered output node.
References
1. International Technology Roadmap for Semiconductors Update Overview, 2012. [Online].

2. W. Beyene, Design and analysis of high-speed links, in Tutorial, Proceedings of 17th IEEE
Workshop on Signal and Power Integrity, Paris, France, 12–15 May 2013
3. M. Cases, Main memory design fro SPI engineers, in Tutorial, Proceedings of 17th IEEE
Workshop on Signal and Power Integrity (SPI), Paris, France, 12–15 May 2013
S/390 G5 and G6 custom microprocessors. IBM J. Res. Dev. 43(5/6), 681–706 (1999)
5. Q. Zhu, W.W.M. Dai, High-speed clock network sizing optimization based on distributed RC
and lossy RLC interconnect models. IEEE Trans. CAD Integr. Circuits Syst. 15(9):1106–1118
(1996)
6. A. Deutsch, G.V. Kopcsay, P. Restle, G. Katopis, W.D. Becker, H. Smith, P.W. Coteus, C.W.
Surovic, B.J. Rubin, R.P. Dunne, T. Gallo, K.A. Jenkins, L.M. Terman, R.H. Dennard, G.A. Sai-
Halasz, D.R. Knebel, When are transmission-line effects important for on-chip interconnection.
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280–289 (2009)
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interconnects for the high-speed SI applications, in Proceedings of 10th International Sympo-
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2011
9. B. Ravelo, A.K. Jastrzebski, Modelling of symmetrical distributed clock RC H-tree, in Pro-
ceedings of 2012 International Symposium on Electromagnetic Compatibility (EMC Europe),
Rome, Italy, pp. 1–6, 17–21 Sept 2012
10. P.J. Restle, A. Deutsch, Designing the best clock distribution network, in Keynote, Digest of
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1998
Trans. CAS I 52(2), 313–322 (2010)
13. T. Eudes, B. Ravelo, T. Lacrevaz, B. Fléchet, Distributed model of two-level asymmetrical
PCB interconnect tree, in Proceedings of 2013 International Symposium on Electromagnetic
Compatibility (EMC Europe), Brugge, Belgium, pp. 132–137, 2–6 Sept 2013
14. J. Cho, E. Song, H. Kim, S. Ahn, J.S. Pak, Ji. Kim, Jo. Kim, Mixed-mode ABCD parameters:
Trans. EMC 53(3), 1–9 (2011)
15. D.A. Frickey, Conversions between S, Z, Y, h, ABCD and T parameters which are valid for
complex source and load impedances. IEEE Trans. MTT 42(2), 205–216 (1994)
16. I. Chanodia, D. Velenis, Effects of crosstalk noise on H-tree clock distribution networks,
in Proceedings of 2006 International Symposium on CAS, vol. 4, Island of Kos, Greece,
pp. 5627–5630, 21–24 May 2006
17. I. Chanodia, D. Velenis, Effects of parameter variations and crosstalk on H-tree clock dis-
tribution networks, in Proc of 48th Midwest Symposium on CAS, vol. 1, pp. 547–550, Aug
2005
18. T. Eudes, B. Ravelo, T. Lacrevaz, B. Fléchet, Fast estimation of high-speed signal integrity
for coupled PCB interconnects, in Proceedings of 17th IEEE Workshop on Signal and Power
Integrity, Paris, France, pp. 159–162, 12–15 May 2013
19. C. Svensson, G.E. Dermer, Time domain modeling of lossy interconnects. IEEE Trans. Adv.
Packag. 24(2), 191–196 (2001)
20. A.R. Djordjevic, R.M. Biljic, V.D. Likar-Smiljanic, T.K. Sarkar, Wideband frequency-domain
characterization of FR-4 and time-domain causality. IEEE Trans. EMC 43(4), 662–667 (2001)
21. B. Ravelo, F. Vurpillot, A.K. Jastrzebski, Asymmetrical PCB interconnect tree modelling
with coupling effect, in Proceedings of 2014 International Symposium on Electromagnetic
Compatibility (EMC Europe 2014), Gothenburg, Sweden, pp. 713–718, 1–4 Sept 2014
22. B. Ravelo, A. Normand, F. Vurpillot, Modelling of interbranch coupled 1:2 tree microstrip
interconnect. ACES J. 33(3), 285–292 (2018)
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Chapter 11
Temperature Effect Analysis
on Microstrip Structure
Blaise Ravelo, Atul Thakur, Ashish Saini and Preeti Thakur
11.1 Introduction
With the tremendous trend on the electronic circuit design shirking size, the electro-
magnetic compatibility/interference (EMC/EMI), the signal integrity and the temper-
ature influence become critical effects [1–5] which must be integrated to the design
and fabrication phases. These undesirable physical phenomena are more and more
crucial for the deep submicron VLSI [1, 2]. It was found that the thermal effects
can induce particular phenomenon as the electromigration in the integrated circuits
[3, 4]. Moreover, the clock signal performances can be degraded due to the thermal
influence on the substrate [5]. More recently, electronic research and design engi-
neers experimented that the temperature effect and the moisture are susceptible to
degrade the PCBs global performance [6]. Due to the constant increase of integration
density, the substrate material characterization with the frequency and temperature
dependence becomes a challenging subject for the microwave and integrated circuit
designers and manufacturers [2, 7]. Until now, very few investigations on the tem-
perature influence to the electronic devices’ performance as the integrated [8] and
hybrid [9] circuits are available in the literature. Despite the developed EM classi-
cal modeling, simulation and test techniques [10, 11], the simultaneous influence
of electrical, EM and temperature effects on the microwave circuits and devices
remains an open question for the electronic research and design engineers. Further-
more, most of the existing classical EM characterization techniques dedicated to the
dielectric materials are based on the consideration of S-parameters by using waveg-
uide structures. Some of the available techniques are essentially carried out with the
through-reflect-line calibration [11], coplanar lines [12–14] and split-ring resonators
B. Ravelo
A. Thakur (B) · A. Saini · P. Thakur
Amity University, D-210, Gurugram, Haryana 122314, India
e-mail: athakur1@ggn.amity.edu

216 B. Ravelo et al.
[15]. However, those techniques present a heavy process complexity, and they do
not include the temperature effect and require sophistical analytical approaches. The
existing measurement technique of complex permittivity which takes into account
the temperature variation as proposed in [16] was set with different shapes of res-
onant cavity. Nevertheless, such a characterization technique is particularly limited
in terms of the operating frequency. Furthermore, it cannot be used for predicting
the material characteristics in the baseband and microwave frequencies which can
be regularly required for the digital and microwave or mixed SI analysis [17]. Com-
plex EM material characterizations for EMC and EMI applications have been also
developed [18–21].
To overcome such technical limits, a relevant characterization method enabling
to predict the substrate material parameters in the UWB frequency (with baseband
frequency up to some GHz) with the use of microstrip technology can be envisaged.
In addition to the flexibility of microstrip line theoretical approach, it enables a
particularly simple experimental process as can be found in [17].
This chapter addresses the EM characterization technique of dielectric substrate
material with the temperature influence based on the microstrip line theory. For the
better understanding, the present section is principally organized in three sections.
Section 11.2 is focused on the methodological approach of the substrate material
characterization method under study. The fundamental formulas enabling to deter-
mine the permittivity will be proposed. The experimental application of the analytical
approach will constitute Sect. 11.3. A microstrip test structure printed on FR4 epoxy
will be investigated. The conclusion of the chapter is drawn in the last section.
11.2 Empirical Methodology
The theoretical approach of this substrate material characterization method is elabo-

rated in the present section. The method is essentially built with the consideration of
microstrip structure. After brief introduction of the structure geometrical definitions
and its S-parameters, the formulas allowing the extraction of the parameters to be
determined will be proposed.
11.2.1 Formulation of the Temperature-Dependent Z-Matrix
The most accurate way to perform a substrate material EM characterization in

the baseband and broadband microwave frequency dependence is based on the S-
parameters’ measurement consideration. Thanks to the design simplicity and the
flexibility of the analytical approach, the TL and resonator structures are the most
popular technology to realize this characterization technique. In fact, by considering
the exploitation of S-parameters analytical definition in function of the geometri-
cal parameters, the substrate EM parameters as the permittivity formulation can be
11 Temperature Effect Analysis on Microstrip Structure 217
Fig. 11.1 Microstrip line

structure and its physical
parameters
extracted. Along with the chapter, the TL implemented in microstrip structure will
be investigated to establish the theoretical approach.
The configuration of the structure using the dielectric substrate characteristic
measurement method under study is shown in Fig. 11.1. It acts as a microstrip TL with
physical length d, metallization width w and thickness t which is printed on dielectric
substrate with height h. The substrate complex permittivity versus frequency f and
temperature T will be extracted from the TL measured two-port S-parameters.
Along the chapter, the reference impedance is denoted Z 0 = 50 . The two-port
system S-to-Z transform applied to the microstrip structure proposed in Fig. 11.1
allows to determine the access and transfer impedances. From where, the input
and transmitted impedance versus frequency f with respect to the S-parameters
measurement at the temperature T are defined as:

1 + S11 (jf , T ) − S22 (jf , T ) − S11 (jf , T ) · S22 (jf , T )
Z0 ·
+S12 (jf , T ) · S21 (jf , T )
Z11 (jf , T ) = , (11.1)
1 − S11 (jf , T ) − S22 (jf , T ) + S11 (jf , T ) · S22 (jf , T )
−S12 (jf , T ) · S21 (jf , T )
Z0 · 2S21 (jf , T )
Z21 (jf , T ) = (11.2)
1 + S11 (jf , T ) + S22 (jf , T ) − S11 (jf , T ) · S22 (jf , T )
+S12 (jf , T ) · S21 (jf , T )
On the one hand, these expressions permit to determine the TL matrix impedances
from the measured S-parameters by using a VNA. On the other hand, by assuming
that the TL is Z 0 -loaded and non-dispersive, the same input and transfer impedances
can be determined knowing the characteristic impedance Z c and the propagation
constant γ via the following expressions:
cos h(γ · d )
Z11 = Zc , (11.3)
sin h(γ · d )
Zc
Z21 = . (11.4)
sin h(γ · d )
To perform the temperature effect analysis, these analytical formulations will be

combined with the microstrip line properties. The building block of the determination
method of the substrate material parameters under study is described in the next
paragraphs.
11.2.2 Microstrip Substrate Temperature-Dependent

Characterization
First and foremost, the dielectric characteristics are established from the microstrip
line analysis combined with the Bahl and Trivedi theory [17]. By definition, the
TL propagation constant is defined in function of the per-unit loss α and the phase
constant β via the basic expression:
γ (jf , T ) = α(f , T ) + j · β(f , T ). (11.5)
From the member to member division of Eqs. (11.3) and (11.4), the following
expression of the propagation constant can be obtained:

1 Z11 (jf , T )
γ (jf , T ) = arg cos h . (11.6)
d Z21 (jf , T )
Then, the effective relative permittivity εreff (f , T ) of the dielectric material con-
stituting the microstrip TL can be established from the phase constant thanks to the
relation:
2
c · ∂β(f , T )
εreff (f , T ) = , (11.7)
2π ∂f
with c is the light speed in the vacuum. From where, the substrate relative permittivity
can be extracted with the expression [17]:
2εreff (f , T ) − 1 + a(w/h)
εr (f , T ) ≈ , (11.8)
1 + a(w/h)
where the mathematical function a(.) is defined by:

√ 1 + 0.04(1 − x)2 for x < 1
a(x) = 1+12/x
. (11.9)
√ 1
1+12/x
for x ≥ 1
Finally, the loss tangent can be extracted from the equation:

c · α(f , T )
tan δ(f , T ) ≈ . (11.10)
π · f εreff (f , T )
During the numerical modeling, those analytical relations were implemented as

MATLAB program. The computed results will be discussed in the next section.
11.3.1 Application for Microstrip Substrate Characterization
After introduction to the experimental setup, the measurement results exploitation

will be presented in this section based on the previous analytical approach.
The microstrip TL assumed as the circuit under test is photographed in Fig. 11.2.
It can be seen that this TL presents physical parameters w = 1.5 mm and d =
164 mm. The circuit is printed on FR4 epoxy substrate with height h = 0.8 mm and
copper etched with thickness t = 35 µm. The S-parameters of the circuit under test
were measured with the Agilent VNA 8502C from DC to 5 GHz. Moreover, after

tested interconnect line [22]
calibration, it was placed in the furnace provided by THITEC® depicted in Fig. 11.2.
The furnace presents the physical size 50 cm × 47 cm × 50 cm or volume 117 L.
The furnace operates with a digital function allowing to program the temperature of
its internal chamber. For the present study, the temperature chamber was increased
from ambient T = 40–140 °C. In order to consider the temperature influence on the
circuit under test, the sampling of the measured S(jf, T )-parameters was recorded at
least after five minutes of the temperature change.
To check the relevance of the proposed method, preliminary numerical tests with
EM computation based on the MoM were performed.
11.3.1.2 Discussion on Experimental Results
Based on the experimental setup shown in Fig. 11.3, the DUT S-parameters were
measured from DC to 5 GHz by increasing the temperature step by step. For the
sake of simplicity and temperature influence illustration, only the measured S 11 (f,
T ) reflection and S 21 (f, T ) transmission parameters at T = {40 °C, 60 °C, 85 °C,
100 °C, 120 °C, 140 °C} are presented, respectively, in Fig. 11.4a, b.
It is noteworthy that during the test, there is no significant difference between
S 11 (f, T ) and S 21 (f, T ) for T varied from the ambient temperature of about 20–40 °C,
and the TL losses increase with the temperature. Then, the UWB characteristics of
the FR4 constituting the DUT substrate from DC to 5 GHz can be determined from
expressions (11.7) and (11.10).
Consequently, the measured dielectric constant εr (f , T ) is plotted in Fig. 11.5a. It
can be emphasized that the obtained relative permittivity εr (f , T ) is proportionally
inverse of the temperature T. Moreover, εr (f , T ) presents an absolute variation of
about 0.27 when increasing the temperature from 40–140 °C. Furthermore, Fig. 11.5b
depicts the loss tangent in the same temperature range. The loss tangent tan[δ(f, T )]
increases with T from about 0.025 with margin of about 0.02. The loss tangent is

experimental test bench
including the VNA and the
furnace [22]
Fig. 11.4 Measured (a) -15

S-parameters of the DUT of
Fig. 11.2 for T = {40 °C,
60 °C, 85 °C, 100 °C,
120 °C, 140 °C} [22] -30
S11, dB
-45 40°C
60°C
85°C
100°C
120°C
140°C
-60
0 1 2 3 4 5
Frequency, GHz
(b) 0
-2
S21, dB
40°C
-4 60°C
85°C
100°C
120°C
140°C
-6
0 1 2 3 4 5
Frequency, GHz
sensitive to the TL resonance frequencies. This temperature effect can be reduced

by choosing material with less thermal coefficient of expansion and low losses.
The envelop of loss tangent can be estimated by using other methods like strip-line
ring resonator using proper calibration method and by reducing the systematic error
and instrumental error through repeated characterization. Compared to the existing
characterization techniques introduced in [10, 11], the proposed method is simpler
and allows to operate in UWB frequency from DC to several GHz. In addition, it
enables the microwave structure modeling versus temperature.
11.3.1.3 Conclusion
A simple and efficient characterization method of dielectric substrate constant and

loss tangent is developed. The method is particular innovative with its possibility to
operate in super UWB frequency with temperature influence. The proposed method
is based on the use of microstrip TL properties. The analytical concept illustrating
the methodology principle is presented. To illustrate the proposed method function-
ality, a proof of concept was designed, fabricated, simulated and experimented. The
(a) 5.5
Relative permittivity εr(f)

40°C
60°C
85°C
100°C
120°C
140°C
4.5
3.5
0 1 2 3 4 5
Frequency, GHz
(b) 0.06
40°C
60°C
85°C
100°C
0.04 120°C
140°C
tan(δ)
0.02
0.00
0 1 2 3 4 5
Frequency, GHz
Fig. 11.5 a Measured FR4 substrate dielectric constant and b loss tangent versus frequency and
temperature [22]
relevance of the method was verified with MoM numerical tests. Then, an applica-
tion with a prototype of microstrip TL printed on FR4 epoxy substrate is presented.
The dielectric constant εr (f , T ) and loss tangent tan[δ(f, T )] from DC to 5 GHz
were extracted by considering the temperature variation from 40 to 140 °C. More-
over, since the linear thermal coefficient of copper is 18.10−6 m/mK, the temperature
from 40 to 140 °C, i.e., by 100 °C will increase the length of microstrip line from
164 to 164.3 mm, i.e., by 0.18%.
The present method is limited to the prediction of the PCB substrate global char-
acteristic. The main drawback is for the characterization of typically micrometric
size materials. In addition, the method is particularly sensitive to the measurement
artefacts.
Fig. 11.6 Measured voltage 40° 100° 140°

transfer function: magnitude 40
(in top) and gain (in bottom)
|Vo|/|Vi| (dB)
for T = {40 °C, 100 °C, 20
140 °C} [23]
0
-20
0.5 1 1.5 2 2.5 3
Frequency (GHz)
Phase(Vo/Vi) (°)
-500
-1000
0.5 1 1.5 2 2.5 3

Frequency (GHz)
11.3.2 Application for Single Line SI Analysis
11.3.2.1 Measured VTF with Temperature Effect
From the measured S-parameters, the transfer function was extracted based on the
MATLAB computations. Figure 11.6 displays the measured frequency responses
of the interconnect line under test from DC to 3 GHz. As expected, the microstrip
line presents strong peaks of resonance frequencies. It can be pointed out that the
temperature effects are represented by the shift of the resonance frequency. This
observation can be understood due to the influence of the temperature on the substrate
relative permittivity.
The frequency-dependent equivalent RLC model of the microstrip line versus
frequency was extracted as introduced in [8] by taking into account the substrate
parameters. To complete the performed analysis, the time-domain analyses were
carried out. The obtained results will be presented in the next paragraph.
In the first analysis, the responses of the microstrip line including the temperature
influence T = {40 °C, 100 °C, 140 °C} were generated with equivalent RLC model.
Then, nonlinear load is assumed as a varicap.
The overall system was excited by 8-bit digital serial source “01011000” with
0.1 Gbps rate. The rise/fall time was fixed equal to 0.5 ns. The transient analyses
were launched with sampling time of about 0.1 ns. When the load resistive effect
was neglected, the obtained results are displayed in Fig. 11.7. It can be seen that the
Fig. 11.7 Time-domain vi vo(40°) vo(100°) vo(140°)

response of the microstrip
interconnect versus 3
temperature for R = ∞ and
C 0 = 5 pF, α 1 = 0.2 and α 2 2
= 10−6 [23]
Voltage (V)
1
-1
-2
0 20 40 60 80
Time (ns)
output signal is significantly influenced by the first resonance frequency located at

about 0.2 GHz. Over- and under-shoots of about 100% were occurred.
To improve the behavior of the output signal, optimization was realized. To do
this, the output load resistance and the varactor parameter α 1 were varied in order to
minimize the distortion with the input signal based on the least mean square method.
The retained matching value of the load resistance was R = 100 . Therefore, the
transient result depicted in Fig. 11.8a–c was realized. It can be seen that in this case,
the overshoot was considerably canceled out.
It is worth noting that the present electrical interconnect modeling allows to gener-
ate results with computation processor unit time lower than milliseconds. The present
method can be particularly useful for the PCB-conducted EMC and SI analyses when
the temperature and the nonlinear load influence need to be assessed. However, in the
considered temperature range, the signal delay variation is not empirically significant.
11.3.3 Transient Analysis of Coupled Microstrip Line
Further, transient analysis of coupled microstrip line combined with nonlinear load
is presented in this paragraph [23]. The layout of the coupled structure under study
is depicted in Fig. 11.9. It is comprised of a microstrip line having the same physical
characteristics (w = 1.5 mm, d = 162 mm) as the previous one shown in Fig. 11.9
neighbored with a piece of perturbation microstrip line TLp . The latter is also 35 µm
thickness Cu-metallized but the physical width w0 = 0.5 mm and length d 0 = 50 mm.
During the numerical tests, it was assumed that the two coupled lines are spaced by
0.5 mm.
vi vo(α 1=0) vo(α 1=0.4) vo(α 1=0.9)
2
Voltage (V) (a): T=40°
1
-1
0 50 100 150
Time (ns)
2
Voltage (V)
(b): T=100°
1
-1
0 50 100 150
Time (ns)
2
Voltage (V)
(c): T=140°
1
-1
0 50 100 150
Time (ns)
Fig. 11.8 Time-domain response of the microstrip interconnect versus α 1 and temperature for R
= 100 and C 0 = 5 pF and α 2 = 10−6 [23]
Fig. 11.9 Layout of the coupled microstrip line with nonlinear load (R = {∞, 100 }, C 0 = 5 pF,
α 1 = 0.2 and α 2 = 10−6 ). The perturbation line is loaded by R0 = 50 [23]
The considered structure was excited by the same source as in the previous paragraph
with 8-bit digital serial data “0101100” with 0.1 Gbps rate. The rise/fall time was
assumed to be equal to 0.5 ns. The computed results are plotted in Fig. 11.10a, b.
It can be seen that the output signal distortions are significantly visible because the
input signal rate was decreased which is equivalent to increase the signal bandwidth.
Then, the resonance effect is included in the bandwidth of the 10 ns-period input
data. The NL effect increases slightly the perturbation effect with the modification
of the over- and under-shoot. Furthermore, when the interconnect structure is open
loaded, due to the coupling influence, the resonance effect is increased when the
input is in “high level state”, vi = “1” and, contrarily, is decreased when the input is
in “low level state”, vi = “0”. However, the coupling effect increased and delayed the
instant peak time of the overshoot when R = 100 . This funding can be highlighted
in more general approach, for example, by using pseudo-random bitstream source
with 8-bit maximal sequence, one creates the eye diagram displayed in Fig. 11.11a,
b from the nonlinear loaded coupled structure shown in Fig. 11.9.
The synchronous clock signal is represented by a 0.1 Gbps rate periodic signal.
The rise/fall times and threshold voltage for detecting external trigger are, respec-
tively, 0.5 ns and 0.5 V. As can be seen in Fig. 11.9a, for the case of 0.1 Gbps rate
data, the height of the opening and the width of the cross are widely low for R =
∞. The eye pattern confirms once again that overshoot attains 100% of the input
Fig. 11.10 Compared (a) 3 vi v1 v2 v3

responses of the nonlinear
loaded single line (v1 ), 2
Voltage (V)
R-loaded coupled line (v2 )

and nonlinear loaded 1
coupled line (v3 ). a R = ∞
0
and b R = 100 [23]
-1
-2
0 20 40 60 80
Time (ns)
(b) 1.5
1
Voltage (V)
0.5
-0.5
0 20 40 60 80
Time (ns)
Fig. 11.11 Eye diagram (a) 3

from 0.1 Gbps data
streaming responses of the 2
Voltage (V)
nonlinear loaded coupled
1
interconnect line for a R =
∞ and b R = 100 [23] 0
-1
-2
0 5 10
Time (ns)
(b) 1.5
1
Voltage (V)
0.5
-0.5
0 5 10
Time (ns)
signal amplitude. The performance of the interconnect structure is clearly better as

illustrated by Fig. 11.11b with eye-opening height equal to 100% for R = 100 .
11.3.3.3 Conclusion
A SI analysis of PCB electrical microstrip interconnects responses including the

temperature effect and nonlinear influence was presented. The interconnect network
was assumed with RC and varactor nonlinear load. The methodology for extracting
the system time-domain response was presented.
Then, experimental setup including the temperature control process with con-
sideration of the furnace was explained. Then, based on the experimental data, the
optimized response of the interconnect line was realized and discussed. Further,
application results of nonlinear analysis with crosstalk will be added in the final
version of the chapter. Finally, the influence of the perturbation via microstrip line
in addition with nonlinear load was analyzed based on the eye diagram based on the
0.1 Gbps rate bitstream.
As ongoing research, the modeling method under study can be extended to more
general structures as the case of high-density PCB for the EMC and SI investigation.
An analysis methodology of the temperature effect onto the microstrip line behaviors
is developed in this chapter. The proposed thermal effect analysis is elaborated with
the combination of S-parameter theory. The reverse approach enables to realize an
extraction method of the microstrip line substrate characteristics dependently to the
frequency in function of the temperature. Then, an innovative approach of thermal
SI analysis is introduced.
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Chapter 12
General Conclusion
Blaise Ravelo
Analytical methodologies of fast modeling of PCB interconnect are introduced in

this book. The interconnect model is built with the TL elements which can behave
as lumped or distributed circuits. By combining the circuit, microwave and signal
theories, fascinating ways to establish the interconnect parameters as Z and Y and T
and S-matrices are developed. Then, the spontaneous steps leading to the determi-
nation of the signal integrity parameters are introduced. The proposed methods can
be applied to both frequency domain and time domain analyses.
The book offers also fantastic methods to analyze and model particularly complex
electrical PCB interconnects behaving as SIMO or tree networks. First, a fast way
named as SIMO to SISO transform enabling to determine the topological diagram
equivalent to the electrical paths between the different nodes is proposed. Then, the
parameters of the SISO circuit as the analytical current or voltage transfer function
are elaborated. Moreover, deep challenging analyses of the interconnect tree with
interbranch coupling are also developed. Finally, wink on the temperature effect
onto the interconnect behavior is also addressed.
The concrete approach of the proposed analysis and modeling methodology is
verified with classical microstrip structures.
B. Ravelo (B)

Summary
The book focuses on the modelling methodology of microstrip interconnects. Various

structures of single-input multiple-output (SIMO) tree interconnects for the signal
integrity (SI) engineering practice are addressed. Lumped and distributed transmis-
sion line elements based on single-input single-output (SIMO) models of symmetric
and asymmetric trees are elaborated. More complicated phenomenon as the inter-
branch coupling is also investigated. The modelling approach is based on the ana-
lytical approaches using the Z-, Y- and T-matrices. The established method enables
to determine the SIMO tree S-parameters and voltage transfer function. Illustrative
results with frequency and time domain analyses are provided for each case of tree
interconnect structures. The book can benefit researchers, engineers and graduate
students in fields of analogue, RF/microwave, digital and mixed circuit design, SI
and manufacturing engineering.
The applications of the modelling methods proposed in this book concern gener-
ally on the SI characterization of microwave, digital and mixed electronic systems.
In difference to most of the manual books which are providing characterization tech-
niques using the existing computational commercial tools and measurement equip-
ments, the proposed one investigates in depth the analytical modelling of different
topologies of tree interconnect structures. Nowadays, these interconnect structure
modelling remains one of the most challenging topics. The models enable to pro-
vide fast and accurate analyses of the PCB trace effects on the SI, power integrity,
electromagnetic interference and EMC engineering. The book is particularly suited
for readers who are interested in the development of real positioning systems, both
hardware and software.

Modelling For Signal Distribution, https://doi.org/10.1007/978-981-15-0552-2

Analytical Methodology of Tree Microstrip Interconnects Modelling For Signal Distribution

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Blaise Ravelo Editor

ISBN 978-981-15-0551-5 ISBN 978-981-15-0552-2 (eBook)

Sotteville-lès-Rouen, France Blaise Ravelo

10 Analytical Modelling of Interbranch Coupling Effect on Coupled

Dr. Blaise Ravelo is currently an Associate Professor at the Graduate Engineering

Instrumentation & Measurement, Ieee Transactions On Industrial Electronics,

HFSS® High Frequency Solver Simulator® (Simulation tool from

1.1 Preliminary Introduction

1.2 Analysis Methodology of PCB Electrical Interconnects

© Springer Nature Singapore Pte Ltd. 2020 1

1.3 Z/Y/T/S Parameter of Single-Input Single-Output

1.4 Analytical Modelling of Single-Input Multiple-Output

The interconnect structure is assigned as a SIMO system when it presents several

1.4.1 Symmetric Tree

1.4.2 Non-symmetric or Asymmetric Tree

The modelling of asymmetric type of interconnect trees is developed in Chap. 8.

1.5 Analysis of PCB Interconnect Interbranch Coupling

Chapters 9 and 10 describe the analyses of coupling effect between interconnect

1.6 Analysis of Temperature Effect onto the PCB

1.7 Outline of the Book Chapters

The present book is organized in ten main chapters:

Thomas Eudes and Blaise Ravelo

T. Eudes · B. Ravelo (B)

© Springer Nature Singapore Pte Ltd. 2020 5

2.2 Recall on Elementary Cell

2.2.1 Elementary L-Cell

Fig. 2.1 Unit L-cell formed N in Z N out

where s is the Laplace variable. A mathematical analogy related to these elementary

2.2.2 T-Matrix Modelling of Periodical Identical L-Cell

So, one demonstrates that the recursive

M(n+1)11 = (1 + Z · Y )Mn11 + Y · Mn12 , (2.5)

M(n+1)12 = Z · Mn11 + Mn12 , (2.6)

M(n+1)21 = (1 + Z · Y )Mn21 + Y · Mn22 , (2.7)

M(n+1)11 = Z · Mn21 + Mn22 , (2.8)

2.3 Analytical Investigation of Microstrip Transmission

2.3.1 Microstrip Line Physical Parameters

Fig. 2.3 Microstrip TL

dielectric substrate is characterized by its height h, relative permittivity εr and loss

Knowing the physical properties of the microstrip structure, the characteristic

2.3.2 RLCG Parameter Extraction Method

can be calculated with the following expressions:

Fig. 2.4 TL RLCG model

is the operating angular frequency.

where μ0 is the vacuum permeability. By using these parameter definitions, one

2.3.3 T-Matrix Modelling

As example of numerical–digital interconnection circuitry [11, 25–27], let us con-

gate source interconnection line load gate

Fig. 2.5 Interconnection TL driven and loaded by logic gates

transfer matrix of the interconnection line characterized by (Z c , γ ) with geometrical

The considered RLCG modelling behaviour is previously depicted in Fig. 2.4.

gate source interconnection line load gate

2.3.4 VTF Modelling

2.4 S-Parameter and Time-Domain Convolution Applied

2.4.1 Topological Analysis

Source Interconnect line Load

vin Zs (d, Zc, ) ZL vout

2.4.2 S-Parameter Modelling of PCB Microstrip

According to microwave theory, the scattering- or S-matrix is a mathematical concept

2.4.3 Time-Domain Convolution Methodology

To illustrate the functioning of the present modelling technique, let us consider a

Reflections, transmission and

Voltage transfer function ABCD Matrix Z and S Matrices

Input signal and