Design of Counters Using Reversible Logic

V. Rajmohan, Member IACSIT Dr. V. Ranganathan

Department of Electronics & Communication Engineering Department of Electronics & Communication Engineering
Hindustan Institute of Technology & Science, Chennai, KCG College of Technology, Chennai. India
India drvrangan@yahoo.com
rajmohan.vijayan@gmail.com

Abstract –- Now-a-days, the reversible logic design attracts Rest of the paper is organized as follows. Section II
more interest due to its low power consumption. A lot of provides the idea of basic and necessary reversible logic
research has been done in combinational as well as sequential gates used in this work. Section III provides the details about
design of reversible circuits. In this paper we have proposed a the proposed reversible gate. Section IV provides the
reversible T-Flip-flop which is better than the existing designs optimized reversible T Flip-flop and its comparison with the
in the literature. A novel design of reversible asynchronous existing work. Section V provides the conventional
and synchronous counters is also proposed in this paper. As asynchronous structure and its reversible design. Section VI
far as it is known, this is the first attempt to apply reversible provides the conventional synchronous structure and its
logic to the counter design. In this paper we have also
reversible design. Section VII concludes the work.
proposed a new reversible gate which can be used as copying
gate. We hope this paper will initiate a new area of research in
the field of reversible sequential circuit.
II. REVERSIBLE LOGIC GATES
Keywords – Low-power VLSI, Low-power CMOS design, This section describes the reversible logic gates that are
reversible logic, quantum computing, reversible counters being used in the design.
Fig. 1 shows a Feynman Gate [13]. Feynman Gate (FG)
can be used as a copying gate. Since a fan-out is not allowed
I. INTRODUCTION in reversible logic, this gate is useful for duplication of the
required outputs.
Reduction of power dissipation remains one of the major
Fig. 2 shows Sayem Gate [12]. A single Sayem Gate (SG)
goals in the VLSI circuit design for many years. R.Landauer
can be used to realize the function of D-Latch.
demonstrated in the early 1960s, irreversible hardware
Fig. 3 shows the Fredkin Gate (FRG) [15]. This is the
computation results in energy dissipation due to the
most widely used reversible gate.
information loss, regardless of its realization technique [1]. It
is proved that the loss of each one bit of information
dissipates at least KTln2 joules of energy (heat), where
K=1.380650 x 10-23 m2kg-2K-1 (joules Kelvin-1) is the
Boltzman’s constant and T is the absolute temperature at
which operation is performed [1]. Reversible logic circuits
have theoretically zero internal power dissipation since they
do not lose information. Bennett showed that in order to Figure 2 Sayem Gate
avoid KTln2 joules of energy dissipation in a circuit, it must
be built using reversible logic gates [2]. The applications of
reversible logic are quantum computation [3], optical
computing [4], ultra low power CMOS design [5] and nano
technology [6].
Even though some significant works ([7] - [12], [14])
have been already done in the field of reversible sequential
logic design, research on reversible counters has not been Figure 3 Fredkin Gate
done. This paper proposes a novel concept on reversible
sequential circuit design which includes asynchronous and
synchronous counters.

Figure 1 Feynman Gate

Figure 4 Peres Gate
___________________________________
978-1-4244 -8679-3/11/$26.00 ©2011 IEEE

138
 Fig. 4 shows a Peres Gate (PG) [16]. It is also known as
New Toffoli Gate (NTG). Functionally Peres Gate is equal
with the transformation produced by a Toffoli Gate followed
by Feynman Gate.
7. The reversible realization of T Flip-flop has two SG gates
and one Feynman Gate. And it has two constant inputs and it
produces three garbage outputs. The comparison of the
proposed design with the existing designs is given in Table
III.
TABLE II POSITIVE EDGE TRIGGERED T FLIP-FLOP

III. PROPOSED REVERSIBLE GATE CLK T Qt-1 Q

We have proposed a new conservative reversible gate 0 0 0 0
named RSJ Gate. This is a 2 through 4x4 reversible gate.
1 0 0 0
The block diagram of the proposed gate is shown in Fig. 5.
Its corresponding Truth Table is shown in Table I. From this 0 0 1 1
truth table we can verify that the input and output vectors are 1 0 1 1
unique which satisfies the condition of reversibility. 0 1 0 0
1 1 0 1
0 1 1 1
1 1 1 0

Figure 5 Proposed RSJ Gate

TABLE I TRUTH TABLE OF THE PROPOSED REVERSIBLE GATE

A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
Figure 6 Reversible Positive Edge Triggered T Flip-flop
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 0
0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 1
1 1 0 0 1 1 1 1
Figure 7 Block Diagram
1 1 0 1 1 1 1 0
1 1 1 0 1 1 0 1 TABLE III COMPARISON OF DIFFERENT T FLIP-FLOPS WITH
1 1 1 1 1 1 0 0 ONLY Q OUTPUT

No. of Garbage Constant

Gates Outputs Inputs
IV. PROPOSED REVERSIBLE POSITIVE EDGE
Existing [9] 10 12 10
TRIGGERED T-FLIPFLOP
A flip-flop is a bi-stable electronic circuit that has two Existing [14] 5 3 2
stable states and can be used as a one-bit memory device. In
Existing [17] 10 10 10
this section we propose the construction of a Master-Slave T
Flip-flop using reversible gates. The truth table of the T Flip- Proposed design 3 3 2
flop is given in Table II. The reversible design is shown in Improvement factor
Fig. 6 and the corresponding block diagram is shown in Fig. 3.3 4 5
w.r.t [9]

139
 Improvement factor reversible T Flip-flop, the complemented Q output is
1.6 - -
w.r.t [14] produced using Feynman Gate with the input B=1. These
Improvement factor
3.3 3.3 5 complemented Q outputs of each T Flip-flop trigger the
w.r.t [17] subsequent T Flip-flops and the reversible design performs
the Up-Counter operation.
Each T Flip-flop contains 3 reversible gates, 2 constant
V. DESIGN OF ASYNCHRONOUS REVERSIBLE inputs and 3 garbage outputs. Hence the proposed reversible
COUNTERS counter design contains 15 reversible gates, 11 constant
The counter is one of the most intensively used inputs and produces 12 garbage outputs.
functional devices in digital systems. The counter is
basically a group of flip-flops connected together in such a B. Proposed 4-bit Asynchronous Down-Counter
way that the combined output will perform the counting The reversible design of the above 4-bit asynchronous
operation. In a ripple/asynchronous counters, the output Down-Counter is shown in Fig. 10. At the output of each
transition of one Flip-flop serves as a source for triggering reversible T Flip-flop, the fan-out of Q output is produced
other flip-flops. using Feynman Gate with the input B=0. These Q outputs of
each T Flip-flop trigger the subsequent T Flip-flops and the
A. Proposed 4-bit Asynchronous Up-Counter reversible design performs the Down-Counter operation. The
The conventional circuit diagram of a 4-bit binary ripple proposed reversible counter design contains 15 reversible
up-counter and its corresponding truth table is shown in Fig. gates, 11 constant inputs and produces 12 garbage outputs.
8 [18].
C. Proposed 4-bit Asynchronous Up/Down Counter
The reversible design of the asynchronous Up/Down
Counter is shown in Fig. 11. The Up/Down operation of this
reversible design is controlled by the control input
UP/DOWN. When this control input is 1 the reversible
design operates as an Up counter. When this control input is
0 the reversible design operates as a Down Counter. The
proposed reversible counter design contains 15 reversible
gates, 11 constant inputs and produces 12 garbage outputs.

Figure 10 Proposed 4-bit Reversible Asynchronous Down-Counter

Figure 8 Conventional 4-bit asynchronous Up-Counter (a) circuit diagram,
(b) Truth Table

Figure 11 Proposed 4-bit Reversible Asynchronous Up/Down-Counter

Figure 9 Proposed 4-bit Reversible Asynchronous Up-Counter

The reversible design of the above 4-bit asynchronous

Up-Counter is shown in Fig. 9. At the output of each

140
 VI. DESIGN OF SYNCHRONOUS REVERSIBLE the AND function. The proposed reversible synchronous
COUNTERS counter design contains 18 reversible gates, 18 constant
In the synchronous counters, the count pulses are applied inputs and produces 16 garbage outputs.
directly to the control/CLK inputs of all the Flip-flops.
Synchronous counters have regular pattern and can be
constructed using flip-flops and gates.

A. Proposed 4-bit Synchronous Up-Counter

A conventional 4-bit Synchronous Counter (count-down)
with count enable function can be realized as shown in
Fig.12 [18].
The reversible design of the above 4-bit Synchronous
down Counter is shown in Fig. 13. The proposed RSJ gates
are used to produce the copy of the Q output of the T Flip-
flops. The Peres gate is used to realize the AND function.
The proposed reversible synchronous counter design
contains 15 reversible gates, 13 constant inputs and produces
12 garbage outputs.

Figure 14 Conventional 4-bit Synchronous Up/Down Counter

Figure 15 Proposed 4-bit reversible synchronous Up/Down Counter

Figure 12 Conventional 4-bit Synchronous Down-Counter

Figure 13 Proposed 4-bit reversible synchronous down counter
B. Proposed 4-bit Synchronous Up/Down Counter
The conventional 4-bit Synchronous Up/Down-Counter
is shown in Fig. 14 [18]. The reversible design of this 4-bit
Synchronous Up/Down Counter is shown in Fig. 15. The
proposed RSJ gates are used to produce the copy of the Q
output of the T Flip-flops. The Peres gate is used to realize
VII. CONCLUSION
The key contribution of this paper is the reversible
realization of 4-bit Asynchronous and synchronous counters
by using proposed reversible gates and the existing one. As
far as it is known, this is the first attempt to apply reversible
logic to counter design in the literature. We also have
proposed a new conservative reversible gate. This gate can
be used to produce multiple copies of a signal. The proposed
asynchronous and synchronous counter designs have the
applications in building reversible ALU, reversible processor
etc. This work forms an important move in building large
and complex reversible sequential circuits for quantum
computers. The future work could be to develop efficient
reversible counters and reversible controller circuits.

141
 REFERENCES
[1] Landauer, R., “Irreversibility and heat generation in the computing
process”, IBM J. Research and Development, 5(3): pp. 183-191, 1961.
[2] Bennett, C.H., “Logical reversibility of Computation”, IBM J.
Research and Development, 17: pp. 525-532, 1973.
[3] M. Nielson and I. Chuang, “Quantum Computation and Quantum
Information”, Cambridge Univ. Press, 2000.
[4] E. Knill, R. Laflamme and G.J. Milbun,”A scheme for efficient
quantum computation with linear optics”, Nature, vol. 409, no. 6816,
pp. 46-52, 2001.
[5] G. Schrom, “Ultra-low-power CMOS Technology”, PhD thesis,
technschen Universitat Wien, June, 1998.
[6] R.C. Merkle, “Two types of mechanical reversible logic”,
Nanotechnology, vol.4, pp. 114-131, 1993.
[7] P. Picton, “Multi-valued sequential logic design using Fredkin gates,”
Multiple-Valued Logic Journal, vol. 1, pp. 241-251, 1996.
[8] J. E. Rice, “A New Look at Reversible Memory Elements,”
Proceedings of IEEE International Symposium on Circuits and
Systems, 2006.
[9] H. Thapliyal and M. B. Srinivas, “A Beginning in the Reversible
Logic Synthesis of Sequential Circuits,” Proceedings of Military and
Aerospace Programmable Logic Devices International Conference,
2005.
[10] NM Nayeem, Md A Hossian, L Jamal and Hafiz Md. Hasan Babu,
“Efficient design of Shift Registers using Reversible Logic,”
Proceedings of International Conference on Signal Processing
Systems, 2009.
[11] Himanshu Thapliyal and N Ranganathan, “Design of Reversible
Latches Optimized for Quantum Cost, Delay and Garbage outputs,”
Proceedings of International Conference on VLSI Design, 2010.
[12] Abu Sadat Md. Sayem and Masashi Ueda, “Optimization of
Reversible Sequential Circuits,” Journal of Computing, vol.2, issue 6,
pp. 208-214, 2010.
[13] R. Feynman, “Quantum Mechanical Computers,” Optical News, 1985,
pp. 11-20.
[14] SKS Hari, S Shroff, Sk Noor Mahammad and V. Kamakoti,”Efficient
Building Blocks for Reversible Sequential Circuit design,”
Proceedings of the International Midwest Symposium on Circuits and
Systems, 2006.
[15] E. Fredkin and T. Toffoli,” Conservative Logic,” International
Journal of Theoretical Physics, vol 21, pp.219-253, 1982.
[16] A. Peres, Reversible logic and Quantum Computers. Phys. Rev. A,
Gen. Phys., 32(6): 3266-3276, Dec. 1985.
[17] J.E. Rice, “A New Look at Reversible Memory Elements,”
Proceedings of IEEE International Symposium on Circuits and
Systems, 2006.
[18] M. Morris Mano, Michael D. Ciletti,” Digital Design,” fourth edition,
Pearson Education, pp. 268-288.

142