ZONE BASED PROTECTION FOR LOW VOLTAGE SYSTEMS;
ZONE SELECTIVE INTERLOCKING, BUS DIFFERENTIAL AND THE
SINGLE PROCESSOR CONCEPT
Copyright Material IEEE
Paper No ICPS-08-23
Marcelo Valdes, PE Paul Hamer, PE
IEEE Senior Member IEEE Fellow
GE Industrial and Consumer Chevron
Plainville, CT Richmond, CA
Marcelo.Valdes@GE.com PaulHamer@Chevron.com
Radoslaw Narel Bill Premerlani, PHD
GE consumer and Industrial GE Research
Plainville, CT Niskayuna, NY
Radoslaw.Narel@GE.com Bill.Premerlani@CRD.GE.com
Abstract - Time based coordination and protection is the
normal basis for coordinating low voltage power distribution
systems. Enhancements, such as zone selective interlocking
and bus differential protection, may be used to accelerate
protective devices. However, these improvements may be
costly, difficult to implement, and may not function as expected
using commonly available technology. Nevertheless, the
potential benefit of fault clearing speed and selectivity are more
valued in today’s arc-flash and reliability conscious
environment than ever before. The writers shall discuss some
issues associated with these traditional improvements, pitfalls
to avoid and, more effective ways to implement zone-based
protection to achieve fast fault protection while maintaining
complete selectivity for a broad range of fault magnitudes,
system configurations and load types.
Index terms - Selectivity, coordination, zone-selective-
interlocking, bus differential, motor contribution, Single-
Processor-Concept, directional overcurrent protection.
I. INTRODUCTION
Low voltage power distribution systems must deliver reliable
power within constraints of cost and size using available
technology. Protective devices must be selected and adjusted
to operate selectively, reliably and as quickly as possible.
Protection has traditionally been coordinated by ensuring that
for any specific value of fault or overload current the
downstream device closer to the over current is faster than the
upstream device further away from the overcurrent. This time-
based coordination can achieve good system selectivity.
However, it does this at the cost of the upstream overcurrent –
protective-device’s speed. In a large power system, important
main devices can be significantly delayed to allow layers of
load side devices to clear selectively. To improve upon time
based coordination two well known methods can be used:
zone-selective-interlocking, and differential protection.
This paper will briefly review the effect of clearing speed on
arc flash energy, and how zone selective interlocking and
differential protection can improve device speed. There are
limitations, and risks of improper operation for these methods
that will also be discussed, as well as how to mitigate those
risks using the “Single-Processor-Concept”[1].
Within this paper the expression, “algorithms are run
simultaneously” will be used. In the context of the “Single-
Processor-Concept”, this statement means that algorithms are
executed within the same ½ power cycle. In the
implementation of the “Single Processor Concept” referenced
current, voltage, status and commands for all equipment
Tom Papallo
GE Industrial and Consumer
Plainville, CT
Tom.Papallo@GE.com
circuits are processed every ½ cycle at a central. Commands
to trip or open a circuit breaker are issued at the end of each
such data processing cycle simultaneously to the start of the
next processing cycle. Hence, multiple algorithms can process
the same synchronized data and optimize their overall
performance. For further elaboration on the system
architecture the reader is encouraged to read reference 1 “The
Single-Processor Concept for Protection and Control of Circuit
Breakers in Low-Voltage Switchgear”[1].
Current transformers used in the referenced implementation
of single processor concept are not traditional ANSI relay class
transformers. These current transformers are referred to as
sensors and have secondary currents below one ampere.
Their characteristics are incorporated and compensated in the
algorithms as required to achieved required accuracy.
II. BACKGROUND
A. Impact of Clearing Speed on Protection
Incident arc flash energy is an accepted way of measuring
damaging heat energy radiated from an arc in air during an
arcing fault event. IEEE 1584-2004[2] provides formulas to
estimate arcing current and incident heat energy over a range
of working distances under a variety of conditions. The guide
defines arcing current as a function of available voltage and
bolted fault current (Ibf), and the gap between the current
carrying conductors. The calculated arcing current is less than
the bolted fault current. Fig. 1 demonstrates the relationship of
arcing current to bolted fault current as a percent at three
different voltages for a conductor gap of 32 mm. A 480V arcing
current varies from 43% to 56% available short circuit current
for available short circuit current values of 20kA to 100kA.
% of Ibf
80% 600V
70% 480V
208V
60%
50%
40%
30%
20%
10%
0%
100
20
30
40
50
60
70
80
90
Ibf
Fig. 1. Arcing Current as Function of Prospective Fault
Current, 32 mm Gap, Arc in Box Formula.[2]

The relationship of arcing current to available bolted fault
current also varies depending on the gap between electrodes.
The electrodes represent the current carrying conductors. Fig.
2 shows that the relationship can range from 65% at 20,000A
available and a 13mm gap to 43% with 100,000A available and
a 32mm gap.
Protective device reaction speed must be considered in
relation to the arcing current present during an arcing fault
event. Fig. 1 and 2 demonstrate that the arcing current can be
a variable percent of the prospective fault current based on
multiple parameters identified in the IEEE 1584 guide. The
IEEE guide is based on a series of tests performed under
specific laboratory conditions. The standard states that two
values of arcing current be used to identify protective device
operating speed, and resultant arcing energy; the calculated
arcing-current, and 85% of that value. In the opinion of the
authors, more variance is possible because these formulas are
based on calibrated bolted fault currents and very specific
electrode geometry. Additional unaccounted variance could be
caused by system impedance not considered in short circuit
calculations such as connections, distribution equipment
impedance and protective device impedance. Additional
variations in the geometry of the conductors involved in the
arcing event that differ from those used in the laboratory could
create differences between actual and predicted arcing
currents. No generally accepted method exists to account for
this variance at this time, however, conservative use of the
calculation should, probably, consider additional variance in
arcing current and in incident energy around the values
predicted by the model.
Fig 2. Arching Current as a Function of Prospective Fault
Current, at 480 V, HRG, for Various Electrode Gaps. [2]
Other considerations are the sources of fault current, the
direction, and path of each fault current contribution. A bus with
significant available short circuit current may have a portion of
that current come from motor contribution. These various
considerations mean the arcing fault current through the main
may be surprisingly small. Consider a 62kA, 4,000A low
voltage switchgear bus with an estimated 10,000A of motor
contribution through feeders, and estimated 52,000A of
transformer contribution through the main circuit breaker. The
potential arcing current flowing through the main over-current
device may be estimated for 480V switchgear:
• 62,000 –10,000 = 52,000A (transformer contribution only)
• 52,000 x .48 = 25,000A (.48 is from graph in fig. 2)
• 25,000 x .85 = 21,250A (85% to account for arcing current
variance from known bolted currents)[2]
Hence, in a system with a significant value of prospective
short circuit fault current we see that current through the main
device for an arcing fault on the main bus may be less than
22,000. If, this is a 4000A bus, the arcing fault current could fall
within the tolerance of a 5X pick rating for the main circuit
breaker and below 50% the current limiting threshold of a
4000A Class L fuse. A main circuit breaker may not consider
this a short-time fault and a 4000A fuse would not be operating
in its current limiting range.
Additional arcing current variance could be introduced by
incorrect utility information or conservative assumptions in the
short circuit current calculations that result in higher calculated
fault values than available. The impedance of conductor
terminations and protective devices, for example, will introduce
impedance not normally taken into account during short circuit
calculations. Traditional fault current calculations to identify the
required rating of equipment and components must be
conservative by making sure any error results in higher, not
lower, calculated fault currents. When calculating arc flash
incident energy, the more dangerous level of energy may
happen with, either, lower or higher arcing fault values. While
higher arcing current will cause higher incident energy per
cycle, lower arcing fault current values may result in slower
protective device operating times that will increase incident
energy.
The potential for low arcing currents could add significant risk
to an arc flash event. Any device, whether fuses or circuit
breakers, that depends on high current values to operate
quickly can operate differently from expected if arcing currents
are lower than expected. For large low-voltage-power circuit
breakers even short time pick up points set to achieve
selectivity with the required short time characteristics of loads
in the system may be set above potential arcing currents.
III. TRADITIONAL ENHANCEMENTS, CONCERNS
A. Impact of Arc Flash Current on Short Time Pick Up
Fig. 3 is the relationship of calculated energy vs. time in
cycles, for a HRG 480 V system with a 32 mm electrode gap
and an 18-inch working distance. As the graph indicates a
2
clearing time that exceeds 22 cycles will result in ~ 40cal/cm .
Above this level, no level of PPE is suitable.
Fig. 3. Incident Energy as Function of Clearing Time in Cycles,
480V, HRG, 32mm, 18”, 52kA Ibf, Arc in Box.[2]
In this example the main circuit breaker set with a short time
pick up of 5x nominal will have a short time pick up band of
18,000 to 22,000A. Though it may not be common for a large
main circuit breaker to be set this high, such settings may
result from similar settings in large feeders and allowances for
high inrush currents. The 21,250A three-phase arcing fault
 CURRENT IN AM PERES X 1000 AT 480 VOLTS
current calculated raises the possibility the circuit breaker may 1000
900
800
.5 .6 .8 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 100 2 3 4 5 6 7 8 9 1000 2 3 4 5 6 7 8 9 10000
1000
900
800

clear at its long-time delay instead of the faster short-time 700

600
500
700
600
500
400 400

delay. Even if this device is part of a zone interlocking scheme, 300 300

if the current does not exceed the short time pick up, the
200 200

device will not operate within the short time band. 100
90
80
70
60
100
90
80
70
60

The longer clearing time could result in a significant level of 50

40

30
50
40

30

incident arc flash energy, well above HRC4 (hazard risk 20 20

category 4). A 4000A class-L fuse with a current limiting 10

9
8
10
9
8

threshold around 55,000A would not improve the situation. 7

6
7
6

TI ME IN SECONDS

TI ME IN SECONDS
5 5
4 4

3
Main operating 3

B. Zone Selective Interlocking and Motor Contribution: 2

as back up
2

Direction Matters 1
.9
.8
1
.9
.8
.7 .7
.6 .6
.5
Main operating .5

In zone-selective-interlocking (ZSI), several levels of circuit .4

.3 for in zone fault

.4

.3

breakers operate selectively at their minimum time delay for in- .2 .2

zone short-time faults. For a series of circuit breakers as .1

.09
.08
.07
.1
.09
.08
.07

shown in Fig. 4 communication is enabled that allows devices .06

.05
.04
.06
.05
.04

to receive blocking signals from downstream devices and also .03

.02
.03

.02

allows the device to send a signal to the next upstream circuit .01 .01

breaker. The signal is generated when the circuit breaker .5 .6 .8 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 100 2 3

CURRENT IN AM PERES X 1000 AT 480 VOLTS

4 5 6 7 8 9 1000 2 3 4 5 6 7 8 9 10000

senses current that exceeds its short time pick up level. If that
circuit breaker also receives a blocking signal, it will operate at
a programmed delay. If it does not receive a blocking signal, it
will operate at its minimum time delay.
Fig 5. ZSI Effect On Upper CB in 2 CB Scheme
Let us consider a situation as shown on the one line in Fig. 6.
In the system shown an 800A frame CB is feeding an MCC
with four 100Hp motors. Each motor has full load current of
current of 146.3A amperes and a locked rotor current of 863A
(5.9 x FLA). The motors will start individually during expected
operation of the system the 800A CB is set above 125% of the
motor bank’s full load current – 732A (146.3A x 4 x 1.25). The
short time pick up of the circuit breaker is set to clear 125% of
3 motors FLA + 125% of one motor’s starting current ((146.3A
x 3 + 146.3 x 5.9) x 1.25), 1624A.

Fig 4. Three Level Zone-Selective-Interlocking System.

Zone interlocking depends on feeder circuit breakers sensing

in-zone fault current and sending blocking signal to the mains
and ties. The time-current-curve in Fig. 5 demonstrates the
effect of zone selective interlocking on short time operation of
two circuit breakers. If current flows through the feeder to a
fault in its zone then the blocking signal will cause the main CB
to operate at its set delay above the feeder’s clearing time.
This ensures fast operation of the feeder while maintaining the
main as a back up if the fault current also exceeds the main’s
short-time pick-up. If the fault occurs on the main bus, the
feeder will not see it and the main will operate at its faster time Fig 6. Bus Fault With Source and Motor Contribution
delay and clear in less than 100 milliseconds.
Fig. 7(a) is the time current curve for the feeder, the main
(operating in the zone interlocked mode) and the motor load.
The motor load is shown with a 10 second starting inrush for
one motor with the other three running at full load.

Fig. 7(a). Feeder set for MCC load, 1 motor start
Fig. 7(b) demonstrates the same circuit under bus fault
conditions and the MCC’s contribution of fault current for 0.1-
.05 second. The motor contribution is enough to initiate short
time timing in the feeder circuit breaker and hence the feeder
circuit breaker will issue an interlocking signal to the main
causing it to operate at a delayed time band. The main is now
reacting more slowly for a fault in its zone of protection than
intended by the system designer. The reverse current caused
by the motor contribution fools the feeder circuit breaker into
operating as if it is feeding a fault on its load side. The Zone
Selective Interlocking, in this case, performs opposite from
expected.
Fig. 7(b). MCC Fault Contribution to Main bus Fault – Main
nd
CB Forced to 2 Delay by ZSI Signal From Feeder
This risk can be addressed by setting the feeder’s delay
higher or adjusting the short time pick up higher. In either case,
some desirable protection is compromised.
In the case of a bus with no low voltage main, the primary
medium voltage transformer protective device main may be
zone interlocked with the feeders. The problem of fault
contribution from motors through feeders is equally valid when
the main is on the other side of a transformer, and slower than
expected operation of the medium voltage device is also
possible.
C. ZSI Applications in Multiple Source Systems With
Ties: Selectivity or Protection
In distribution systems with tie circuit breakers, ZSI schemes
may be configured two different ways; with a selective tie, or
with fast mains. Fig. 8(a) demonstrates the general (may vary
by manufacturer) configuration for a selective tie and Fig. 8(b)
for fast mains. Both of these schemes result in a compromise
between selectivity and fast protection.
Fig 8(a). Zone-Selective Interlocking With Selective Tie
In the selective tie configuration, the feeder circuit breakers
on both sides of the tie interlock with the tie. The tie then
interlocks with both mains. A fault downstream of a feeder will
properly keep the tie and mains operating at a delayed interval
while the feeder should clear the fault faster. For a fault on
either bus, the tie will delay the mains while it separates the
buses. However separating the buses does not clear the fault.
Whichever bus is faulted remains faulted until the respective
main clears one time delay later. In this scenario the feeders,
tie and mains are coordinated, one time delay is saved, but the
fault can remain energized for two time delays via one source.
The fast main connection interlocks the feeders with the tie
and both main circuit breakers. I this case bus fault will be
seen by all three circuit breakers as a fault within their
respective zones and all three circuit breakers will trip at a
minimum time delay. Fast protection is achieved, however
system reliability is sacrificed.
In an ideal system the main and tie feeding the faulted bus
would clear in minimum time while the other bus remained
connected to its dedicated source.
Fig 8(b). Zone-Selective-Interlocking With Fast Mains
D. Zone Selective Interlocking and Faults Ahead of a
Main Circuit Breaker
Most low voltage power systems will be fed from a
transformer via a low voltage main circuit breaker. A fault
detection and isolation problem exists when a fault occurs
between the low voltage main and the transformer secondary
terminals. During closed tie operation, with sources in parallel
the fault is fed from the other source through the tie and both
main circuit breakers (Fig. 14). Knowledge of the magnitude of
current flow is not enough to identify fault location even when a
ZSI scheme is used. In the selective tie configuration shown in
Fig. 8(a) the tie circuit breaker would clear first and properly
isolate the fault from the other source, though not from all
motor contribution, and would drop at least one bus
unnecessarily. However, in the fast main configuration shown
in Fig. 8(b) both mains and tie will clear simultaneously,
unnecessarily disconnecting both buses from their source.
In an ideal situation, the main closest to the fault should
separate the fault from the other source in minimum time. The
tie, as well, as the other main should remain closed. A medium
voltage device should also operate as quickly as possible
separating the fault from its primary source. To accomplish this
the fault location must be known.
E. Zone Selective Interlocking and Instantaneous
Protection
To achieve the fastest possible protection and minimum of
cascaded time delays it is desirable to use a feeder circuit
breaker with an instantaneous characteristic set low enough to
sense arcing currents in the protected circuit. Any circuit
breaker upstream may be set at a short time band to be
selective with the feeder circuit breaker. Traditionally the short
time band should be position above the clearing time of the
feeder circuit breaker operating instantaneously. With large
stored energy devices instantaneous clearing times are usually
drawn at 3 cycles (50ms). The short time band in the next
device would start above 3 cycles as shown on the left side of
Fig. 9.
Fig. 9. Traditional ZSI (Left) Above Instantaneous vs. Faster
Implementation (right) Overlapping Feeder Instantaneous
It would be more desirable that the short time delay of the
second circuit breaker operate faster and still maintain
selectivity with the overlapping instantaneous response of the
low-voltage-power circuit breaker downstream. The right side
of Fig. 9 shows two circuit breakers with the main device
operating at a faster short-time band that overlaps the
instantaneous band of the feeder. Any zone selectively
interlocked circuit breakers further upstream would be
selectively operating at the same short-time band. This second
faster operating mode would be preferable because it results
faster protection as long as selectivity can be provided by an
interaction of the instantaneous and fast short time protection.
A delay of 20 to 25 milliseconds is sufficient to be selective
with the clearing time of most molded case circuit breakers
operating instantaneously that may be fed through that main
device. Minimum time delay available may vary by
manufacturer.
F. Bus differential Protection: Best Zone Protection
Bus differential protection is based on Kirchoff’s node law:
“all the currents into a node (bus) must equal all the currents
exiting a node”. A bus differential algorithm is able to calculate
fault current subject to the limitations of error in sensing and
signal processing. Medium voltage relays used for this function
typically employ a percentage-differential-slope, which adjusts
the threshold relative to the magnitude of currents being
measured. This method allows the algorithm to compensate for
the non-linear characteristics of iron core current transformers.
However, in low voltage systems, high fault currents combined
with small CT ratings may significantly exceed the saturation
level of iron core current transformers making the percent
slope method impractical for an extended range. At some large
current, the error can no longer be compensated.
Fig. 10. Two Zone Double Ended Substation
Bus differential is most applicable to detection of lower value
higher-impedance faults that may or may not exceed the short
time pick up of large main and tie circuit breakers. As fault
currents increase, a properly zone-interlocked system can
provide similar results as a differential algorithm. Hence a
combination of bus differential protection and properly set zone
selective short time protection can provide a broad range of
selective protection operating in minimum time.
Bus differential protection requires dedicated current
transformers and a dedicated relay. In low voltage applications,
this scheme may be regarded as too costly or complex to
consider. Furthermore traditional relaying and CTs may not be
able to handle the required dynamic range to maintain
nuisance free tripping for through-faults due to saturation.
IV. IMPROVEMENTS & ENHANCEMENTS POSSIBLE
A. The “Single-Processor-Concept” and Fault Location
The “Single-Processor-Concept”[1] for circuit protection is a
system where a single processor takes all pertinent system
information and is able to process it simultaneously for a
complete line up of power distribution equipment. Since all
current and voltage information is synchronized and available
in one place at the same time, calculations may be made using
single simultaneous data samples or RMS values calculated
over time. Which type of data is used depends on what is
optimal for the algorithm.
Fig. 11. Simultaneous, Instantaneous Values of Four
Waveforms Available Through Simultaneous Sampling
Fig. 11 demonstrates how four instantaneous (single data
samples) values for the four currents in a simple radial system
can be used to calculate the differential current for the bus at
every data sample. Proper polarity assignment allows a
differential calculation to be made with every data sample
using current magnitude only. The calculations can be
corrected for expected signal and processing error. Tests have
shown that using this method and iron core current
transformers sufficient resolution to detect fault currents
smaller than the rating of the bus being protected can be
achieved. Performing the calculation for a length of time such
as 1 or 1.5 cycles allows sufficient calculations to be made to
confirm, with a high degree of certainty, the magnitude and
location of the fault current.
The single processor concept allows the use of the same
circuit information for a variety of protective and control
algorithms such as bus differential without the need for single
function dedicated devices. Hence, the same hardware
providing normal over-current, ground fault and zone selective
interlocking, can provide bus differential protection
simultaneously.
B. Combining Bus Differential and Zone Selective
Interlocking: Complete Range Fault Detection
Limiting the differential calculations to a range where the
measured currents do not exceed 10 times the rated current of
any CT in the system keeps the calculation within the linear
range of the transformers. The differential function can be
complimented by the short-time zone-selective-interlocking
scheme. The combination provides fault sensing and location
information over the complete expected fault range.
A 4,000 ampere bus with 4,000 amp mains and tie would
require over 40,000 amperes of fault current through either the
main or the tie before the bus differential algorithm would be
suspended. In a situation where the fault is downstream of a
1,600-ampere feeder, fault current through the feeder must
exceed 16,000 amperes for the bus-differential algorithm to be
disabled. In either or these situations, the current is high
enough to engage the short time pick up of the circuit breakers
required to isolate the fault optimally and, to reach 10X for 1.5
cycles would require a forward fed fault from a significant
source, not reverse fed motor contribution.
C. Method for Detection of Current Direction in Faulted
Systems With Multiple Fault Current Sources: Relative
Direction
To address potential issues created by motor contribution or
closed tie operation with multiple sources the zone selective
interlocking system would need to identify relative fault current
direction. Traditional implementations of zone selective
operations are not able to do this. Sufficient identification of
fault current direction can be achieved in the single processors
system because faults currents can be compared to each
other. Since the intent is to simply identify relative direction, the
exact angle or magnitude is not required, and significant error
can be accommodated without loss of key directional
information.
To address the problem of which side of the tie a fault is
located an algorithm similar to a partial differential calculation
may be used. A partial differential calculation uses only the
mains and ties thereby minimizing cumulative error caused by
many small current transformers associated with the feeders.
Current direction may be defined as inward (+1) for current
flowing towards the bus, or outward (-1) for current flowing
away from the bus. Fig. 12 demonstrates the left main, and the
tie flowing towards the bus. This identifies a fault on the main
bus. The right bus has one current flowing in, and one current
flowing out, hence it is not the faulted bus.
Fig. 12. Fault Current Contribution for Left Side Fault
In the situation where a single feeder circuit breaker goes
into short time trip pick up timing in addition to the main and
ties the direction of that feeder’s current can also be compared
to the main’s and tie’s current direction. If the current is
determined as inward then the fault is in the bus. If the fault
current in the feeder is opposite the current direction in the
main and tie then the fault is a through-fault fed by the feeder.
Consider the case where two feeders go into simultaneous
short time-pick up timing, both may be determined to be
flowing in the same direction as the main and tie, i.e. inward.
That indicates the fault is in the bus. If one feeder is flowing
inward and the other outward then the fault is on the load side
of the one feeder with current flowing opposite all other
excessive currents.
The situation where two feeders are both simultaneously
feeding separate faults on their load side is improbable.
However, it would not result in a lack of tripping. The logic can
identify that neither is flowing in the same inward direction as
the main and tie and hence both feeders should trip.
 The specific method is to consider each zone as a partial
differential using only ties and mains. Equation (1) would be
used when any CB in the zone is identified as having current in
excess of its short time threshold.
Ir = ¦I M − ¦ ( I T * DT ) (1)
1− p 1− q
Where Ir is the residual for the partial differential zone, IM is
the current for the main, IT is the current for the tie and DT is
the reference direction unit vector for the tie. The reference unit
vector is designated such that if the tie and main current flow
towards the bus equation (1) adds the two currents. p and q
are the number of mains and ties feeding the partial differential
zone respectively. Ir is compared to a minimum threshold such
as 1.5 times the largest CT in the zone (usually the main).
When Ir exceeds this threshold the fault is in the zone or being
fed by the zone.
In the case that one or more current readings exceed 10X
their respective CTs a test is set up to find a large reference
phasor for each phase current and then all the other currents in
short time pick up are compared to those phasors to determine
relative direction. Once a reference phasor is identified for
each phase, the phasor for current in each phase of every
breaker in the partial differential zone that has exceeded a
defined current threshold can be compared.
For each phase, a reference current and angle is calculated -
IE and ang(IE). Whether other fault currents for that phase in the
partial differential zone are same is identified by first computing
the angular difference between a faulted breaker in the zone
and the reference faulted circuit breaker via equation (2).
Δ θ = ang ( I α ) − ang ( I β )
(2)
Where I is the phase current in the circuit being considered
and 'T is the angular difference.
. The angular difference is checked to determine if the
currents are in the same direction, defined as “in, 1”, or in the
opposite direction, defined as “out, 0”. The logic can handle
significant angular error because the expected angular
difference is 180 degrees for opposing currents. If the angular
difference is between + 60 degrees from 180, the currents are
considered to be in opposite directions.
However, since this is a partial differential algorithm
additional consideration must be given to feeders, to determine
if the fault is in the zone or fed through the zone. To that end
only the current of any feeders that are in short time pick up
are considered. If the current through the feeder is determined
to exceed 10X (a value that should be above potential motor
contribution) then the fault is determined to be downstream of
the feeder. If the current is under 10X and above the feeder’s
short time pick-up then direction of the feeder’s fault current is
determined to properly locate the fault.
To determine the relative direction of a faulted feeder’s
current it must also be compared to a reference phasor that
represents the “in” current for the respective faulted partial
differential zone. The phasor representing each phase current
for every faulted feeder fed by the faulted partial differential
zone is compared looking for a difference in direction that is
180’ + 60’. If the difference is found then the feeder is
conducting current towards a downstream fault, if the angular
difference is outside of this range then the feeder is conducting
motor contribution towards the main bus. The various tests on
the faulted feeders will determine if one feeder is feeding a
fault in its zone of protection or multiple feeders are conducting
motor contribution towards a bus fault.
Once the determination is made of what each CB in the zone
is conducting, all the proper circuit breakers can be opened.
Whether it’s one main, a main and a tie, or several sources into
a bus including downstream motor contribution, all devices
contributing fault current can be identified. Proper back up
circuit breakers can be identified and operated if required as
best suits the fault location, magnitude and system
configuration at the time of the fault. This can be done in the
same time frame that a simple short time calculation can be
made for a single circuit breaker.
D. Method for Detection of Fault Current Direction Ahead
of Main Circuit Breakers: Absolute Direction
Further analysis demonstrates that if the fault were located
on the line side of a main the algorithm, based on relative
direction of current in the source circuit breakers would yield
inconclusive results. In the case of a fault on a main’s line side
the fault location would be indeterminate, as neither bus would
show the fault located within them. Both buses would show the
tie and main with current flowing in opposite directions
indicating a through fault. See Fig. 14 for an illustration of this
situation. To solve for this situation knowledge of the actual
current direction through the main circuit breaker is required.
Fig 14. Fault Contribution to Fault Ahead of Main
In a single-processor-based system, data from the present
may be compared to past data. This allows a comparison of
pre-fault voltage to pre and post-fault current to be made after
any current in excess of the pick up threshold is detected.
Comparing the phase angle of fault current with the phase
angle of pre-fault current, and looking for the reversal will
detect a reverse current fault. A pre-fault voltage phasor
maybe continuously calculated and discarded when it is
updated. When current exceeding fault magnitude is
exceeded, the voltage phasor from a predetermined number of
cycles back would be used as a reference. Reversal would be
indicated by a 180-degree shift as well as any additional lag
the fault conditions would introduce. Post fault phase voltage
would be an unreliable source of information as voltage may
collapse considerably during fault conditions. In a case of
complete voltage collapse the small remaining voltage would
be the bus IR drop that is always in phase with current and
would not yield the information required. Hence, the algorithm
implemented in equation (3) will detect current reversal.
150 ≤ ang( I ) − α ≤ 250
D D
(3)
Where ang(I) is the angle of the positive sequence current
phasor and α is the pre-fault voltage positive sequence phasor.
The expected theoretical angle for a forward current would be -
0 to 90 degrees for a purely resistive to purely inductive
current. A reversal in current would add 180 degrees and
would range from 180 to 270 degrees. More realistically the
forward angle may be 0 to 60 degrees for resistive to very
inductive loads. A reversal of 180 degrees would cause the
angle to shift to 180 to 240 degrees. The above algorithm
should identify a fault shifting from load currents flowing at 30
degrees leading to 70 degrees lagging (-30º < α < 70º). The
pre-fault positive-frequency voltage phasor would require
compensation for any mismatch between sampling rate and
frequency. That compensation is ignored in the above formula
for sake of simplicity.
The algorithm in equation (4) may be performed on each
(I ) ≥ ( P
phase current periodically to determine fault current.
2
RMS RC )2 (4)
Where IRMS could be computed form ½ cycle of current
samples for each phase and PRC is the reverse current
protection setting chosen for the main circuit breaker being
considered.
Once it is determined that a current through the main has
exceeded the pick up threshold for reverse current pick up, a
series of calculations can be run comparing the angular
relationship between pre-fault positive-sequence current and
post fault positive-sequence current by referencing both to pre-
fault positive-sequence voltage. If the current is determined to
have reversed then the fault is ahead of that device. Since this
reverse current setting need not be considered for forward
current coordination analysis the pick up level may be quite low
and the delay only as long as required to make a reliable trip
decision. Zone selective interlocking can provide back up
levels of protection even in this reverse direction by reversing
the hierarchy implemented for forward faults.
These comparisons plus appropriate error compensation,
cooling and heating algorithms can be used to provide quick
reverse fault protection on any circuit breaker. The application
is most useful at main circuit breakers to detect reverse-fed
fault current in parallel multiple-source systems or when
substantial motor contribution can provide the required current
to identify a fault.
V. SUMMARY
A. Directionally Sensitive Zone Based Protection
Based on this set of solutions, available to the protection
engineer a complete zone based protection system can be
provided for multiple source, or single source systems with
large motor loads capable of substantial motor contribution or
with multiple sources operating in parallel. The algorithms
operating simultaneously would be:
• Bus differential protection
• Short time -Reverse current detection at mains
• Short time – Directional zone interlocking between mains
and ties
• Short time - Directional zone selective interlocking at
And
feeders with zones above them
• Instantaneous tripping function at feeders able to operate
while other ZSI functions operate simultaneously
The instantaneous function would be continuously performed
in any of several ways in which instantaneous tripping is
obtained in modern digital trips. If an instantaneous trip
because of potential motor contribution to a bus fault or
separate feeder fault is not desired then the instantaneous
should be set above the potential maximum motor contribution.
All short time functions, including those for the circuit breaker
operating instantaneously can continue to function regardless
initiation of the instantaneous trip function as long as the
system is designed to do so.
The bus differential function is performed independently of all
other functions and would continue to function as long as no
single current exceeded 10 times the rating of any CT within
the zone. Bus differential may be set significantly under the
short time pick up level of any main or tie and offers the most
sensitive fault protection. Since bus differential functions only
for bus faults the setting is independent of all other settings in
the system that may be required for optimum selectivity or
sustaining loads.
Reverse current protection at the main would function
independently and would issue a trip signal to the proper circuit
breaker when the algorithm is satisfied, including a medium
voltage transformer main if provided. The same algorithm
would simultaneously block action by the other short time
functions to prevent unnecessary nuisance tripping if other
sources can continue to sustain load.
All algorithms are able to reliably calculate with as little as
two half cycles of current data. The combination of the various
algorithms operating simultaneously can provide identification
of fault location ahead, within and downstream of a bus in a
line up of switchgear with multiple sources and closed ties,
regardless of motor contribution magnitude relative to the short
time settings of feeder circuit breakers. The minimum
sensitivity of a the bus differential algorithm allows fault smaller
than the a bus’ current rating to be located and the various
short time algorithms allow faults up to the short circuit rating of
the equipment, if the circuit breakers allow it, to be detected
and located with 1 cycle of data.
Limitations in range of settings, circuits, and exact detection
and clearing times would depend on the specific
implementation of the algorithms described and the devices
used to implement the system.
B. Putting it Together
The net effect of these implementation on 2500kVA
substation with a 4000A main and tie, a 1600A feeder and
vacuum CB ahead of the transformer is shown on the time
current curve in Fig. 15. A current limiting molded case circuit
breaker located downstream of the 1600A feeder is added for
comparison.

Fig 15. TCC: MCCB, Swgr Feeder and Swgr Bus
The time current curve shows the following devices:
• 250A molded case current limiting MCCB applied on a bus
with 30kA bolted fault available, 17,100A arcing fault
available at 100%, 14,500 arcing current at 85%
• 1600A LVPCB feeder applied on a system with 65kA total
bolted fault current, calculated arcing at feeder load side of
30,500A at 100%, 26,00A at 85%, single source
• 4000A with 62kA bolted fault current available from one
source. 4000A bus is protected with a combination of bus
differential protection set to pick up at 800A and functional
up to 40,000A, with a delay clearing in 92 ms. A zone
selective algorithm keeps the main operating at minimum
time delay all the way to maximum fault value.
In addition the main CB is able to isolate the load side from any
line side fault condition or if a parallel source is provided such
as during a close transition transfer. This function would look
like definite time function similar to how 87B is shown in Fig.
15. The reverse protection is not shown on this TCC.
The feeder protection and main bus protection are fully
selective. The MCCB may be fully selective based on its
current limiting capabilities.
All calculated arc flash currents downstream of the feeder are
interrupted by a device operating instantaneously, the main
bus arcing current is interrupted by devices operating at
minimum time band yielding the following energy levels at
480V
• Main bus, 62kA Ibf, 32mm, 24”, .092s ==> 7.9cal, HRC2
• Main bus, 62kA Ibf, 32mm, 18”, .092s ==> 12cal, HRC3
• Feeder terminals, 32mm, 18”, .05s ==> 6.5cal, HRC2
• MCCB bus, 30kA Ibf, 25mm, 18”, .05s ==> 3.8cal, HRC1
• MCCB terminals, 25mm, 18”, .017s==> 1.3cal, HRC0
The above listed arc flash energy values do not reflect the
result of actual testing of these devices for arc flash
performance, which would generally result in lower incident
energy values nor do they account for motor contribution
decrement which could lower values further.
VI. REFERENCES
[1] “The Single-Processor Concept for Protection and Control
of Circuit Breakers in Low-Voltage Switchgear”, M Valdes,
T Papallo & I Purkayastha, IEEE Transactions July/August
2004, pg 932-940. Also presented at IEEE PCIC 2003.
[2] “IEEE Guide for Performing Arc-Flash Hazard
Calculations”, IEEE Standard 1584-2002, Published by
The institute of Electrical and Electronic Engineers, Inc.
NY, NY.
VII. VITA
Paul Hamer (S’70–M’74–SM’89–F’97) received the B.S.E.E
degree from Virginia Polytechnic Institute and State
University, Blacksburg, and the M.S.E.E. degree from Oregon
State University, Corvallis, in 1972 and 1979, respectively. In
1979, he joined Chevron Corporation, where he is currently a
Consulting Engineer, Electrical Machinery and Power
Systems, with Chevron Energy Technology Company,
Richmond, CA. His primary responsibilities include power
system, motor, and generator application and consultation.
He has worked on many refining, chemical, and oil production
projects during his career with Chevron. As a member of the
American Petroleum Institute (API) Subcommittee on
Electrical Equipment, he has contributed to the API standards
for induction and synchronous machines and the API
recommended practice on electrical area classification. He
represents the API on the National Electrical Code, Code-
Making Panel 11, on the subjects of motors, motor circuits,
and controllers, and on the technical committee for NFPA
70E, Standard for Electrical Safety in the Workplace. From
1972 through 1977, he was with Westinghouse Electric
Corporation, where he was a Service Performance Engineer
with the Large Generator Department and an Industrial Power
System Engineer and Resident Engineer with the Industry
Services Division. Mr. Hamer has been an active member of
the Petroleum and Chemical Industry Committee of the IEEE
Industry Applications Society since 1981. He is a Registered
Professional Electrical Engineer in the State of California.
Radoslaw Narel graduated from Technical University of
Bialystok, Poland in 1996 with MS degree in Computer
Science. He started with GE in 1999 in the New Product
Development department. He has worked on multiple power
protection related software / firmware projects. He currently
holds position of senior software engineer and leads technical
aspects of a single processor power protection firmware
project. He is the holder of 3 US and international patents.
Tom Papallo graduated from the University of Connecticut in
1986 with a BS degree and in 1989 with an MS degree, both in
Mechanical Engineering. He started with GE in 1986 in the
New Product Development department. He has also worked on
circuit breaker and electrical distribution system projects for
several other major manufacturers, returning to GE in 1997. He
is currently the technical lead for a New Product Development
project and an adjunct member of the Design Office for the
New Product Introduction Department, Plainville, CT. He is the
holder of 18 US and international patents has co-authored
three IEEE technical papers.
Dr. William Premerlani graduated from Rensselaer
Polytechnic Institute in 1971, 1972, and 1974 with a BS, MS
and Doctor of Engineering in Electric Power Engineering. He
has since worked at GE’s Global Research in Niskayuna, New
York, exploring a wide range of technologies in the fields of
parallel computing, power system protection, and software
development. Dr. Premerlani holds more than 35 patents, and
has co-authored numerous technical papers. His current
research interest is in phasor measurements and advanced
protection algorithms. He is a co-author of the popular
textbooks: “Object Oriented Modeling and Design” and “Object-
Oriented Modeling and Design for Database Applications”.
Marcelo E. Valdes graduated from Cornell University in 1977
with a BS in Electrical Engineering. He has held various field
and management positions at General Electric since 1977. He
currently is the Manager of Application Engineering for GE’s
Circuit breaker Business in Plainville Connecticut. Mr. Valdes
is past chair of several local IEEE chapters. He is a registered
Professional Electrical Engineer in California. Mr. Valdes has
co-authored several technical papers in IEEE forums and has
several patents pending in the field of power systems
protection.