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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Configurable Logic Operations Using

Hybrid CRS-CMOS Cells
Xiaoping Wang , Member, IEEE, Shuai Li, and Zhigang Zeng , Senior Member, IEEE

Abstract— Memristors have recently begun to be explored

in logic operations. In this paper, a compact scheme using
complementary resistive switching (CRS)-CMOS cells (CCCs)
for logic operations and data storage is proposed. Several logic
operations, including IMPLY, IMPLY- AND, AND, NAND, OR, and
NOR , are realized with CCCs. Then the AND –OR logic and the
OR –AND logic are presented to realize the programmable logic
arrays built with CCCs, providing opportunities for memristor-
CMOS integrated circuits.
Index Terms— Complementary resistive switching (CRS)-
Fig. 1. (a) Typical I –V characteristic of a memristor. (b) Typical V –I
CMOS cell (CCC), logic operation, memristor, programmable characteristic of a CRS.
logic arrays (PLAs).

I. I NTRODUCTION
T HE memristor was originally proposed by Chua [1]
in 1971 and later fabricated by Williams’s team at HP
Labs in 2008 [2]. As a new nanoscale device, the memristor
presents many favorable features, such as nonvolatility, fast
switching speed, high density, and good-scalability, which
provides realization of more efficient circuits with tremendous
possibilities. With these coveted properties, memritors are
quite capable of holding promise for use in diverse appli-
cations, such as digital circuits, passive crossbar arrays, and
nonvolatile random access memory [3]–[7]. In addition, there
are many popular researches, such as machine learning [8],
controller designing [9], [10], and stability [11], [12], can
also try to use memristor as the core component to design
the corresponding circuits.
Computational logic is one of applications of memristors,
where memristors are adopted as basic elements of logic
gates, which can save space of the integrated chip due to
their nanoscales. Several different logic families focusing on
individual logic gates have been proposed, such as IMPLY
gates [13] and complementary resistive switch (CRS)-based
gates [14], [15]. Although IMPLY gates and CRS-based logic
gates can be exploited to realize various logic functions with
a few memristors, all of these logic functions required a well-
designed sequencer to operate the logic gate, and any basic
Boolean function required more than one clock to perform
Manuscript received June 19, 2017; revised October 21, 2017 and
December 25, 2017; accepted January 4, 2018. The work was supported by
the National Natural Science Foundation of China under Grant 61374150.
(Corresponding author: Xiaoping Wang.)
The authors are with the School of Automation, Huazhong University of
Science and Technology, Wuhan 430074, China, and also with the Key
Laboratory of Image Processing and Intelligent Control of Education Ministry
of China, Wuhan 430074, China (e-mail: wangxiaoping@hust.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2018.2791625
1063-8210 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
the computation [16], which incurs high delays for Boolean
operations.
In this paper, the CRS-CMOS cell (CCC) is presented
to realize several logic operations, including IMPLY, AND,
IMPLY-AND, NAND, OR, and NOR, whereby programmable
logic arrays (PLAs) can be built with CCCs to realize logic
functions in a simple configurable way. Besides, the CCCs
can be used to build the nonvolatile memory to eliminate the
destructive read in the memory built with CRS.
II. M EMRISTOR
As a two-terminal device, two states can be encoded within
memristors: the high-resistance state (HRS) and the low-
resistance state (LRS). In this paper, memristors with threshold
voltages Vset and Vreset are adopted. When the voltages across
memristors exceed threshold voltages, the states of memristors
can be changed. As shown in Fig. 1(a), an applied voltage
larger than Vset can change a memristor into LRS, a volt-
age smaller than Vreset can change a memristor into HRS.
If the voltage across a memristor is between Vset and Vreset ,
the state drift of the memristor can be negligible for simplicity.
Therefore, the memristor can be regarded as the bipolar
switching device.
Passive memristive crossbar arrays have the issue of sneak-
path currents due to the fact that the crossbar architecture is
based on the memristor as the only memory element, without
gating [17]–[19]. To alleviate the sneak-path currents, CRSs
consisting of two antiserial memristors X and Y were proposed
to act as memory cells [15]. State combinations of X and Y
are used to encode logic values, and logic 0 and logic 1 can
be represented with RON /ROFF and ROFF /RON , respectively. The
V –I characteristic of a CRS is shown in Fig. 1(b), and the state
change of the CRS is determined by threshold voltages Vth1
and Vth2 . A positive voltage greater than Vth2 can switch the
CRS into RON /ROFF (logic 0), and a voltage lower than −Vth2
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 2. (a) CCC built with NMOS. (b) CCC built with PMOS, the peripheral
circuits for precharging is omitted. (c) Truth table of IMPLY. (d) Truth table
of IMPLY.
can switch the CRS into ROFF /RON (logic 1). The voltage
between Vth1 and −Vth1 cannot change the state of CRS, and it
can be adopted to detect the state of CRS. However, previous
CRS approaches in crossbar arrays suffer from the destructive
read issue, the CRS may be switched into an unstable state
during reading, and an extra write back operation is required to
turn the CRS into its original state after reading. In this paper,
we present the CCC to construct the memory, which simplifies
the reading operations and provides a new approach to realize
logic operations.
III. H YBRID CRS-CMOS C IRCUITS
A. Hybrid CRS-CMOS Cells
As shown in Fig. 2(a) and (b), the memory cell consists
of a CRS A and a transistor T . The state of A is set by
the voltage Vc between bitline i n and word line r ow. If the
voltage Vc greater than Vth2 is applied at i n and r ow is
grounded, A is switched into RON /ROFF (logic 0). If the voltage
Vc lower than −Vth2 is applied and r ow is grounded, A is
switched into ROFF /RON (logic 1). That is to say, the cells can
be configured into different states to realize different logic
functions according to different applications.
B. Nondestructive Reading
Different from the previous destructive read approaches
in CRS arrays [7], we adopt the transistor T to detect the
state of A. There are two steps during the reading process,
pr echarge and executi on. The pr echarge step is similar
to [20], the line out is precharged to Vcharge through peripheral
circuits marked with a dashed rectangle in Fig. 2(a). In the
executi on step, V R (lower than Vth1) is applied at i n and r ow
is grounded, memristors X and Y act as a voltage divider, and
the voltage of node g determines whether T is activated or not.
Assume that the resistances of X and Y are R X and RY ,
the voltage at node g can be expressed as follows:
RY
Vg = VR .
R X + RY
Assume (ROFF /RON ) = 100, V R = Vcharge < Vth1 , when A
stores logic 0 and logic 1, respectively, the Vg can be written
Fig. 3. (a) Circuit of IMPLY-AND operations. (b) Circuit of IMPLY-AND.
The peripheral circuits for precharging are omitted.
as follows:
ROFF
Vg | A=0 = VR ≈ VR (2)
RON + ROFF
RON
Vg | A=1 = V R ≈ 0. (3)
ROFF + RON
The voltage on the line out is Vcharge after the pr echarge
step. If T is an nMOS, V R is large enough to activate the
transistor T . Therefore, when A stores logic 0, T is activated
to discharge out to ground. When A stores logic 1, out keeps
the voltage Vcharge . If T is a PMOS, when A stores logic 1, T is
activated to discharge out to ground. When A stores logic 0,
out keeps the voltage Vcharge . Therefore, the logic value in A
can be read from out.
C. IMPLY and IMPLY Operations
To execute logic operations using the CCCs, we assume
that logic values can be represented by the states of A and
I/O voltages. That is to say, RON /ROFF or the low voltage
(≈0 V) represents logic 0, and ROFF /RON or the high voltage
(≈V R ) represents logic 1. In Fig. 2(a), A and i n are used as
operands, and the result in the form of voltages is obtained
at out. Using these designs, the IMPLY logic operation is
presented as follows after the precharge step is completed.
1) Case 1: When i n = 0, A = 0, and a low voltage is
applied at i n, the transistor T cannot be activated and
out keeps at the high-voltage state (logic 1).
2) Case 2: When i n = 0, A = 1, and a low voltage is
applied at i n, the transistor T cannot be activated and
out keeps at the high-voltage state (logic 1).
3) Case 3: When i n = 1, A = 0, a high voltage V R
is applied at i n, and A holds at the state RON /ROFF ,
the transistor T is activated to discharge out to ground
(logic 0).
4) Case 4: When i n = 1, A = 1, a high voltage V R is
applied at i n, and A stays at the state ROFF /RON , the tran-
sistor T keeps at the nonactivated state (logic 1). The
truth table of the IMPLY operation is shown in Fig. 2(c),
and we can obtain
(1)
out = i n + A. (4)
When pMOS is adopted as shown in Fig. 2(b), the IMPLY
operation can be realized. The operation process is similar
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WANG et al.: CONFIGURABLE LOGIC OPERATIONS USING HYBRID CCCs 3

Fig. 4. (a) Simplified AND–OR logic PLA, r1, r2, and r3 are inverters. (b) Simplified OR–AND logic PLA.

with the aforementioned IMPLY operation. When i n = 1 and
A = 0, the transistor T holds at the nonactivated state, out
holds at the high-voltage state during the executi on step. For
other cases, the transistor T is activated to discharge out to
ground. The truth table of the IMPLY operation is shown
in Fig. 2(d), and we can obtain
out = i n · A.
D. IMPLY-AND, AND, NAND, OR, and NOR Operations
In Section III-C, we have presented IMPLY and IMPLY
operations. Now we use multiple CCCs to realize the
IMPLY-AND logic operation as shown in Fig. 3(a). If any
transistor is activated, out is discharged to ground during
executi on step, therefore, we can obtain
out = (i n1 + A) · (i n2 + B) · (i n3 + C).
If i n1 = i n2 = i n3 = V R (logic 1), we can obtain AND logic
from (6)
out = A · B · C.
If A = B = C = RON /ROFF (logic 0), we can obtain NOR
logic from (6)
out = i n1 · i n2 · i n3 = i n1 + i n2 + i n3.
Similarly, IMPLY-AND can be realized as shown
in Fig. 3(b). An inverter is required to get out from out, out
and out can be expressed as follows:
out = (i n1 · A) · (i n2 · B) · (i n3 · C) (9)
out = i n1 + A + i n2 + B + i n3 + C. (10)
If in1 = in2 = in3 = V R (logic 1), we can obtain OR logic
from (10)
out = A + B + C. (11)
If A = B = C = RON /ROFF (logic 0), we can obtain NAND
logic from (10)
out = i n1 + i n2 + i n3 = i n1 · i n2 · i n3. (12)
E. Programmable Logic Arrays
Any logic function can be resolved into the combination
of AND logic operations and OR logic operations, and OR
logic and AND logic can be configured into PLAs to realize
logic functions. PLA can be built with CCC according to the
analysis in III-D. Two different schemes to realize PLA are
(5) presented as follows.
1) AND–OR Logic PLA: As shown in Fig. 4(a), the PLA con-
sists of AND and OR arrays. Assume that operands have been
configured into CCC of AND arrays during the initialization.
To initialize the arrays, conventional CRS arrays write schemes
can be directly adopted [15]. V R is applied at i n1, i n2, and i n3
to realize AND operations during the executi on step, which
are used to obtain minterms of target logic functions. For
example, the intermediate results in Fig. 4(a) out1 , out2 ,
and out3 can be obtained as follows:
(6)
out1 = ABC (13)

out2 = ABC (14)
out3 = ABC. (15)
(7)
In OR arrays, intermediate results are used as inputs to get
the final results, and intermediate results are selected by
configuring the cells in OR arrays to act as operands in
OR operations according to (6). If a cell is configured into
(8) logic 0, the intermediate result in the same row is select as
an operand. In contrast, if a cell is configured into logic 1,
the intermediate result in the same row is abandoned in OR
operations. Therefore, the cells in OR arrays require to be con-
figured into logic 1 or logic 0 according to the Section III-A.
Each output requires an inverter to get final result. The final
results in Fig. 4(a) are obtained at out1, out2, and out3 as
follows, whereby AND–OR logic functions can be realized.
out1 = (out1 + 0) · (out2 + 0) · (out3 + 1)
= ABC + ABC (16)
out2 = (out1
+ 0) · (out2 + 1) · (out3 + 0)
= ABC + ABC (17)
out3 = (out1 + 1) · (out2 + 0) · (out3 + 0)
= ABC + ABC. (18)
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

When the logic operations are performed in the arrays, the out
lines in the rows involved in logic operations are charged and
other out lines are not charged. The voltage V R lower than
Vth1 is used as the input voltage to perform the executi on step,
and it would not change the state of cells. Therefore, only the
out lines involved in logic operations can be discharged in the
executi on step.
2) OR–AND Logic PLA: As shown in Fig. 4(b), the PLA
consists of two NOR arrays, instead of using data in the form
of resistances as operands, voltages at i n1, i n2, and i n3 are
used as operands. The arrays should be configured to realize
different logic functions. The states of cells in NOR arrays-1
are configured to select proper input voltages as operands
according to (6). If a cell is configured into logic 0, the input
voltage in the same column is selected as an operand. If a
cell is configured into logic 1, the input voltage in the same
column is abandoned. As mentioned in Section III-A, different
states can be set into the cells to realize the target functions.
Therefore, we can obtain the intermediate results. For example,
out1 , out2 , and out3 can be obtained as follows:
out1 = i n1 · i n2 = i n1 + i n2
out2 = i n2 · i n3 = i n2 + i n3
out3 = i n1 · i n3 = i n1 + i n3.
Similarly, out1 , out2 , and out3 are used as inputs to get
final results in NOR arrays-2. NOR arrays-2 are configured to
select proper intermediate results to perform logic operations
as same as the mentioned earlier. Therefore, the final results
in Fig. 4(b) are obtained at out1, out2, and out3 as follows,
whereby OR–AND logic functions can be realized:
out1 = (out1 + 0)(out2 + 0)(out3 + 1)
= (i n1 + i n2)(i n2 + i n3)
out2 = (out1 + 0)(out2
+ 1)(out3
= (i n1 + i n2)(i n1 + i n3)
out3 = (out1 + 1)(out2 + 0)(out3
= (i n2 + i n3)(i n1 + i n3).
F. Bit Full Adder
Based on the OR-AND logic, a one-bit full adder can be
realized in the PLA built with CCC as shown in Fig. 5(a).
The CCC is simplified as shown in Fig. 5(b). The typical
one-bit full adder function equations are shown as follows:
S = A ⊕ B ⊕ Ci n
Cout = AB + (A ⊕ B)Ci n
they can be expressed with maxterms as follows:
S = (A + B + Ci n)(A + B + Ci n)
×(A + B + Ci n)(A + B + Ci n)
Cout = (A + B + Ci n)(A + B + Ci n)
×(A + B + Ci n)(A + B + Ci n).
Therefore, the one-bit full adder can be realized with two
NOR arrays in III-E2. As shown in Fig. 5(a), each cell is
configured into logic 0 or logic 1. If the cell is configured
(19)
(20) Fig. 5. One-bit full adder.
(21)
into logic 0, the input voltage is selected as an operand. If the
cell is configured into logic 1, the input voltage is abandoned.
The NOR array-1 is used to obtain the logic NOT of required
maxterms, the NOR array-2 is used to select required logic
NOT of maxterms to form results according to (27) and (28).
In [5], [21], and [22], the full adder is realized in the
memristor-based or CRS-based crossbar arrays. Due to their
pure memristive structure, the area of circuits is smaller than
(22) the traditional CMOS circuits. However, the well-designed
+ 0) sequencer is required to realize complex logic functions, which
(23) may incur high delays for logic operations and complicate
peripheral circuits design. In [5], [21], and [22], the required
+ 0)
sizes of arrays for the one-bit full adder are 8 × 1, 9 × 1,
(24) and 4 ×9 respectively, and 15, 19, and 23 steps are required to
realize the one-bit full adder, respectively. Although the sizes
of the full adder (8 × 7) in Fig. 5(a) is larger than the full
adder in [5], [21], and [22], two execution steps are required
to realize the computation after configuring the PLA.
G. Memory Built With CCC
(25) Instead of using for logic operations, the CCCs can be
used to realize the nonvolatile memory as shown in Fig. 6.
(26) To perform the write operations, conventional CRS write
schemes can be directly adopted [15]. For example, to write
logic 0 (1) into A, Vth2 (-Vth2) and GND are applied at the
column line col1 and the row line r 1, respectively. For other
(27) rows (r 2 and r 3), the isolation voltage are applied at them to
protect the states of cells from the destruction. Due to the same
structure, the write operations can be used to configure the
(28)
cells into logic 1 or logic 0 in the PLA in Fig. 4, whereby
different logic functions can be realized.
Different from conventional CRS destructive read
schemes [7], the CRS cells may be switched into an
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WANG et al.: CONFIGURABLE LOGIC OPERATIONS USING HYBRID CCCs
Fig. 6. Simplified memory built with CCC.
TABLE I
S IMULATION PARAMETERS
unstable state during reading, and an extra write back
operation is required to turn the CRS into its original state
after reading. Our scheme for reading is nondestructive and
parallel as mentioned in III-B. There are two steps during the
reading process: pr echarge and executi on. For example,
to read A, B, and C parallelly, row lines should be precharged
selectively to Vcharge . Row lines out1, out2, and out3 are
precharged to Vcharge and other rows are not be charged.
Then the executi on step is performed by applying V R at the
column line col1. The CRS is regarded as the voltage divider
to activate the transistor, and its state determines whether
the transistor discharge the out lines to the ground or not as
mentioned at III-B. Therefore, we can obtain logic values of
A, B, and C parallelly by detecting the state of out1, out2,
and out3.
IV. S IMULATION
In this section, the simulations of logic operations are pre-
sented. We adopt the memristor model presented in [23] and
45-nm CMOS PTM model [24] to carry out the simulations,
and the simulation parameters are presented in Table I.
A. Delay of Precharging and Discharging
Fig. 2(a) is used as an example to evaluate the delay of
precharging and discharging. When the voltage of out rises to
90% of Vcharge , the pr echarge step is completed. We assume
the transistor has a diffusion capacitance Cdiff , a pull-down
resistance Rpd , and the precharge circuit of n-bit cells has
an equivalent resistance Req . Therefore, the time constant
of the precharging circuit is tpre = n Req Cdiff . The delay of
precharging increases when the number of cells increases.
As for discharging, we assume that the discharging is
completed when the voltage of out falls to the 50% of
Vcharge , and the time constant of the discharging circuit,
5
TABLE II
D ELAY OF P RECHARGE AND D ISCHARGE
Fig. 7. Simulation of precharging and discharging with different bits in the
worst case.
tpre = (n/m)Cdiff Rpd and m is the number of activated tran-
sistors. Therefore, the largest discharging pull-down resistance
is obtained when only one transistor is activated, which gives
the longest discharging delay.
The time delay of n-bit cells is shown in Table II. As can be
seen, the increment of bits gives a larger equivalent diffusion
capacitance, causing an increment of charging or discharging
delay. Besides, the simulation for out in the worst case is
presented in Fig. 7. Vcharge and V R are used in pr echarge and
executi on steps, respectively. There are voltage overshoots
when V R is applied to activate the transistor. The voltage
increment of out results from the capacitance between gate
and drain of the transistor, this capacitance acts as a boost
capacitance to increase the voltage of out. The voltage over-
shoots can be alleviated by increasing the number of cells due
to the filtering function of capacitors in nonactivated transistors
as shown in Fig. 7. Using the precharging and discharging
delay time, the timing for logic operations can be designed
properly.
B. Simulations of IMPLY and AND Operations
The IMPLY operation is realized with the cell presented
in Fig. 2(a). The operands of IMPLY operations are i n, and
the state of A and the result is obtained at out in form
of voltages. The simulations of the IMPLY operation are
presented in Fig. 8. After the pr echarge step out rises to
Vcharge , then the voltage at i n and the state of A (X and Y )
determine whether the transistor is activated to discharge out
to ground. When i n = 1 and A = 0, out is discharged to
ground as shown in Fig. 8(c), and out keeps at the high-voltage
state in the rest of the cases.
The AND operation is realized via the cascade of
multiIMPLY operations as mentioned earlier. The circuit
in Fig. 3(a) is adopted as an example in our simulations.
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 8. Simulation of IMPLY operations.
Fig. 9. Simulation of AND operations.
As shown in Fig. 9, when A, B, and C all store logic 1,
out holds at the high voltage as shown with the curve out 1
in Fig. 9. If any of A, B, and C stores logic 0, out is discharged
to ground as shown with the curve out 0 in Fig. 9.
C. Comparison
In [13], [21], [25], and [26], IMPLY-based and MAGIC
logic gates are presented to realize in-memory logic operations
in pure memristor crossbar arrays. Due to the sneak-path
currents, it is hard to guarantee the correctness of results when
multiple logic operations are performed parallelly even though
some schemes are presented to alleviate this situation [22].
In [5] and [14], logic operations performed in CRS-based
crossbar arrays are presented to reduce the impact of sneak-
path currents. It is similar to [13], [21], and [25], complicated
operations sequences are necessary to realize target logic
functions, which may cause longer delay and aggravate the
complexity of peripheral circuits. In addition, the CRS-based
logic involves reading and sensing the intermediate data during
execution.
Compared with previous logic families, logic operations
based on CCC have their advantages and disadvantages. The
hybrid CMOS-memristive structure requires more area than
the pure memristive circuits, and operating voltages require
the careful planning to suit for memristors and CMOS. Even
so, logic operations based on CCC can be executed in a simple
configurable way in arrays of CCC without the requirement
of long execution sequences, which simplifies the peripheral
circuits. The sneak-path currents have no impact on the logic
operation, and multiple logic operations can be performed
TABLE III
C OMPARISONS OF D IFFERENT T ECHNOLOGIES . F: F EATURE S IZE ,
T: T RANSISTOR , C: C APACITOR , AND R: R ESISTIVE
D EVICE (M EMRISTOR )
parallelly. Besides, the memory built with CCC can realize
the nondestructive read compared with the memory built with
CRS. The comparison of different technologies is presented
in Table III, CCC can be used to perform logic operation
compared with the cells in SRAM, DRAM, and FLASH.
Although the CRS arrays have relative higher data storage
density than the arrays built with CCC, nondestructive reading
can be realized in the memory built with CCC. The arrays
built with CCC have relative higher data storage density
compared with SRAM and Akers arrays. The hybrid CCCs
are more compatible with COMS technology and memristors
technology.
V. C ONCLUSION
In this paper, new memory cells built with CCC are pre-
sented to realize several logic operations, including IMPLY,
IMPLY-AND, AND, AND, OR, and OR, whereby PLA are
built with CCC to perform complex logic operations in a
simple configurable way. The verification for the feasibility
of our scheme is presented with HSPICE simulations. Our
scheme opens an opportunity for additional memristor-CMOS
integrated circuits and provides a convenient method to realize
logic computation designs.
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Xiaoping Wang (M’14) was born in Huangmei,
China, in 1974. She received the B.S. and M.S.
degrees in automation from Chongqing University,
Chongqing, China, in 1997 and 2000, respectively,
and the Ph.D. degree in systems engineering from
the Huazhong University of Science and Technology,
Wuhan, China, in 2003.
Since 2011, she has been a Professor at the
School of Automation, Huazhong University of Sci-
ence and Technology. Her current research interests
include memristors and its application to memory
storage, modeling, simulation, and optimization.
Shuai Li received the B.E. degree from the School
of Automation and Electrical Engineering, Jinan
University, Guangzhou, China, in 2015. He is cur-
rently working toward the M.E. degree at the School
of Automation, Huazhong University of Science and
Technology, Wuhan, China.
His current research interests include memristor-
based memory technology.
Zhigang Zeng (SM’13) received the Ph.D. degree in
systems analysis and integration from the Huazhong
University of Science and Technology, Wuhan,
China, in 2003.
He is currently a Professor at the School of
Automation, Huazhong University of Science and
Technology, and also with the Key Laboratory of
Image Processing and Intelligent Control, Ministry
of Education China, Wuhan, China. He has authored
over 100 international journal papers. His current
research interests include theory of functional differ-
ential equations and differential equations with discontinuous right-hand sides,
and their applications to dynamics of neural networks, memristive systems,
and control systems.
Dr. Zeng has been a member of the Editorial Board of Cognitive Compu-
tation since 2010, Neural Networks since 2012, and Applied Soft Computing
since 2013. He was an Associate Editor of the IEEE T RANSACTIONS ON
N EURAL N ETWORKS from 2010 to 2011 and has been an Associate Editor
of the the IEEE T RANSACTIONS ON C YBERNETICS since 2014 and the IEEE
T RANSACTIONS ON F UZZY S YSTEMS since 2016.