3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

PIPELINED CORDIC ARCHITECTURE AND ITS IMPLEMENTATION ON

SIMULINK
Shalini Rai, C.K.Dwivedi, Rajeev Srivastava
Department of Electronics & Communication, University of Allahabad, Allahabad (UP), India
shaliniece_04@yahoo.com
ckdwivedi@gmail.com
rajeev_jk@rediffmail.com

Abstract- Coordinate Rotation Digital Computer (CORDIC)
algorithm is very useful algorithm for the designing of low
cost and efficient VLSI circuit’s at large scale. It may be
suitable for the generation of trigonometric functions,
multiplication of complex numbers, matrix inversion and
finding the solution of linear equations. The CORDIC
algorithm has also been employed in calculation of sine and
cosine values. The sine & cosine values are used in various
transform of Digital Signal processing like z transform and in
communication system. There are different ways to generate
the sin & cosine values. These conventional methods require a
huge memory space. A good quantization level is required for
large memory. So CORDIC algorithm based sine & cosine
waves’ generation has been used because its flexibility
characteristics and low quantization error. In this paper some
pipelined CORDIC structures are presented for generation of
sine and cosine values, multiplication, division of two numbers
and finding out square root or arctangent values. These
structures have been implemented and results observed by
using simulink of MATLAB.
Keywords: CORDIC algorithms, trigonometric functions,
pipelined CORDIC architecture
I: Introduction
There are several advancements in the research area of
VLSI architecture for the real time Digital signal
processing. In 1959 Volder has described an algorithm
called Coordinate Rotation digital computer (CORDIC) [1,
8] .It is simply a set of algorithm by using only shift and add
operations. It is used for improving the speed of VLSI
circuits. In 1971 walther [2, 9] has given new algorithm for
computations in different coordinate system like
circular, linear and hyperbolic using the CORDIC algorithm
which has discovered by Volder.
During last 50 years the CORDIC algorithm has been used
in wide area of applications. It is used as a single
functional unit named as CORDIC Processor for DSP
applications. Applications are linear transformations, FIR,
IIR, lattice filters and matrix based signal processing [3, 4],
singular value decomposition (SVD), matrix inversion,
complex number multiplications,eigen value decomposition,
solution of linear system, generation of trigonometric
functions, fourier and related transform and image
processing. With the advancement in VLSI technology the
applications of CORDIC algorithm are expanded to the field
of biomedical sciences, neural net-work, and radio
communication. CORDIC algorithm has also been used
for computing machine applications like HP-2152, HP- 9100
and HP-35. As time passes there are various advancement
take place in VLSI technology. With use of advanced
CORDIC algorithm provided higher performance and cost
reduction hardware solutions for real time applications of a
two dimensional rotations and transcendental functions. A
new improved algorithm has been developed. It is called
fast rotations or orthonormal μ-rotations over a set of fixed
angles. This improved algorithm is used for finite impulse
response filter for image processing, 3D graphics and simple
generation of spherical rays. The main drawback of
CORDIC algorithm is a large no of iteration which affects
the system. There are several methods like angle-recording
(AR), modified vector rotation, mixed scaling rotation
(MSR) and scaling free CORDIC algorithms have been
proposed for reduction of no of iteration, improving the
system performance and speed up the system.
The CORDIC algorithm based different architecture has
taken place for implementing different applications
based on different coordinate system. CORDIC
architectures are required a high signal to noise ratio, high
throughput, reduced hardware complexity and latency. So for
the improvement of throughput and reduction of complexity
of hardware the parallel and pipelined CORDIC architecture
can be used. The CORDIC architectures will be used in
several applications are direct frequency synthesis, digital
communication, robotics manipulation and graphics and
animation. In this paper, our purpose is to implement the basic
CORDIC Algorithm with the pipelined CORDIC architecture by
using the simulation tool simulink (MATLAB) for calculating
the trigonometric values. Simulink is originated by Mathwork
which is a graphics based programming language. It is used for
making the model of any circuits and these models are simulated
and analyzed by the simulink. In simulink any circuits is
designed by the use of graphical block and a customizable set of
block libraries. The rest of this paper is organized as in following
manner. In section II describes the arithmetic of CORDIC
Algorithm .In section III – the Different architectures of
CORDIC algorithm have been discussed. The implementation of
the CORDIC Algorithm has been discussed in section IV, and
conclusions along with future aspects are described in section V.

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 3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

II: Arithmetic of CORDIC Algorithm

Number system of CORDIC Algorithm
There are two types of number system is used in CORDIC,
the non redundant and redundant number system. A non
redundant radix λ number system has the set {0, 1, λ-1} and
all numbers can be uniquely represented. The CORDIC
which is designed by non redundant number system, the
carry propagation delay is occurred in addition. For the
reduction of carry propagation delay we use the redundant
binary number system. There are two common redundant
binary number system in CORDIC arithmetic which are
signed–digit (SD) and carry-save (CS) number system [12,
13]. In radix 2, SD number system is represented with digits
{-1, 0, 1}. In carry save number system, numbers are
represented with digit set {0, 1, 2}.In λ radix SD number
system the digit set is [-β,-β+1,…-1,0,+1,…..,α],where α ≤ (λ-
1) and (1≤β≤(λ-1)).In the conventional CORDIC
architectures, we use the non redundant CORDIC arithmetic.
The Generalized CORDIC Equations:
The basic iterative formulas of CORDIC can be: For i = 0, 1,
2, --------n-1[10]
x(i+1) = x(i) - m* σi*y(i)* λ-s(m,i) (3)
y(i+1) = y(i) + σi*x(i)* λ-s(m,i) (4)
z(i+1) = z(i) – σi*am(i) (5)
m is an integer
m = +1 Circular Rotation
m = -1 Hyperbolic Rotation
m=0 Linear Rotation
{σi} refers to the mode of CORDIC in which it is used.
It depends on whether the CORDIC algorithm is in
which rotational mode.
(a) Rotation mode
(b) Vectoring mode
For vectoring mode
σ(i) = +1 if yi < 0 (8)
-1 otherwise
λ indicates the radix of the number system .
λ=2 for radix 2
λ=4 for radix 4
s(m, i) is a non- decreasing integer shift sequence. The given
relation is satisfied by the s(m, i).
s(m, i) ≤ s(m , i+1) ≤ s(m, i) + 1 (9)
and is uniquely chosen for every m value.
The angle rotated in the ith iteration is
am (i) = m-1/2 tan-1[m 1/2 λ-s (m, i ) ] (10)
am(i) is dependent on both m and λ.
The convergence of the algorithm depends on the non
decreasing integer shift sequence, which affects the accuracy
of the final results.
This is not the necessary that the final output vector which is
obtained by the required micro rotations, are accurate. There is
some increment in the vector length. To maintain the constant
vector length, scaled the output result by the factor K which is
called the scale factor
K= Пki (11)
ki= √1+mσ2(i)λ2-s(m,i)
ki denotes the elementary scaling factor of the ith iteration. K is
the final scaling factor after the n iteration.
III: CORDIC Architectures
CORDIC ARCHITECHTURE – CORDIC Architectures can
be classified in two categories folded and unfolded based
upon three iterative difference equations.

σ(i) = sign(zi) for rotation mode (6)

-sign (yi) for vectoring mode CORDIC
ARCHITECHTURE

For rotation mode FOLDED UNFOLDED

σ(i) = -1 for zi < 0 (7) (9)

+1 otherwise

2 SERIAL PARALLEL
 3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

PIPELINED
WORD
fig1: Flow chart of CORDIC architecture
SERIAL

Folded Architecture [17]: Folded architecture is realized
into a single hardware functional unit by using the three
equations of CORDIC algorithm and time multiplexing. The
folded CORDIC architecture can be divided into bit serial
architecture and word serial architecture.
parallel architecture is very high. It uses the shift- add/sub
operations in parallel using an array of shift-add/sub stages.
This architecture is more efficient and reliable than serial
architecture.

Bit Serial Architecture: In this architecture one bit is used in a

each iteration for hardware implementation. The basic
CORDIC block contains three simple adder/subtractor and
two shift registers with a ROM containing a look –up
table.ROM contains the fixed angles for the particular
coordinates system in which CORDIC architecture
implemented. It is a slow down architecture because it uses n
clock for every single calculations. For every micro rotation a
one clock cycle is required. After n clock cycle the o/p is
obtained. The throughput of serial design is (clock
rate)/(number of iterations*word length).

Word Serial Architecture: In word serial architecture one word

is used in a each iteration for the functional unit fig2: Folded architecture
implementations.

Unfolded Architecture [17]: In unfolded architecture the

one iteration output is the input of the next iteration cycle.
If there are n iteration cycles, so n stages of three difference
equations are implemented into hardware. We get the high
throughput of this architecture by the elimination of read
only memory. The unfolded architectures can be divided
into two categories first is the pipelined architecture and
second is the parallel architecture,

Pipelined CORDIC [15, 17]: Pipelined CORDIC contains n

stages of CORDIC blocks which are cascaded. It has fixed
shift registers at every steps of pipelined architecture and
performs fixed number of shifts every time. It contains at each
steps to store the fixed angle for the particular rotations at
every CORDIC block. Each block performs a single micro –
rotation. i.e ith steps performs single micro-rotation. The
pipelined CORDIC Architecture is faster than serial
architecture, and doesn’t require a look –up table. Pipelining
is used to reduce the critical path so that the system speed
may be faster. It may be used in adaptive filters, discrete fig3: Unfolded architecture
orthogonal transforms, sinusoidal wave generation and other
signal processing applications.

Parallel CORDIC [17]: In this architecture the iterative

CORDIC is combined multiples times. The latency of parallel
architecture is only one clock cycle. The throughput of
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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

Fig5: Parallel architecture

In this paper the pipelined CORDIC Architecture implemented
by using simulink which are developed by Mathwork
(MATLAB).We developed the Pipelined CORDIC Processor
with nine stages for the calculation sine cosine values by using
the CORDIC algorithm in rotation mode , circular rotation and
set the initial x value=1/k, y=0, z=desired angle. Square root
Fig4: Pipelined architecture value and tangent values was calculated by using pipelined
CORDIC architecture with CORDIC algorithm in vectoring
mode, circular rotation and set the initial x value =1, y=2,
z=0.Multiplication and division of two values was calculated
by pipelined CORDIC architecture with CORDIC algorithm in
rotation mode, linear rotation, set the initial x value=1/k, y=0,
z=2 and vectoring mode, linear rotation, set initial x value =2,
y=1, z=0 respectively. Polar to rectangular conversion
implemented by using the Pipelined CORDIC Architecture,
having circular rotation and rotation mode with initial x value
=r*1/k, y=0, z=desired angle. Summary of CORDIC also have
been discussed.

Summary of CORDIC Algorithm [10, 11]

Rotation Mode σi= sign(zi), zi→0 Vectoring Mode σi = sign(-yi), yi→0

Mode Angle Applications Mode Angle Applications

m=1 circular am(i)= Xi+1= k(x0 cosz- y0sinz0) m=1 circular am(i) = Xi+1= k√x02+y02

tan-1(2-i) Yi+1= k (x0 sinz0+y0cosz0) tan-1(2i) Yi+1= 0

Zi+1= 0 Zi+1= z0+tan-1(y0/x0)

For sin,cos set x0= 1/k For tan-1 set x0=1,z0= 0,

tanz=sinz/cosz, k=1.646….. cos-1 θ= tan-1(√1-θ2/θ)

Sin-1θ= tan-1(θ/√1-θ2)
-i -i
m=0 linear am(i)= 2 Xi+1= x0 m=0 linear am(i)= 2 Xi+1= x0

Y+1= y0+x0z0 Yi+1=0

Zi+1= 0 Zi+1= z0+y0/x0

For multiplication set y0=0 For division set z0=0

m= -1 am(i)= Xi+1= k’(x0 coshz0-yosinhz0) m=-1 am(i)= Xi+1=k’√x02+y02

Hyperbolic tanh-1(2-i) Yi+1= k’(x0sinz0+yocosz0) Hyperbolic tanh-1(2-i) Yi+1=0

Zi+1=0 Zi+1 =z0+tan-1(y0/x0)

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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

For sinh,cosh set x0=1/k’ For tanh-1 set x0=1 ,z0=0

tanhz= sinhz/coshz Cosh-1θ= tanh-1(√1-θ2/θ)

ez =sinhz+coshz Sinh-1θ= tanh-1(θ/√1-θ2)

wt= et lnw, k’= 0.828… lnθ= 2 tanh-1(θ-1)/(θ+1)]

√θ= √(θ+1/4)2-(θ-1/4)2

IV: Implementation of CORDIC Algorithm

A: Calculation of sin and cosine of angle 60 degree

x0 = 0.6073, y0 = 0, z0 = 60 degree

We get the result x= cosθ = cos 60 = 0.4939

y= sinθ = sin60= 0.8696
Calculated value cos 60= 0.5 and sin60 = 0.866
Percentage Error in cosine value=
(Simulated Value- Calculated value)*100/Calculated value= fig6: The Adder/Subtractor Logic Subsystem [18]
(0.4939-0.5)*100/0.5= -0.0122*100= -1.22%
Percentage Error in Sine value= (0.8696-0.866)*100/0.866=
0.004*100=0.4%

x0=1, y0=2, z0= 0

We get the result

x= k√x2+y2 =1.646 √12+22 = 3.682
z= z+tan-1(y/x) = 0+tan-1(2/1)= 63.17

Calculated value k √12+22=3.680 and tan-1(y/x) = 63.43

fig7: Implementation of single CORDIC iteration [18]

B. Calculation of Square Root and tan-1 Values

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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

D. Calculation of Division of two numbers

x0=2, y0=1, z0=0

We get Result x= x=2

z= z+y/x=0.4926

Calculated division value= = y/x= ½=0.5

Percentage Error= (0.4926- 0.5)*100/0.5= -0.015*100= -1.5%

Percentage Error in Square Root Value

= (3.682-3.680)*100/3.680 =0.00054*100 = 0.05%
E. Polar to Rectangular Conversion
Percentage Error in tan-1 Value x0=2*0.6073,y0=0,z0=30
= (63.17-63.43)*100/63.43= - 0.0041*100 = - 0.4%
We get the result
C. Calculation of Multiplication of two Numbers x=r*cosθ = 1.739
y=r*sinθ =0.9878
x0= 0.6073,y0= 0,z0=2
Percentage Error in x= (1.739-1.732)*100/1.732=
We get Result x= x=0.6173, y= xz= 1.212 0.0040*100=0.4%

Calculated multiplication value= 0.6073*2=1.2146

Percentage Error in y = (0.9878- 1)*100/1
Percentage Error= (1.212-1.2146)*100/1.2146 =-0.0122*100= -1.2%
= -0.0021*100= -0.2%

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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

Fig8: Pipelined architecture of CORDIC for sine and cosine

Fig9: Pipelined architecture of CORDIC for square root and tan-1

fig10: Pipelined architecture of CORDIC for multiplication

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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

fig11: Pipelined architecture of CORDIC for division

fig12: Pipelined architecture of CORDIC for the conversion from polar to rectangular

V: Results & Conclusions

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3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

Square,tan1, - done
Functions Actual value Simulated Percentage
value Error Multiplication, - done
Division

Sine (angle=60°) 0.866 0.8696 0.4% Polar to rectangular - done

Cosine(angle=60°) 0.5 0.4939 -1.22%

Square 3.680 3.682 0.05% In this paper we discussed about the CORDIC Algorithm and
root(x0=1,y0=2,z0=0) its implementation by using the MATLAB R2009a simulink
tool. We have implemented the sine, cosine, tan-1,
Tan-1(x0=1,y0=2,z0=0) 63.43 63.17 -0.4%
multiplication, division applications of CORDIC Algorithm
with reduced no of iteration. Sine and Cosine Values was
Multiplication 1.2346 1.232 -0.2%
(x0=0.6173,y0=0,z0=2) derived by using the CORDIC Algorithm in rotation mode and
Division 0.5 0.4926 -1.5% circular rotation .Tan-1 & square root values was derived by
(x0=2,y0=1,z0=0) using CORDIC algorithm in vectoring mode and circular
Polar to Rectangular x=r*cosθ 1.768 0.4% rotation. Similarly Multiplication was derived by using
(x0=2*0.6173,y0=0,z0=30) CORDIC Algorithm in linear rotation and rotation mode.
=1.732 1.004 -1.22% Division was derived by using CORDIC Algorithm in linear
y= r*sinθ=1 rotation and vectoring mode. These applications are used in the
wireless applications and mobile communications and also
Comparison with previous work [18] used in software defined radio services. Also future work the
HDL code can be generated from the simulink graphical
Functions Previous work Present work
program, HDL code can be generated by XILINX software and
No of iterations 12 9 implemented on FPGA kit.

Sine, cosine done done

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