GATE SOLUTIONS

E L E C T R O N I C S AN D C O M M U N I CAT I O N

From (1987 - 2017)

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Second Edition : 2017

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 PREFACE

It is an immense pleasure to present topic wise previous years solved paper of GATE Exam.
This booklet has come out after long observation and detailed interaction with the students
preparing for GATE exam and includes detailed explanation to all questions. The approach has
been to provide explanation in such a way that just by going through the solutions, students will
be able to understand the basic concepts and will apply these concepts in solving other questions
that might be asked in future exams.

GATE exam now a days has become more important because it not only opens the door for
higher education in institutes like IIT, IISC, NIT's but also many of the PSUs have started
inducting students on the basis of GATE score. In PSU’s, which are not inducting through GATE
route, the questions in their exams are asked from GATE previous year papers. Thus, availability
of authentic solutions to the students is the need of the day. Towards this end this booklet
becomes indispensable.

I am thankful to IES master team without whose support, I don't think, this book could have
been flawlessly produced.

Every care has been taken to bring an error free book. However comments for future improvement
are most welcome.

Mr. Kanchan Kumar Thakur

Director Ex-IES
 CONTENTS

1. Network Theory .......................................................................................... 01–124

2. Signal and Systems .................................................................................. 125–232

3. Electronic Devices .................................................................................... 233–310

4. Analog Electronics .................................................................................... 311–440

5. Digital Circuits ........................................................................................... 441–540

6. Microprocessor ......................................................................................... 541–566

7. Control Systems ....................................................................................... 567–692

8. Communications ....................................................................................... 693–822

9. Electromagnetics ...................................................................................... 823–952

10. Mathematics ........................................................................................... 953–1012

11. General Aptitude ................................................................................... 1013–1048

 Network Theory
1UNIT

Syllabus
Network solution methods : nodal and mesh analysis; Network theorem; superposition,
Thevenin and Norton’s, maximum power transfer; Wye-Delta transformation; Steady
state sinusoidal analysis using phasors; Time domain analysis of simple linear circuits;
solution of network equations using Laplace transform; Frequency domain analysis of
RLC circuits; Linear 2-port network parameters: driving point and transfer functions;
State equations for network

CONTENTS
1. Basics of Network Analysis ----------------------------------------------------- 01–24

2. DC Transients and Steady State Response -------------------------------- 25–66

3. Resonance ---------------------------------------------------------------------------- 67–75

4. Network Theorems ---------------------------------------------------------------- 76–95

5. Two Port Networks --------------------------------------------------------------- 96–114

6. Network Functions and Network Synthesis ---------------------------- 115–120

7. Network Graphs ----------------------------------------------------------------- 121–124

 Chapter 1
Basics of Network Analysis
4
I
+ 2I +
V2 5A 4 4 V1
1. A connection is made consisting of resistance – –
A in series with a parallel combination of
resistances B and C. Three resistors of the
(a) 5V, 25V (b) 10V, 30V
value 10  , 5  , 2  are provided. Consider
all possible permutations of the given (c) 15V, 35V (d) 0V, 20V
resistors into the positions A, B, C, and
[GATE 2015]
identify the configurations with maximum
possible overall resistance, and also the ones 4. In the circuit shown, the switch SW is
with minimum possible overall resistance. thrown from position A to position B at time
The ratio of maximum to minimum value t = 0. The energy  in J  taken from the
of the resistances (upto second decimal 3V source to charge the 0.1 F capacitor
place) is __________ from 0V to 3V is
SW
+3V 120 B A
[GATE-2017]
2. In the network shown in the figure, all t=0

resistors are identical with R  300  . The 0.1F

resistance Rab (in  ) of the network is
_____. (a) 0.3 (b) 0.45
a (c) 0.9 (d) 3
R
[GATE 2015]
R R R R R
R R R 5. In the circuit shown, the average value of
R=300
the voltage Vab (in Volts) in steady state
R R
Rab R R R R condition is _____
b 1k 1F 1mH 2k
b a

[GATE 2015] + Vab +

– – 5V
5sin(5000t )
3. In the given circuit, the values of V1 and V2
respectively are [GATE 2015]
 NETWORK THEORY 3
6. At very high frequencies, the peak output (c) Data is sufficient to conclude that the
voltage V0(in Volts) is _____ supposed currents are impossible.
100 F (d) Data is insufficient to identify the
+
currents i2, i3 and i6. [GATE 2014]
1k 1k V0 10. In the figure shown, the value of the current
100 F
I (in Amperes) is ______.
+ –
1.0sin(t)V
– 5 5
I
1k 1k
5V 1A 10
100 F

[GATE 2015] [GATE 2014]

7. In the circuit shown, the voltage Vx (in Volts) 11. The circuit shown in the figure represents a
is _____
A1Ii
0.5V X Ii R

10
+ (a) voltage controlled voltage source
A VX 20 8 0.25VX
– (b) voltage controlled current source
[GATE 2015]
(c) current controlled current source
8. The magnitude of current (in mA) through
(d) current controlled voltage source
the resistor R2 in the figure shown is ____.
R2 [GATE 2014]

1k 12. Consider a delta connection of resistors and

its equivalent star connection as shown
10mA R1 2k R 3 4k 2mA below. If all elements of the delta connection
are scaled by a factor k, k > 0, the elements
R4
of the corresponding star equivalent will be
3k scaled by a factor of
[GATE 2014]
9. Consider the configuration in the figure which Ra RC RB
is a portion of a larger electrical network. Rb Rc
RA
i5
(a) k2 (b) k
i2
(c) 1/k (d) k
R R
i3 [GATE 2013]
R 13. The average power delivered to an
i4
i1 i6 impedance  4  j3   by a current
5cos 100t  100  A is
For R  1  and currents i1  2 A , i4 = –1 A,
i5 = –4A, which one of the following is TRUE ? (a) 44.2 W (b) 50 W
(a) i6 = 5 A (c) 62.5 W (d) 125 W
(b) i3 = –4A [GATE 2012]

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 4 GATE SOLVED PAPER 1987-2017
14. The impedance looking into nodes 1 and 2 M
in the given circuit is 1
L1 L2
Ib

1k 99Ib 2
9k (a) L1 + L2 + M (b) L1 + L2 – M
1
100  (c) L1 + L2 + 2M (d) L1 + L2 – 2M
2
[GATE 2004]
(a) 50  (b) 100 
18. The dependent current source shown in
(c) 5  (d) 10.1k given figure
5
[GATE 2012]
15. A fully charged mobile phone with a 12 V V1 = 20 V 5 V 1/5A
battery is good for a 10 minute talk-time.
Assume that, during the talk-time, the
(a) delivers 80 W (b) absorbs 80 W
battery delivers a constant current of a 2 A
and its voltage drops linearly from 12 V to (c) delivers 40 W (d) absorbs 40 W
10 V as shown in the figure. How much [GATE 2002]
energy does the battery deliver during this 19. The Voltage e0 in the figure, is
talk-time? 4 2
v(t)
+
12 V 12V + e0
4 2
–
–
10V
4
(a) 2 V (b) V
t 3
0 10 min (c) 4 V (d) 8 V
(a) 220 J (b) 12 kJ [GATE 2001]
(c) 13.2 kJ (d) 14.4 kJ 20. If each branch of a Delta circuit has
[GATE 2009] impedance 3 Z, then each branch of the
16. In the interconnection of ideal sources equivalent Wye circuit has impedance
shown in the figure, it is known that the 60 Z
V source is absorbing power. (a) (b) 3 Z
3
+–
Z
20 V (c) 3 3 Z [GATE 2001]
(d)
I +
– 60V 3
12A 21. In the given circuit, the voltage v(t) is
Which of the following can be the value of 1 1
the current source I? +
(a) 10 A (b) 13 A eat A v(t) 1H ebtA

–
(c) 15 A (d) 18 A
[GATE 2009] (a) eat  ebt (b) eat  ebt
17. The equivalent inductance measured
(c) aeat  bebt (d) aeat  bebt
between the terminals 1 and 2 for the circuit
shown in the figure is [GATE 2000]

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10 GATE SOLVED PAPER 1987-2017

1 Mark 22. (a) 13. (c)

1. (2.14) 23. (b) 14. (d)
2. (100) 24. (c)
15. (c)
3. (a) 25. (b)
16. (a)
4. (c) 26. (a)
17. (a)
5. (5) 27. (d)
18. (c)
6. (0.5) 28. (a)
29. (d) 19. (b)
7. (8)
30. (a & d) 20. (a)
8. (2.8)
9. (a) 2 Marks 21. (None of these)

10. (0.5) 1. (a) 22. (d)

11. (c) 2. (1) 23. (d)
12. (b) 3. (d) 24. (d)
13. (b) 4. (5)
25. (d)
14. (a) 5. (–1A)
26. (b)
15. (c) 6. (1.5)
27. (b)
16. (a) 7. (20)
28. (d)
17. (d) 8. (29.09)
18. (a) 9. (2.504) 29. (a)

19. (c) 10. (10) 3 Marks

20. (a) 11. (0.4083) 1. (c)
21. (d) 12. (2.618)

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 NETWORK THEORY 11

Solutions

[Here, branch ‘pqrs’ is removed as no

current flows through it, because it forms
Sol–1: a balanced bridge]
 Req =  2R    2R   R  R
A
R
= R R R = 100
3
Sol–3: (a)
B C 4 x
+ I +
(1)
V2 5A 4 4 2I V1

Resistor are 2, 5 and 10 – –

For maximum resistance B = 2, C = 5, A = 10
80 Applying nodal analysis at node (1), we
Rmax = get
7
for minimum resistance, x x
5 =   2I
A = 2, B = 5, C = 10 4 4
2x x
16  5 =
4
 2
4
x  4I
Rmin =
3  x = 5
Rmax (80 / 7)
= Now,V1 = 5V  x  V1 
Rmin (16 / 3)
= 2.14 V1  5  4  V2 = 0
[KVL in the outermost loop]
Sol–2: (100)
 V2 = 5 + 5 × 4 = 25 V
Sol–4: (c)
R RR R R R
R eq R R R Initially capacitor is uncharged. For t > 0,
R R
the circuit will be :
R R R R
120 
3V
i(t) R
(R=300 )
C 0.1 F
R R/2 R/2 R
R R R
R eq p r s
q
R R/2 R/2 R Current in RC circuit while charging is
given by :
V0  t/RC
i(t) = e where V0 = 3V
R
R eq 2R R R 2R Power delivered by the source = P
= 3i(t) [ P = V.I]

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 12 GATE SOLVED PAPER 1987-2017
t t By voltage division rule
Also, Energy =  Pdt   3i  t  dt
0 0
0.5
V0 = V
Capacitor gets fully charged at steady 0.5  0.5
state i.e t   . V

V0  t/RC V0 =
2
 E =  3. e dt
0
R 1
V0 = 1.0sin  t 
3V0  1   2
=  e  t/RC 0
R 1 RC   V0 = 0.5sin  t 
 0
= 3V0C e  e   V0 peak = 0.5 Volts
= 3  3  0.1 0  1J Sol–7: (8)
E = 0.9 J 0.5V X
Sol–5: (5)
• For AC input voltage 5 sin 5000t  ,
voltage across capacitor (C) at steady P 10
state is also sinusoidal, whose average +
value is zero. 5A VX 20 8
• For DC voltage = 5V, at steady state 0.25VX
–
capacitor behaves as open circuit and
Apply KCL at point P
inductor behaves as short circuit,
therefore circuit is Vx Vx  0.25Vx
  0.5Vx  5
b a 20 10
1K –V + 2K
ab
5V
 1 75 1
Vx    5
 20 1000 2 
Vab=5V
Average value of voltage across  1 3 1
Vx    5
capacitor is Vab = 5V.  20 40 2 
Sol–6: (0.5)  2  3  20 
Vx  5
At very high frequencies, capacitor  40 
behaves as short-circuit.
1 5
Vx    5
 XC = jC 8
When    , X C  0[short circuit]  Vx = 8 Volts
When all capacitors are replaced by Sol–8: (2.8)
short-circuit.
Transforming current sources into
voltage sources, we get
1K  1 K V0
1k
1.0sin(t)

1K  1K 2k 4k

i
20V +
– 8V

0.5 K V0
3k
1.0sin( t) V
20  8
0.5K i = = 2.8 mA
2  1  4  3 k
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 NETWORK THEORY 13
Sol–9: (a) +

i5
Vi Ii AVVi R
A
i2
–
1 R 1 Voltage controlled voltage source
R i3
B R +
i4 C
1 i6
i1
Vi Ii GmVi R
Given,

R  1 , i1  2A , i4 = –1A, i5 = –4A –
Applying KCL at node B, Voltage controlled current source
+
i 4  i1  i 2 = 0
i2 = i1  i 4  2  1  1A Vi Ii RmI i R
Applying KCL at node A,
–
i5  i 2  i3 = 0
Current controlled voltage source
i3 = i 2  i 5  1  4  3A Sol–12: (b)
Applying KCL at node C, Ra
i 3  i 6  i1 = 0
RC RB
i6 = i1  i 3  2   3   5A
Rb RA Rc
Sol–10: (0.5)
5 a 5
I
To convert delta to star
5V 1A 10
RaR b
RC = R  R  R
a b c
Applying KCL at node a, if they are factor by k so
Va  5 Va kR a kR b
 1 = 0
5 15 R´C = kR  kR  kR
a b c
3  Va  5   Va = 15
kR a R b
4Va = 30 R´C = R  R  R
a b c
Va = 7.5V
R´C = k Rc
Va 7.5
 I =   0.5A So they are also factored by k.
15 15
Sol–11: (c) Sol–13: (b)
The average power delivered to a complex
impedancy R  jX is given by
Ii AIIi R Pavg = I2rms R
2
 5 
=    4 = 50 W
Current controlled current source
 2
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 14 GATE SOLVED PAPER 1987-2017
Sol–14: (a) For absorbing power by 60 V,
ib I – 12 < 0
So I < 12A
99ib
1 K Sol–17: (d)
D M
9K
I
1 + 1
100 V L1 L2
2 –

Let voltage across 1, 2 is V and current 2

through it is I. Since the flux in both coil is opposing, so
mutual inductance will be negative
V = i b  9000  1000 
compared to self inductance.
V = –10000ib Net inductance = L1  M  L 2  M
Applying KCL at point D
= L1  L 2  2M
V Sol–18: (a)
ib + I + 99ib =
100 5 i1 V1/5 A
V V
I = +
100 100 +
V1 = 20V 1 5 V1/5 A
V – –
I =
50
And the impedance equivalent will be
given by Apply KVL in loop 
1 ,
V
= Z  50   V 
I V1  5i1  5  i1  1   0
Sol–15: (c)  5 
Energy dissipated = V.I.t Joules [V in  i1 = 0A
volts, I in ampere, t in seconds] So, voltage across 5 resistor
Here, the graph of V – t is given. The = 5 × 4 = 20 V
area under V – t graph will give the So power delivered by current source
product of V & t. [V in Volts and t in
= 20 × 4 = 80 Watts
seconds]
Note : If current in a resistor flows from
 Energy dissipated = [Area under low voltage to high voltage then it is
graph] × I
delivering power (applicable for both
1 voltage source or current source).
=  12  10   10  60  2 Joules
2
Sol–19: (c)
= 11  10  60  2 Joules
4 2
Energy Dissipated = 13.2 kJ
+
Sol–16: (a)
12V 4 e0 2
20 V
–
+–

+ 60 V Req = 4  4  4  6 
I
–
(I–12) 12
I =  2A
6
12A
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