Lahore University of Management Sciences

EE/CS-320 – Computer Organization and Assembly Language

Fall Semester 2013-14
Instructor Shahrukh Athar
rd
Room No. Room 9-349A, Department of Electrical Engineering (Right Wing), 3 Floor, SBASSE Building, LUMS
Office Hours Tue-Thu 02:00 pm to 04:00 pm
Email shahrukh.athar@lums.edu.pk
Telephone Direct: 042-35608423; LUMS Extension: 8423
TA (s) TBA
TA Office Hours TBA
Course URL (if any) Learning Management System (LMS)
Course Basics
Credit Hours Total: 4 (Theory: 3; Lab: 1)
Lecture(s) Nbr of Lec(s) Per Week 2 Duration 75 minutes
Lab(s) Nbr of Lab(s) Per Week 1 Duration 180 minutes
Recitation/Lab (per week) Nbr of Lec(s) Per Week -- Duration --
Tutorial (per week) Nbr of Lec(s) Per Week 1 Duration 90 minutes
Course Distribution
Core Core for CS Majors of SSE
Elective Elective for EE Majors of SSE or for students from other majors who fulfill the Pre-Requisite requirement
Open for Student Category
Close for Student Category
COURSE DESCRIPTION

Modern computer technology requires professionals of every computing specialty to understand both hardware (HW) and
software (SW). The interaction between HW and SW also offers a framework for understanding the fundamentals of computing.
In this course students will study topics such as Instruction Set Architecture, Basic Assembly Instructions, Addressing Modes,
Computer Performance evaluation, Floating Point Data, Data Path Design for Single Cycle and Multiple Cycle Computers, Pipelined
Data Path Basics, Hazards in Pipelining, Memory hierarchy design, storage and I/O. The Lab will have focus on MIPS Assembly Level
Programming and some HW experiments. The course will have one comprehensive design project in which students will design and
implement an 8-bit MIPS architecture based processor using HW components.

COURSE PREREQUISITE(S)

 1. EE/CS-220 Digital Logic Circuits, AND

 2. CS-200 Introduction to Programming
 Talk to the instructor if you are unsure about the background needed to take this course.

COURSE OBJECTIVES AND LEARNING OUTCOMES

To learn:
  The link: High-Level Language (For example C Language)  Assembly Language (such as MIPS Assembly)
  Machine Language.
  The language of the computer using the MIPS Assembly Language as an example.
 The arithmetic of the computer.
 The design of a basic 5-stage single cycle Processor.
 The design of a basic 5-stage pipelined Processor.
 Data and Control hazards in pipelining.
 Memory hierarchy Design.
 Storage and I / O.
 Working as team players in a group of engineering students in designing and implementing a
comprehensive hardware project.
 Lahore University of Management Sciences
Grading Breakup and Policy

Quiz(s): 15%
Assignment(s): 3%
Lab(s): 12% (Lab Quiz(s): 2%, Lab Attendance and Task Completion: 10%)
Project: 15%
Midterm Exam: 25%
Final Exam: 30%

Examination Detail
Yes/No: Yes
Combine Separate: Combine
Midterm
Duration: 180 minutes
Exam
Preferred Date: At the beginning of Mid-Term Exam period
Exam Specifications: Close-Book/Close-Notes/Calculator Allowed
Yes/No: Yes
Combine Separate: Combine
Final Exam Duration: 180 minutes
Preferred Date: At the beginning of Final Exam period
Exam Specifications: Close-Book/Close-Notes/Calculator Allowed
Textbook(s)/Supplementary Readings/Programming Environment
Textbook (TB):
 “Computer Organization and Design: The Hardware / Software Interface” by David A. Patterson and John L. Hennessy
th
(4 Edition)

Reference Books (RB):

th
1. “Computer Organization and Architecture” by William Stallings (8 Edition)
th
2. “Computer Organization” by Carl Hamacher, Zvonko Vranesic and Safwat Zaky (5 Edition)
3. “MIPS Assembly Language Programming” by Robert L. Britton

Programming Environments:
1. PCSPIM MIPS Assembly Language Simulator
2. Visual MIPS Simulator

Tutorials, Attendance & Policies

 There may be some tutorials (if required)

 Attendance is strongly recommended as lectures will build upon the material covered in previous lecture(s). There may
also be surprise quizzes.
 Policies:
 Two class quizzes will be dropped. There cannot be any makeup quiz.
 Assignments will be due at the beginning of the class on the due date. Late Assignments will not be accepted.
 The project will be divided into modules and each module will have a specific deadline. Late module submission may
either result in a penalty or may not be accepted at all.
 All instances of cheating will be dealt with strictly in accordance with university rules.

Re-Grading Deadlines

 Any contests of Assignments, Quizzes, Labs, Mid-term Exam and Final Exam must be resolved within 2 days of the
return of the graded item (No exceptions).
 Lahore University of Management Sciences
COURSE OVERVIEW
Recommended Objectives/
Module Topics Sessions
Readings Application

Introduction
1  History and System Level View 2 CH-1 TB Basic introduction of the course
 Some important design considerations

Language of the Computer

 Operation and Operands of HW
 Signed and Unsigned Numbers
 Representing Instructions in the Computer
 Logic Operations
To learn the basics of the MIPS
 Instruction for Making Decisions
2  Supporting Procedures in HW (Stack)
6 CH-2 TB Assembly Language and
practice its programming
 Addressing Modes
 Intro to Compilers
 A Sort procedure and its assembly
 Pointers versus Arrays

Arithmetic for Computers

To learn the hardware used by
 Addition and Subtraction (ALU Design)
CH-3 TB computers to perform Integer
3  Multiplication and Division 3 Topic C.5 TB Arithmetic and the basics of
 Floating Point Arithmetic Floating Point Arithmetic

CPU Performance Factors

4 1 Sec. 1.4 TB CPU Performance Factors

The Processor (Single Cycle) To build a basic MIPS 5-Stage

Single Cycle Processor by using
 Building a Datapath
5  Simple Implementation Scheme (Control)
2 CH-4 TB the HW tools learnt already and
which fulfills the Instruction Set
requirements of Module-2
Mid Term Examination
The Processor (Pipelined) To incorporate Pipelining
 Pipelined Datapath and Control into the Processor designed
 Introduction to Stalling and Forwarding CH-4 TB in Module-5. To learn the
6  Data Hazards and Control Hazards
5 CH-8 RB2 various issues that arise due
 Exceptions to pipelining and techniques
that resolve these issues.
Memory Hierarchy Design To understand the concepts
 A Top Level View of Cache Memory, Main
 Cache Memory CH-5 TB
7  Main Memory
5 CH-4,5 RB1
Memory, Virtual Memory
and to introduce the design
 Virtual Memory of memory hierarchy.
Storage, Input / Output and OS Support
To learn about various
 Storage Devices
CH-6 TB Storage Devices and topics
8  I / O Topics 4 CH-6 to 8 RB1 pertaining to I/O
 Introduction to OS Support
(Input/Output)
(Module-8 is subject to availability of time)
Final Examination
 Lahore University of Management Sciences

Computer Organization and Assembly Language Lab

For lab work a lab manual will be provided to the students at the beginning of each lab, that carries the detail of the lab work to be
performed in that lab session and related instructions to perform the given tasks. The students will be required to fill their lab
manuals according to instructions given in the manual and announced by the Instructor/TAs during the lab session. The students will
also be required to return their lab manuals to the TAs at the end of each lab session since these manuals will not be accepted later.

 Labs 1 & 7 will introduce some HW components necessary for the semester project.
 Labs 2 to 6 & 8 will cover various aspects of MIPS Assembly Language using the PCSPIM Simulator.
 Labs 9 & 10 will illustrate single cycle and pipelined processors using the Visual MIPS Tool.
(The Visual MIPS Tool has been developed by Dr Jahangir Ikram at LUMS).

LAB OVERVIEW
No Lab Topic Week

1 HW Lab: Using ROM, RAM and ALU IC chips (Revision of HW used in EE/CS-220 DLC) 2

2 Introduction to PCSPIM MIPS Assembly Language Simulator and basic Assembly instructions 3

3 Control instructions, Pseudo instructions and arrays 4

4 System Calls and Procedure Calls 5

5 Using the Stack. Multiplication and Division in the MIPS Assembly Language 6

6 Recursion (Factorial) and Sorting in MIPS Assembly Language 7

7 HW Lab: Using a Register File 9*

8 Using the MIPS Floating Point Architecture in PCSPIM 10*

9 Introduction to MIPS Instruction Set Architecture using Visual MIPS Tool (Single Cycle/Pipelined Processor) 11*

10 Introduction to Data Hazards and Branch Hazards using the Visual MIPS Tool 12*

* Subject to the Eid-ul-Azha Holidays