Low Power CMOS Design

Prepared BY
Swapna Sarker
Specialization:VLSI
Role No. 194571

Supervisor
Dr. M. Satish
Assistant Professor
 Abstract
Rapid increase in technology for faster & smarter innovations that
smoothness the needs of humans resulting in use of super technology
in modern age. To meet the increasing demands, the size of electronic
devices is getting reduced. Also, the need to save power arises which
reduces the equipment for cooling process and maintenance. Where
Low power has emerged as a principal theme in today’s modern
electronics world.
Power dissipation has become an important & prime consideration
as performance & area for VLSI chip design. Where CMOS
technology is the key element in the development of VLSI systems
since it consumes less power. Due to wince in the size of device,
reduction in power consumption and over all power management on
the chip are the key challenges. In order to cut down package cost &
to extend battery life, power optimization is important in many designs.
But at the same time, leakage current also plays a momentous role in
low power VLSI design. Leakage current is becoming an increasingly
significant fraction of the total power dissipation of integrated circuits.
This paper describes various techniques that can be used to reduce
the power consumption of CMOS.
 Introduction
In the past decades, the prime focus of VLSI designers were performance,
area and design cost. Power consumption was usually of only secondary
importance relatively. Nevertheless, this trend has begun to change and, with
major priority, power consumption is given comparable importance to speed and
area. The benefit of utilizing combination of low power design techniques in
conjunction with low-power components is more valuable now.

The main sources that are related to power dissipation are:

(1) Capacitive power dissipation due to the charging and discharging of the load
capacitance.

(2) Short circuit currents due to the existance of a conducting path between the
voltage supply.

(3) Leakage current.

The leakage current forms of reverse-bias diode currents and subthreshold currents.
The former is because of the stored charge between the drain and bulk of active
transistors whereas the latter is due to the carrier diffusion between the source and drain
of the OFF transistors as shown in Fig-1.