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Schem, MLB, Kepler, 2phase, D2: Schematic / PCB #'S
Schem, MLB, Kepler, 2phase, D2: Schematic / PCB #'S
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2012-05-09
www.qdzbwx.com SCHEM,MLB,KEPLER,2PHASE,D2
FSB, 5/9/2012
TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
46 High Side and CPU/AXG Current Sensing D2_SEAN
TABLE_TABLEOFCONTENTS_ITEM
91 PCH Constraints 1 D2_KEPLER
2 01/13/2012 55 03/05/2012 103 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
2 System Block Diagram D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
47 Thermal Sensors D2_SEAN
TABLE_TABLEOFCONTENTS_ITEM
92 PCH Constraints 2 D2_KEPLER
3 01/13/2012 56 01/13/2012 105 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
3 Power Block Diagram D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
48 Fan Connectors D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
93 Thunderbolt Constraints D2_KEPLER
4 01/13/2012 57 01/13/2012 106 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
4 Revision History D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
49 KEYBOARD/TRACKPAD (1 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
94 SMC Constraints D2_KEPLER
5 01/13/2012 58 01/13/2012 107 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
5 BOM Configuration D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
50 KEYBOARD/TRACKPAD (2 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
95 GPU (Kepler) CONSTRAINTS D2_KEPLER
6 01/13/2012 59 01/13/2012 108 03/15/2012
TABLE_TABLEOFCONTENTS_ITEM
6 BOM Variants D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
51 DIGITAL ACCELEROMETER & GYRO D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
96 Project Specific Constraints D2_CLEAN
7 01/13/2012 61 01/13/2012 109 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
7 Functional / ICT Test D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
52 SPI ROM D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
97 PCB Rule Definitions D2_KEPLER
8 01/13/2012 62 03/16/2012 130 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
8 Power Aliases D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
53 AUDIO: CODEC/REGULATOR D2_CARA
TABLE_TABLEOFCONTENTS_ITEM
98 DEBUG SENSORS AND ADC D2_SEAN
9 01/13/2012 63 03/16/2012 132 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
9 Signal Aliases D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
54 AUDIO: HEADPHONE FILTER D2_CARA
TABLE_TABLEOFCONTENTS_ITEM
99 SMC12 SENSORS EXTENDED D2_KEPLER
10 01/13/2012 64 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
10 CPU DMI/PEG/FDI/RSVD D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
55 AUDIO: IV SENSE D2_CARA
11 01/13/2012 65 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
11 CPU CLOCK/MISC/JTAG D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
56 AUDIO: IV SENSE FILTER D2_CARA
12 01/13/2012 66 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
12 CPU DDR3 INTERFACES D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
57 AUDIO: SPEAKER AMP D2_CARA
13 01/13/2012 67 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
13 CPU POWER D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
58 AUDIO: JACK D2_CARA
14 01/13/2012 68 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
14 CPU POWER AND GND D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
59 AUDIO: JACK TRANSLATORS D2_CARA
16 03/05/2012 69 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
15 CPU DECOUPLING-I D2_SEAN
TABLE_TABLEOFCONTENTS_ITEM
60 DC-In & Battery Connectors D2_KEPLER
17 03/05/2012 70 01/13/2012
16 CPU DECOUPLING-II D2_SEAN 61 PBus Supply & Battery Charger D2_KEPLER
C
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
17
18
19
PCH SATA/PCIe/CLK/LPC/SPI D2_KEPLER
01/13/2012
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
62
71
72
System Agent Supply D2_KEPLER
01/13/2012
01/13/2012
C
TABLE_TABLEOFCONTENTS_ITEM
18 PCH DMI/FDI/PM/Graphics D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
63 5V / 3.3V Power Supply D2_KEPLER
20 01/13/2012 73 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
19 PCH PCI/USB/TP/RSVD D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
64 1V5R1V35V DDR3 SUPPLY D2_KEPLER
21 01/13/2012 74 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
20 PCH GPIO/MISC/NCTF D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
65 CPU IMVP7 & AXG VCore Regulator D2_SEAN
22 03/19/2012 75 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
21 PCH POWER D2_CLEAN
TABLE_TABLEOFCONTENTS_ITEM
66 CPU IMVP7 & AXG VCore Output D2_SEAN
23 01/13/2012 76 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
22 PCH GROUNDS D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
67 CPU VCCIO (1V0R1V05 S0) POWER SUPPLY D2_KEPLER
24 03/19/2012 77 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
23 PCH DECOUPLING D2_CLEAN
TABLE_TABLEOFCONTENTS_ITEM
68 Misc Power Supplies D2_KEPLER
25 01/13/2012 78 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
24 CPU & PCH XDP D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
69 Power FETs D2_KEPLER
26 01/13/2012 79 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
25 Chipset Support D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
70 Power Control 1/ENABLE D2_KEPLER
27 01/13/2012 80 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
26 USB HUB & MUX D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
71 KEPLER PCI-E D2_KEPLER
28 01/13/2012 81 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
27 CPU Memory S3 Support D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
72 KEPLER CORE/FB POWER D2_SEAN
29 01/13/2012 82 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
28 DDR3 SDRAM Bank A (1 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
73 KEPLER FRAME BUFFER I/F D2_SEAN
30 01/13/2012 83 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
29 DDR3 SDRAM Bank A (2 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
74 1V05 GPU / 1V35 FB POWER SUPPLY D2_SEAN
31 01/13/2012 84 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
30 DDR3 SDRAM Bank B (1 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
75 GDDR5 Frame Buffer A D2_SEAN
32 01/13/2012 85 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
31 DDR3 SDRAM Bank B (2 OF 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
76 GDDR5 Frame Buffer B D2_SEAN
33 01/13/2012 86 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
32 DDR3 Termination D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
77 KEPLER EDP/DP/GPIO D2_SEAN
34 01/13/2012 87 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
33 DDR3/FRAMEBUF VREF MARGINING D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
78 KEPLER GPIOS,CLK & STRAPS D2_SEAN
35 01/13/2012 88 03/05/2012
34 X29/ALS/CAMERA CONNECTOR 79 KEPLER PEX PWR/GNDS
B TABLE_TABLEOFCONTENTS_ITEM
35
36
Thunderbolt Host (1 of 2)
D2_KEPLER
D2_KEPLER
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
80
89
GFX IMVP VCore Regulator
D2_SEAN
D2_SEAN
03/05/2012 B
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
37 01/13/2012 90 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
36 Thunderbolt Host (2 of 2) D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
81 eDP Display Connector D2_KEPLER
38 01/13/2012 91 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
37 Thunderbolt Power Support D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
82 eDP Mux D2_SEAN
44 01/13/2012 92 03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
38 RIO CONNECTOR D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
83 eDP Muxed Graphics Support D2_SEAN
45 01/13/2012 94 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
39 SSD CONNECTOR D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
84 Thunderbolt Connector A D2_KEPLER
46 01/13/2012 96 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
40 USB 3.0 CONNECTORS D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
85 Thunderbolt Connector B D2_KEPLER
49 01/13/2012 97 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
41 SMC D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
86 LCD Backlight Driver (LP8545) D2_KEPLER
50 01/13/2012 98 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
42 SMC Support D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
87 PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER
51 01/13/2012 99 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
43 LPC+SPI Debug Connector D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
88 Power Sequencing EG/PCH S0 D2_KEPLER
52 01/13/2012 100 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
44 SMBus Connections D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
89 CPU Constraints D2_KEPLER
53 03/05/2012 101 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
45 Voltage & Load Side Current Sensing D2_SEAN
TABLE_TABLEOFCONTENTS_ITEM
90 Memory Constraints D2_KEPLER
A A
DRAWING TITLE
SCHEM,MLB,KEPLER,2PHASE,D2
DRAWING NUMBER SIZE
Schematic / PCB #’s Apple Inc. 051-9589 D
REVISION
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
4.18.0
051-9589 1 SCHEM,MLB,KEPLER_2PHASE,D2 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
820-3332 1 PCBF,MLB,KEPLER_2PHASE,D2 PCB CRITICAL PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
TITLE=MLB III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
ABBREV=ABBREV
LAST_MODIFIED=Wed May 9 13:50:52 2012 IV ALL RIGHTS RESERVED 1 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J2500,J2550
PG 73
PG 9
J3100
J2900
www.qdzbwx.com
2 DIMMS
DDR3-1067/1333MHZ
DIMM
D PG 26,28
J6950
D
DC/BATT POWER SUPPLY
PG 63
PG 19 PG 17 PG 17 PG 16 U4900
U6100
SPI
Boot ROM TEMP SENSOR
U2700 CLOCK
Misc PG 55
CK5G05 CLK
PG 44
PG 19
PG 24
BUFFER POWER SENSE
PG 44
PG 16
J5650,5660
5
SATA2.0/3(GB/S)
PG 16
ODD SATA
4
SATA2.0/3(GB/S)
CONN
PG 41
SATA INTEL J5100 Ser
B,0 BSB ADC Fan
LPC + SPI CONN
3
SATA2.0/3(GB/S) Prt
PANTHER-POINT SMC
J4500
PG 16 Port80,serial
LPC PG 46 PG 44
MOBILE
2
SATA2.0/3(GB/S) U4900
HDD SATA
C CONN PG 16
C
1
SATA3.0/6(GB/S)
PG 41
U1800
0 SATA3.0/6(GB/S)
U3600 J3402
PWR CAMERA
PG 31
CTRL
DP OUT
J4501
PG 17 USB IR
U9320 PG 41
RGB OUT
9 10 11 12 13
HDMI OUT PG 33
XP25-5G
PG 83
DVI OUT PG 33 EXTERNAL C
(RESERVATION) PG 33
LVDS OUT
(UP TO 14 DEVICES)
8
J9400 TMDS OUT
7
U3700 J5713
PG 18
USB
PG 18 TRACKPAD/KEYBOARD
6
PG 53
MINI DP PORT
5
4
PG 84 USB J3401
PCI BLUETOOTH
3
PG 31
HUB 1
2
PG 18
1
J4600
0
EXTERNAL A
U9370 PG 34 PG 34
B DDC MUX
JTAG
SMB
B
PG 16 SMBUS
PG 16
PG 83
CONNECTION
PCI-E HDA PG 47
PEG
(UP TO 16 LINES)
PG 16
PG 16 PG 16
DIMM
U9600
U6201
AUDIO
GMUX
CODEC
PG 86 PG 56
U6610,6620,6630
U4100
U3900
GB
A J3401
FW643
E-NET
LINE TIN
FILTER
HEADPHONE
FILTER
SPEATKER
AMP SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
BCM57765 PAGE TITLE
PG 38 PG 57 PG 58 PG 59
PG 36 System Block Diagram
AirPort DRAWING NUMBER SIZE
D F6905
6A FUSE R7020
PPBUS_G3H
SMC_ONOFF_L D
U5001
AC DCIN(16.5V) 8A FUSE SMC_GPU_VSENSE R7640
ADAPTER A VIN
U7000
PPVBAT_G3H VIN
V PPCPUVTT_S0
IN
SMC_DCIN_ISENSE
ISL6259HRTZ
VOUT PP5V_S3_GFXIMVP6_VDD VDD VOUT A PPVCORE_GPU PP5V_S0_CPUVTTS0
VIN
1.05V
VOUT
A
GPU VCORE SMC_CPU_FSB_ISENSE
U5410 ISL95870 TPS22924
PBUS SUPPLY/ ISL6263C U7600 U4202 PP1V0_FW_FWPHY
SMC_GPU_ISENSE
SMC_RESET_L
BATTERY CHARGER
R7050 A U8900
CPUVTTS0_EN
EN
PGOOD
CPUVTTS0_PGOOD (PAGE 39)
EN
VR_ON PGOOD
SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 70)
FW_PWR_EN
(PAGE 64) (PAGE 82)
SMC_CPU_VSENSE
J6950
Q7055
R5388/U5388
V
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R CPU VCORE
SMC_CPU_HI_ISENSE
A VOUT
A PPVCORE_S0_CPU
PANTHER_POINT PM_PWRBTN_L
(9 TO 12.6V)
VIN PWRBTN#
ISL95831
3S2P
SMC_CPU_ISENSE
SYS_RERST#
CPUIMVP7_VR_ON U7400
CHGR_BGATE VR_ON
RSMRST#
PGOOD CPUIMVP7_AXG_PGOOD
(PAGE 67) ACPRESENT
www.qdzbwx.com PM_PCH_PWRGD
PS_PWRGD PLTRST#
PLT_RERST_L
U1800 CPU_PWRGD
PROCPWRGD
C GMUX
PB16B
EG_RAIL1_EN P1V1GPU_EN
U5440
DRAMPWROK
PM_MEM_PWRGD C
EG_RAIL2_EN P3V3GPU_EN U2850 (PAGE 16~21)
PB17A PP5V_S3_DDRREG SMC_CPU_DDR_VSENSE
U9600
PB17B
EG_RAIL3_EN GPUVCORE_EN
R7350
XP25-5 PB18A
EG_RAIL4_EN
VIN VLDOIN
SMC_DDR_ISENSE
V
PM_ALL_GPU_PGOOD DDRREG_EN 1.5V PPDDR_S3_REG PP1V5_S3
(PAGE 86)
PL32A
P1V0GPU_EN
EN1 VIN
VOUT1
PP1V0_S0GPU_REG
DDRVTT_EN
S5 VOUT1
A
S3 0.75V PPVTT_S0_DDR_LDO
1.003V(L/H) R5413 VOUT2 SM_DRAMPWROK
PP1V5_GPU_REG CPU
SMC
P1V5FB_EN
EN2
1.503V(R/H)
VOUT2
A SMC_GPU_1V8_ISENSE
TPS51116
U7300 PGOOD
DDRREG_PGOOD 4.5V PP4V5_AUDIO_ANALOG U1000 VCCCPUPWRGD
VIN MAX8840
(PAGE 66) VOUT
EN U6200
U4900 ISL6236 POK1
P1V0GPU_PGOOD
RESET*
PP3V3_S0 (PAGE 9~14)
RC P3V3S5_EN U9500 PP1V5_S3
P60 POK2
P1V5FB_PGOOD Q7860
DELAY (PAGE 85) Q7801
SMC_PM_G2_EN P1V5CPU_EN PP5V_S0
(PAGE 44) VIN PP1V5_S3RS0
ON G
SLG5AP020
U7801
VIN VREG5 P5VS0_EN
P5VS3_EN PP5V_S3 P1V5S0FET_GATE
EN1 VOUT1
PANTHER-POINT 5V
PM_ALL_GPU_PGOOD
(L/H)
MOBILE PP3V3_S5 PP3V3_S5
PM_SLP_S5_L
P3V3S5_EN VOUT2 U7980
SLP_S5#(E4) EN2 3.3V PP1V8_S0 SMC
Q9806 (R/H) ALL_SYS_PWRGD
Q7880
B RC P5VS3_EN TPS51125
U7201
Q7870
PP3V3_S0GPU
P1V8FB_EN
ON
VIN
G
PP1V8_GPUIFPX PWRGD(P12)
(P64)
SMC_ADAPTER_EN B
DELAY SLG5AP020
(PAGE 65) RSMRST_PWRGD
U7880 RSMRST_IN(P13) PM_RSMRST_L
RSMRST_OUT(P15)
PGOOD
RC DDRREG_EN BKLT_PLT_RST_L P1V8GPUIFPXFET_GATE SMC_ONOFF_L 99ms DLY
PWR_BUTTON(P90) CPUIMVP_VR_ON
DELAY
&& VIN P3V3GPU_EN IMVP_VR_ON(P16)
A RC
DELAY
P1V8S0_EN
P5VS0_EN
PP1V2_S0 TRST = 200mS SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
RC P1V2S0_EN Power Block Diagram
DELAY VIN P1V2S0_EN DRAWING NUMBER SIZE
P3V3S0_EN P1V2ENET_EN ISL8014A PP1V2_ENET
EN
U7760
VOUT
Apple Inc. 051-9589 D
RC CPUVTTS0_EN P1V2ENET_PGOOD REVISION
(PAGE 70) PGOOD R
DELAY
PBUSVSENS_EN
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
RC P1V5CPU_EN THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
DELAY THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE
BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_BOMGROUP_ITEM
PART NUMBER
085-3726 D2,MLB,KEPLER,DEV D2_DEVEL:ENG 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3V] CRITICAL EEEE:DY3V TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
128S0257 128S0264 ALL Kemet alt to Sanyo
085-4776 D2,MLB,KEPLER,FSB DEV D2_DEVEL:FSB 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3W] CRITICAL EEEE:DY3W TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
353S3527 353S3528 ALL Pericom eDP MUX
TABLE_BOMGROUP_ITEM
353S3526 353S3528 ALL TI eDP MUX
685-0016 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 PBUS_CAP:KEMET 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY40] CRITICAL EEEE:DY40 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0855 376S0613 ALL Diodes alt to Toshiba
685-0017 PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2 PBUS_CAP:SANYO 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY43] CRITICAL EEEE:DY43 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0855 376S0613 VREFDQ:M1_M3 ALL Diodes alt to Toshiba
TABLE_BOMGROUP_ITEM
825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY45] CRITICAL EEEE:DY45
376S0903 376S0796 ALL Fairchild alt to Siliconix
TABLE_ALT_ITEM
D
639-3380 PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY4C] CRITICAL EEEE:DY4C TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0977 376S0859 ALL Diodes alt to Toshiba
TABLE_BOMGROUP_ITEM
376S1053 376S0604 ALL Diodes alt to Fairchild
TABLE_BOMGROUP_ITEM
128S0311 128S0329 ALL NEC alt to Sanyo
TABLE_BOMGROUP_ITEM
138S0739 138S0706 ALL Samsung alt to Murata
TABLE_BOMGROUP_ITEM
197S0434 197S0343 ALL Epson Alt to TXC
TABLE_BOMGROUP_ITEM
197S0435 197S0343 ALL NDK Alt to TXC
TABLE_BOMGROUP_ITEM
197S0432 197S0431 ALL NDK Alt to Epson
TABLE_BOMGROUP_ITEM
197S0452 197S0181 ALL Epson Alt to TXC
TABLE_BOMGROUP_ITEM
197S0453 197S0181 ALL NDK Alt to TXC
TABLE_BOMGROUP_ITEM
685-0017 685-0016 ALL Sanyo POSCAP/Mylar alt to Kemet
TABLE_BOMGROUP_ITEM
376S0975 376S1081 ALL Toshiba alt to diodes
TABLE_BOMGROUP_ITEM
371S0709 371S0652 ALL NXP alt to infineon
TABLE_BOMGROUP_ITEM
371S0713 371S0558 ALL DDS alt to ST
TABLE_BOMGROUP_ITEM
377S0126 377S0066 ALL New Semtech package
TABLE_BOMGROUP_ITEM
377S0147 377S0066 ALL On Semi alt to Semtech
TABLE_BOMGROUP_ITEM
152S0461 152S1645 ALL Cyntec alt to Vishay
Programmables
376S1080
155S0667
376S0820
155S0583
ALL
ALL
Diodes alt to On Semi
TABLE_BOMGROUP_ITEM
341S3584 1 IC,TRKPD/KYBD CNTRLR,DVB,D2 U5701 CRITICAL TPAD_PSOC:PROG 107S0232 107S0129 ALL Cyntec alt to TFT
TABLE_BOMGROUP_ITEM
337S2983 1 IC,TP PSOC,QFN,BLANK U5701 CRITICAL TPAD_PSOC:BLANK 197S0466 197S0464 ALL Epson alt to NDK
TABLE_BOMGROUP_ITEM
341S3597 1 IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2 U3690 CRITICAL TBTROM:PROG 341S3564 341S3565 ALL Avnet eDP MUX alt to Renesas
BOM GROUP BOM OPTIONS 341S3565 1 IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2 U9100 CRITICAL DPMUXMCU:PROG
TABLE_BOMGROUP_ITEM
D2_COMMON1 CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO
TABLE_BOMGROUP_ITEM
DRAM VREF Configs
D2_COMMON2 EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
BOM GROUP BOM OPTIONS
D2_PVB VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:PROD VREFDQ:M1_M3,VREFCA:LDO
D2_PROGPARTS SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:ENG_M3 VREFDQ:M1_M3,VREFCA:LDO_DAC
D2_DEVEL:ENG ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:ENG_LDO VREFDQ:M1_DAC,VREFCA:LDO_DAC
D2_DEVEL:FSB ALTERNATE,IVB_PPT_XDP
IVB_PPT_XDP XDP_CONN,XDP_PCH
TABLE_BOMGROUP_ITEM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_BOMGROUP_ITEM
639-2818 PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF0] CRITICAL EEEE:DRF0 Elipda DQ’d
TABLE_BOMGROUP_ITEM
639-2820 PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDP] CRITICAL EEEE:DRDP Keeping for PRQ
D 639-2823 PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600
TABLE_BOMGROUP_ITEM
C C
B B
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
BOM Variants
DRAWING NUMBER SIZE
TRUE NC_SMC_FAN_3_TACH
FUNC_TEST TRUE AUD_HP_PORT_R 53 54 58 TRUE SMBUS_SMC_5_G3_SCL 41 44 CPU NO_TESTs
J3501 - airport FUNC_TEST J5100 - lpc + spi I1733
TRUE AUD_SPDIF_OUT_JACK 53 58
I1760
TRUE SMBUS_SMC_5_G3_SDA 41 44 NO_TEST
TRUE NC_SMC_FAN_3_CTL
I1735 I1761
I1596 TRUE AP_CLKREQ_Q_L 34 I1652 TRUE LPCPLUS_GPIO 20 43 TP_CPU_RSVD<65..62> TRUE NC_TP_CPU_RSVD<65..62> TRUE NC_SMC_FAN_2_TACH
I1734 TRUE AUD_TIPDET_INV 59 I1763 TRUE SYS_DETECT_L 60 MAKE_BASE=TRUE
I1597 TRUE AP_RESET_CONN_L 34 I1655 TRUE LPCPLUS_RESET_L 25 43 TP_CPU_RSVD<58..45> TRUE NC_TP_CPU_RSVD<58..45> TRUE NC_SMC_FAN_2_CTL
I1736 TRUE AUD_TYPEDET 58 59 TRUE GND 8X GND MAKE_BASE=TRUE
I1599 TRUE PCIE_AP_D2R_PI_N 34 92 I1656 TRUE LPC_AD<0> 17 41 43 82 TP_CPU_RSVD<43..32> TRUE NC_TP_CPU_RSVD<43..32> TRUE NC_FW2_TPBP
92
I1738 TRUE CH_HS_GND 4X 58 MAKE_BASE=TRUE
I1600 TRUE PCIE_AP_D2R_PI_P 34 92 I1658 TRUE LPC_AD<1> 17 41 43 82 TP_CPU_RSVD<27..26> TRUE NC_TP_CPU_RSVD<27..26> TRUE NC_FW2_TPBN
92
I1737 TRUE CH_HS_MIC 58 MAKE_BASE=TRUE
TRUE PCIE_AP_R2D_N 34 92 TRUE LPC_AD<2> 17 41 43 82 TP_CPU_RSVD<24..15> TRUE NC_TP_CPU_RSVD<24..15> TRUE NC_FW2_TPBIAS
I1601
TRUE PCIE_AP_R2D_P 34 92
I1659
TRUE LPC_AD<3>
92
17 41 43 82
I1740 TRUE PP3V3_S0 7 8 96 J9000 - eDP TP_CPU_RSVD<2..1>
MAKE_BASE=TRUE
TRUE NC_TP_CPU_RSVD<2..1> TRUE NC_FW2_TPAP
I1602 I1657
US_HS_GND DP_INT_AUX_N
92
I1739 TRUE 4X 58 I1762 TRUE 81 95 MAKE_BASE=TRUE
I1603 TRUE PCIE_CLK100M_AP_CONN_N 34 96 I1661 TRUE LPC_CLK33M_LPCPLUS 25 43 92 TP_CPU_RSVD_NCTF<8..5> TRUE NC_TP_CPU_RSVD_NCTF<8..5> TRUE NC_FW2_TPAN
I1741 TRUE US_HS_MIC 58 I1764 TRUE DP_INT_AUX_P 81 95 MAKE_BASE=TRUE
I1604 TRUE PCIE_CLK100M_AP_CONN_P 34 96 I1660 TRUE LPC_FRAME_L 17 41 43 82 TRUE NC_FW0_TPBP
92 TRUE GND 2X GND TRUE DP_INT_ML_N<0> 81 95
D I1605 TRUE
TRUE
PCIE_WAKE_L
PP3V3_S3RS4_BT_F
18 34
34
I1663 TRUE
TRUE
LPC_PWRDWN_L
LPC_SERIRQ
18 25 41 43
17 41 43
I1766
TRUE
NC_FW0_TPBN
NC_FW0_TPAP
D
I1606
TRUE PP3V3_WLAN 34 42
I1664
TRUE PM_CLKRUN_L 18 41 43
J6801 - 3-mic I1768 TRUE DP_INT_ML_N<2> 81 95 18 TP_CRT_IG_BLUE TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
TRUE NC_ESTARLDO_EN
I1608 I1662
CON_DMIC_CLK DP_INT_ML_N<3> TP_CRT_IG_GREEN NC_CRT_IG_GREEN
I1743 TRUE 59 I1767 TRUE 81 95 18 TRUE
I1609 TRUE USB_BT_CONN_N 34 91 I1665 TRUE PP5V_S0 7 8 MAKE_BASE=TRUE TRUE NC_ALS_GAIN
I1742 TRUE CON_DMIC_PWR 59 I1769 TRUE DP_INT_ML_P<0> 81 95 18 TP_CRT_IG_RED TRUE NC_CRT_IG_RED
I1607 TRUE USB_BT_CONN_P 34 91 I1666 TRUE SMC_RESET_L 41 42 43 61 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR2 26
I1745 TRUE CON_DMIC_SDA1 59 I1770 TRUE DP_INT_ML_P<1> 81 95 18 TP_CRT_IG_DDC_CLK TRUE NC_CRT_IG_DDC_CLK
I1611 TRUE WIFI_EVENT_L 34 41 42 I1668 TRUE SMC_ROMBOOT 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR3 26
I1744 TRUE CON_DMIC_SDA2 59 I1771 TRUE DP_INT_ML_P<2> 81 95 18 TP_CRT_IG_DDC_DATA TRUE NC_CRT_IG_DDC_DATA
TRUE GND 4X GND I1669 TRUE SMC_RX_L 41 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR4 26
TRUE GND I1773 TRUE DP_INT_ML_P<3> 81 95 18 TP_CRT_IG_HSYNC TRUE NC_CRT_IG_HSYNC
I1667 TRUE SMC_TCK 41 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_OCS2 26
TRUE LCD_FSS 81 82 18 TP_CRT_IG_VSYNC TRUE NC_CRT_IG_VSYNC
J3502 - ALS camera I1671 TRUE SMC_TDI 41 42 43
J6802 - L speaker
I1772
TRUE LCD_HPD_CONN 81 18 TP_LVDS_IG_CTRL_CLK
MAKE_BASE=TRUE
TRUE NC_LVDS_IG_CTRL_CLK
TRUE NC_USB_HUB_OCS3 26
I1774
I1610 TRUE PP5V_S3_ALSCAMERA_F 34 I1670 TRUE SMC_TDO 41 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_OCS4 26
I1746 TRUE SPKRCONN_L_ID 59 I1775 TRUE LED_RETURN_1 81 86 18 TP_LVDS_IG_CTRL_DATA TRUE NC_LVDS_IG_CTRL_DATA
I1613 TRUE SMBUS_SMC_2_S3_SCL 7 41 44 94 I1673 TRUE SMC_TMS 41 42 43 MAKE_BASE=TRUE TRUE NC_SMC_XOSC1 41
I1748 TRUE SPKRCONN_L_OUT_N 57 59 96 I1776 TRUE LED_RETURN_2 81 86 18 TP_PCH_LVDS_VBG TRUE NC_PCH_LVDS_VBG
I1614 TRUE SMBUS_SMC_2_S3_SDA 7 41 44 94 I1674 TRUE SMC_TX_L 41 42 43 MAKE_BASE=TRUE TRUE NC_SMC_ODD_DETECT 42
I1747 TRUE SPKRCONN_L_OUT_P 57 59 96 I1777 TRUE LED_RETURN_3 81 86
I1612 TRUE USB_CAMERA_CONN_N 34 91 I1672 TRUE SPIROM_USE_MLB 20 43 52 TRUE NC_SMC_SYS_LED 42
I1750 TRUE SPKRCONN_SL_OUT_N 57 59 96 I1779 TRUE LED_RETURN_4 81 86 17 TP_HDA_SDIN1 TRUE NC_HDA_SDIN1
I1615 TRUE USB_CAMERA_CONN_P 34 91 I1675 TRUE SPI_ALT_CLK 43 MAKE_BASE=TRUE TRUE NC_SMC_HIB_L 41
I1749 TRUE SPKRCONN_SL_OUT_P 57 59 96 I1778 TRUE LED_RETURN_5 81 86 17 TP_HDA_SDIN2 TRUE NC_HDA_SDIN2
TRUE GND I1676 TRUE SPI_ALT_CS_L 43 MAKE_BASE=TRUE TRUE NC_SMBUS_SMC_4_ASF_SDA 42
TRUE GND I1780 TRUE LED_RETURN_6 81 86 17 TP_HDA_SDIN3 TRUE NC_HDA_SDIN3
I1678 TRUE SPI_ALT_MISO 43 MAKE_BASE=TRUE TRUE NC_SMBUS_SMC_4_ASF_SCL 42
TRUE PP5VR3V3_SW_LCD 3X 81 TP_PCI_AD<31..0> TRUE NC_PCI_AD<31..0>
J4400 - rio coax I1679 TRUE SPI_ALT_MOSI 43
I1781
TRUE PPVOUT_S0_LCDBKLT 81 86 99 TP_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
TRUE NC_PCI_C_BE_L<3..0>
TRUE NC_SMC_T25_EN_L 8
I1621 TRUE HDMI_EG_DATA_C_N<2> 38 77 95 I1685 TRUE Z2_CS_L 49 I1755 TRUE SPKRCONN_SR_OUT_N 57 59 96 TRUE TBT_A_D2R_C_P<1..0> 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCDBKLTN 99
TP_PCI_PAR TRUE NC_PCI_PAR
I1620 TRUE HDMI_EG_DATA_C_P<0> 38 77 95 I1686 TRUE Z2_DEBUG3 I1754 TRUE SPKRCONN_SR_OUT_P 57 59 96 TRUE TBT_A_D2R_C_N<1..0> 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCD_PANELP 81 98
TP_PCI_RESET_L TRUE NC_PCI_RESET_L
I1623 TRUE HDMI_EG_DATA_C_P<1> 38 77 95 I1687 TRUE Z2_MOSI 49 TRUE GND TRUE TBT_A_D2R_P<1..0> 7 35 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCD_PANELN 81 98
19 TP_PCI_PME_L TRUE NC_PCI_PME_L
I1624 TRUE HDMI_EG_DATA_C_P<2> 38 77 95 I1689 TRUE Z2_MISO 49 TRUE TBT_A_D2R_N<1..0> 7 35 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_AIRPORTP 99
19 TP_PCI_CLK33M_OUT3 TRUE NC_PCI_CLK33M_OUT3
I1622 TRUE PCIE_CLK100M_ENET_N 17 38 92 I1688 TRUE Z2_SCLK 49 J6900 - DC PWR TRUE TBT_A_R2D_C_P<1..0> 7 35 84 93
TP_PCH_NV_RCOMP
MAKE_BASE=TRUE
TRUE NC_PCH_NV_RCOMP
TRUE NC_ISNS_AIRPORTN 99
I1625 TRUE PCIE_CLK100M_ENET_P 17 38 92 I1691 TRUE Z2_HOST_INTN 49 I1756 TRUE ADAPTER_SENSE 60 TRUE TBT_A_R2D_C_N<1..0> 35 84 93 MAKE_BASE=TRUE
C I1626 TRUE
TRUE
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
17 38 92
17 38 92
I1690 TRUE
TRUE
Z2_CLKIN
Z2_KEY_ACT_L
49
49
I1758 TRUE
TRUE
PP18V5_DCIN_FUSE
TDM_ONEWIRE_MPM
2X 60
60
TRUE
TRUE
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>
84 93
84 93
TP_NV_DQ<15..0>
TP_NV_DQS<1..0>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_NV_DQ<15..0>
NC_NV_DQS<1..0> TP_HDMI_CEC TRUE NC_HDMI_CEC C
I1628 I1692 I1757 MAKE_BASE=TRUE
TP_NV_CE_L<3..0> TRUE NC_NV_CE_L<3..0>
I1629 TRUE PCIE_ENET_R2D_C_N 17 38 92 I1694 TRUE Z2_RESET TRUE GND 2X GND TRUE TBT_B_D2R_C_P<1..0> 85 93 MAKE_BASE=TRUE
TP_NV_ALE TRUE NC_NV_ALE
I1627 TRUE PCIE_ENET_R2D_C_P 17 38 92 I1693 TRUE PSOC_F_CS_L 49 TRUE TBT_B_D2R_C_N<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_HPD TRUE NC_DP_IG_C_HPD
TP_NV_CLE TRUE NC_NV_CLE MAKE_BASE=TRUE
I1631 TRUE USB3_EXTB_RX_N 19 38 91 I1695 TRUE PICKB_L 49 POWER RAILS TRUE TBT_B_D2R_P<1..0> 35 85 93
TP_NV_RB_L
MAKE_BASE=TRUE
NC_NV_RB_L
TP_DP_IG_C_CTRL_CLK TRUE NC_DP_IG_C_CTRL_CLK
TRUE MAKE_BASE=TRUE
I1630 TRUE USB3_EXTB_RX_P 19 38 91 I1799 TRUE PP3V3_S4 7 8 FUNC_TEST TRUE TBT_B_D2R_N<1..0> 35 85 93 MAKE_BASE=TRUE TP_DP_IG_C_CTRL_DATA TRUE NC_DP_IG_C_CTRL_DATA
TP_NV_WR_RE_L<1..0> TRUE NC_NV_WR_RE_L<1..0> MAKE_BASE=TRUE
I1633 TRUE USB3_EXTB_TX_C_N 38 97 I1800 TRUE PP5V_S5 7 8 TRUE TBT_B_R2D_C_P<1..0> 7 35 85 93 MAKE_BASE=TRUE 18 TP_DP_IG_C_MLP<3..0> TRUE NC_DP_IG_C_MLP<3..0>
TRUE PM_SLP_S3_L 7 18 27 38 41 70 TP_NV_WE_CK_L<1..0> TRUE NC_NV_WE_CK_L<1..0> MAKE_BASE=TRUE
I1634 TRUE USB3_EXTB_TX_C_P 38 97 I1697 TRUE PSOC_MISO 49 TRUE TBT_B_R2D_C_N<1..0> 35 85 93 MAKE_BASE=TRUE 18 TP_DP_IG_C_MLN<3..0> TRUE NC_DP_IG_C_MLN<3..0>
TRUE PP0V75_S0_DDRVTT 8 17 TP_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N MAKE_BASE=TRUE
I1632 TRUE USB_EXTB_N 26 38 91 I1797 TRUE PSOC_MOSI 49 TRUE TBT_B_R2D_P<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_AUXP TRUE NC_DP_IG_C_AUXP
TRUE PP1V05_S0 8 17 TP_PCIE_CLK100M_PE4P TRUE NC_PCIE_CLK100M_PE4P MAKE_BASE=TRUE
I1635 TRUE USB_EXTB_P 26 38 91 I1798 TRUE PSOC_SCLK 49 TRUE TBT_B_R2D_N<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_AUXN TRUE NC_DP_IG_C_AUXN
TP_PCIE_CLK100M_PE5N TRUE NC_PCIE_CLK100M_PE5N MAKE_BASE=TRUE
TRUE GND 19X GND I1817 TRUE SMBUS_SMC_2_S3_SCL 7 41 44 94 TRUE DP_TBTSNK0_ML_C_P<3..0> 35 77 95 MAKE_BASE=TRUE
TRUE PP1V8_S0 8 TP_PCIE_CLK100M_PE5P TRUE NC_PCIE_CLK100M_PE5P 18 TP_DP_IG_D_HPD TRUE NC_DP_IG_D_HPD
I1818 TRUE SMBUS_SMC_2_S3_SDA 7 41 44 94 TRUE DP_TBTSNK0_ML_C_N<3..0> 35 77 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
TRUE PP3V3_S0 7 8 96 TP_PCIE_CLK100M_PE6N TRUE NC_PCIE_CLK100M_PE6N 18 TP_DP_IG_D_CTRL_CLK TRUE NC_DP_IG_D_CTRL_CLK
TRUE GND 2X GND TRUE DP_TBTSNK0_ML_P<3..0> 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
J4410 - rio flex TRUE PP3V3_S0GPU 8
TRUE DP_TBTSNK0_ML_N<3..0> 35 95
TP_PCIE_CLK100M_PE6P TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6P 18 TP_DP_IG_D_CTRL_DATA TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
I1636 TRUE ENET_CLKREQ_L 17 38 J5713 - keyboard TRUE PP3V3_S3 7 8
TRUE DP_TBTSNK0_AUXCH_C_P 35 83 95
TP_PCIE_CLK100M_PE7N TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7N 18 TP_DP_IG_D_MLP<3..0> TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>
TRUE ENET_RESET_L 25 TRUE PP3V3_S4 7 8 TRUE PP3V3_S5 8 96 TP_PCIE_CLK100M_PE7P TRUE NC_PCIE_CLK100M_PE7P 18 TP_DP_IG_D_MLN<3..0> TRUE NC_DP_IG_D_MLN<3..0>
I1638 I1802
TRUE DP_TBTSNK0_AUXCH_C_N 35 83 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1639 TRUE HDMI_EG_DDC_CLK 38 77 I1803 TRUE PP3V42_G3H 7 8 TRUE PP3V3_S5_AVREF_SMC 41 42 49 TP_PSOC_P1_3 TRUE NC_PSOC_P1_3 18 TP_DP_IG_D_AUXP TRUE NC_DP_IG_D_AUXP
TRUE DP_TBTSNK0_AUXCH_P 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1637 TRUE HDMI_EG_DDC_DATA 38 77 I1696 TRUE WS_CONTROL_KBD 49 TRUE PP3V42_G3H 7 8 TP_SATA_B_D2RN TRUE NC_SATA_B_D2RN 18 TP_DP_IG_D_AUXN TRUE NC_DP_IG_D_AUXN
TRUE DP_TBTSNK0_AUXCH_N 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1641 TRUE HDMI_HPD_L 38 42 82 I1698 TRUE WS_KBD1 49 TRUE PP5V_S0 7 8 TP_SATA_B_D2RP TRUE NC_SATA_B_D2RP
TRUE DP_TBTSNK1_ML_C_P<3..0> 35 77 95 MAKE_BASE=TRUE
I1640 TRUE I2C_DPMUX_A_SCL 44 I1699 TRUE WS_KBD10 49 TRUE PP5V_S3 8 TP_SATA_B_R2D_CN TRUE NC_SATA_B_R2D_CN 18 TP_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN
TRUE DP_TBTSNK1_ML_C_N<3..0> 35 77 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1643 TRUE I2C_DPMUX_A_SDA 44 I1700 TRUE WS_KBD11 49 TRUE PP5V_S5 7 8 TP_SATA_B_R2D_CP TRUE NC_SATA_B_R2D_CP 18 TP_SDVO_TVCLKINP TRUE NC_SDVO_TVCLKINP
TRUE DP_TBTSNK1_ML_P<3..0> 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1644 TRUE PM_SLP_S3_L 7 18 27 38 41 70 I1702 TRUE WS_KBD12 49 TRUE PPBUS_G3H 8 17 TP_SATA_D_D2RN TRUE NC_SATA_D_D2RN
TRUE DP_TBTSNK1_ML_N<3..0> 35 95 MAKE_BASE=TRUE 18 TP_SDVO_STALLN TRUE NC_SDVO_STALLN
I1642 TRUE PM_SLP_S4_L 18 27 34 38 40 41 70 I1701 TRUE WS_KBD13 49 TRUE PPDCIN_G3H 8 17 TP_SATA_D_D2RP TRUE NC_SATA_D_D2RP MAKE_BASE=TRUE
TRUE DP_TBTSNK1_AUXCH_C_P 35 83 95 MAKE_BASE=TRUE 18 TP_SDVO_STALLP TRUE NC_SDVO_STALLP
I1645 TRUE PP1V5_S0_RIO 8 I1703 TRUE WS_KBD14 49 TRUE PPVCORE_GPU 8 17 TP_SATA_D_R2D_CN TRUE NC_SATA_D_R2D_CN MAKE_BASE=TRUE
TRUE DP_TBTSNK1_AUXCH_C_N 35 83 95 MAKE_BASE=TRUE
I1646 TRUE PP3V3_S3 7 3X P3V3_S3 I1704 TRUE WS_KBD15_CAP 49 TRUE PPVCORE_S0_CPU 8 17 TP_SATA_D_R2D_CP TRUE NC_SATA_D_R2D_CP 18 TP_SDVO_INTN TRUE NC_SDVO_INTN
8 TRUE DP_TBTSNK1_AUXCH_P 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1648 TRUE PP3V3_S4 7 8 I1705 TRUE WS_KBD16_NUM 49 TRUE PPVTTDDR_S3 8 17 TP_SATA_E_D2RN TRUE NC_SATA_E_D2RN 18 TP_SDVO_INTP TRUE NC_SDVO_INTP
TRUE DP_TBTSNK1_AUXCH_N 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
TRUE PP5V_S4 8 5X P5V_S4 TRUE WS_KBD17 49 17 TP_SATA_E_D2RP TRUE NC_SATA_E_D2RP
B I1649
I1680 TRUE FAN_LT_PWM 48 I1720 TRUE WS_KBD8 49 17 TP_PCIE_7_D2RP TRUE NC_PCIE_7_D2RP MAKE_BASE=TRUE
MAKE_BASE=TRUE SMC_BS_ALRT_L TRUE NC_SMC_BS_ALRT_L
I1683 TRUE FAN_LT_TACH 48 I1719 TRUE WS_KBD9 49 17 TP_PCIE_7_R2D_CN TRUE NC_PCIE_7_R2D_CN MAKE_BASE=TRUE
MAKE_BASE=TRUE
I1793 TRUE PP5V_S0 7 3X P5V_S0 I1722 TRUE WS_KBD_ONOFF_L 49 17 TP_PCIE_7_R2D_CP TRUE NC_PCIE_7_R2D_CP
8 MAKE_BASE=TRUE
TRUE GND 5X GND I1721 TRUE WS_LEFT_OPTION_KBD 49
WS_LEFT_SHIFT_KBD
17 TP_PCIE_8_D2RN TRUE NC_PCIE_8_D2RN Thunderbolt NO_TESTs
I1723 TRUE 49 MAKE_BASE=TRUE NO_TEST
17 TP_PCIE_8_D2RP TRUE NC_PCIE_8_D2RP 35 TP_TBT_XTAL25OUT TRUE NC_TBT_XTAL25OUT TRUE PCH_VSS_NCTF<15>
J5660 - right fan TRUE GND 2X GND
17 TP_PCIE_8_R2D_CN TRUE
MAKE_BASE=TRUE
NC_PCIE_8_R2D_CN 35 TP_TBT_PCIE_RESET0_L
MAKE_BASE=TRUE
TRUE NC_TBT_PCIE_RESET0_L
TRUE PCH_VSS_NCTF<1>
TRUE PCH_VSS_NCTF<17>
I1684 TRUE FAN_RT_PWM 48 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<2>
17 TP_PCIE_8_R2D_CP TRUE NC_PCIE_8_R2D_CP 35 TP_TBT_PCIE_RESET1_L TRUE NC_TBT_PCIE_RESET1_L TRUE PCH_VSS_NCTF<19> 7
I1682 TRUE FAN_RT_TACH 48 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<5>
35 TP_TBT_PCIE_RESET2_L TRUE NC_TBT_PCIE_RESET2_L TRUE PCH_VSS_NCTF<19> 7
I1795 TRUE PP5V_S0 3X P5V_S0 TP_PCIE_PE5_D2RN TRUE NC_PCIE_PE5_D2RN MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<7>
MAKE_BASE=TRUE 35 TP_TBT_PCIE_RESET3_L TRUE NC_TBT_PCIE_RESET3_L TRUE PCH_VSS_NCTF<21>
TRUE GND 5X GND TP_PCIE_PE5_D2RP TRUE NC_PCIE_PE5_D2RP MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<9>
MAKE_BASE=TRUE 35 TP_DP_TBTSRC_ML_CP<3..0> TRUE NC_DP_TBTSRC_ML_CP<3..0> TRUE PCH_VSS_NCTF<25>
TP_PCIE_PE5_R2D_CN TRUE NC_PCIE_PE5_R2D_CN MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<11>
MAKE_BASE=TRUE 35 TP_DP_TBTSRC_ML_CN<3..0> TRUE NC_DP_TBTSRC_ML_CN<3..0> TRUE PCH_VSS_NCTF<27>
TP_PCIE_PE5_R2D_CP TRUE NC_PCIE_PE5_R2D_CP MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<12>
J5815 - kbd backlight MAKE_BASE=TRUE 35 TP_DP_TBTSRC_AUXCH_CP TRUE
MAKE_BASE=TRUE
NC_DP_TBTSRC_AUXCH_CP TRUE PCH_VSS_NCTF<29>
I1728 TRUE KBDLED_ANODE1 2X 50 TP_PCIE_PE6_D2RN TRUE NC_PCIE_PE6_D2RN 35 TP_DP_TBTSRC_AUXCH_CN TRUE NC_DP_TBTSRC_AUXCH_CN
MAKE_BASE=TRUE
A I1730 TRUE
TRUE
KBDLED_ANODE2
SMC_KBDLED_PRESENT_L
2X 50
50
TP_PCIE_PE6_D2RP
TP_PCIE_PE6_R2D_CN
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
I1729 PAGE TITLE
MAKE_BASE=TRUE
TRUE GND 4X GND TP_PCIE_PE6_R2D_CP TRUE NC_PCIE_PE6_R2D_CP PCH ALIASES
MAKE_BASE=TRUE Functional / ICT Test
TP_PCIE_PE7_D2RN TRUE NC_PCIE_PE7_D2RN NC_LPC_DREQ0_L TP_LPC_DREQ0_L 17 DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE
D
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
64
67
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_PCH
69
18
15 13 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
D
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S0_CPUAXG 66 =PP3V3_S5_PCHPWRGD 70 =PP3V3_GPU_MISC 77
64 =PPDDR_S3_REG PP1V5R1V35_S3
=PPVIN_S0_VCCSAS0 62 =PP3V3_S5_PCH_GPIO 20 MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
=PPVIN_S0_PCHVCCIOS0 87 =PP3V3_S5_PCH_VCCDSW 21 23 VOLTAGE=1.5V
MAKE_BASE=TRUE
46 =PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS =PP3V3_S5_PWRCTL 70
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP1V5_S3_MEMRESET 27
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE =PP3V3_S5_SMCBATLOW 42
=PPDDR_S3_MEMVREF 33
=PPVIN_S0_GFXIMVP 80 =PP3V3_S5_SYSCLK 25
=PPVIN_S3_P1V5S3RS0_FET 69
=PPVIN_S0GPU_P1V5P1V0 74 =PP3V3_S5_VMON 70
=PPVIN_S0_DDRREG_LDO 64
=PP3V3_S5_XDP 24
46 =PPVIN_S5_HS_OTHER_ISNS PPVIN_S5_HS_OTHER_ISNS =PPVIN_S3_MEM_ISNS_R 45
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP3V3_S4_TBTAPWRSW 84
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE
=PP3V3_S4_TBTBPWRSW 85 45 =PPVIN_S3_MEM_ISNS PP1V5R1V35_MEM
=PPVIN_S5_P5VP3V3 63 MIN_LINE_WIDTH=0.2 mm
69 =PP3V3_S3_FET PP3V3_S3 7 MIN_NECK_WIDTH=0.17 mm
60 =PP18V5_DCIN_CONN PPDCIN_G3H 7 MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE
=PP3V3_S3_BT 34 =PP1V5R1V35_S3_MEM_A 28 29
=PPDCIN_S5_CHGR 61
=PP3V3_S3_DPMUX_UC 82 =PP1V5R1V35_S3_MEM_B 30 31
60 =PP18V5_DCIN_ISOL PPDCIN_G3H_ISOL
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V =PP3V3_S3_ISNS 99
MIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE
=PP3V3_S3_MEMRESET 27 69 =PP1V5_S3RS0_FET_ISNS PP1V5_S3RS0_CPUDDR 96
=PPDCIN_S5_CHGR_ISOL 61 MIN_LINE_WIDTH=0.6 MM
=PP3V3_S3_PCH_GPIO 19 25 MIN_NECK_WIDTH=0.2 MM
=PPDCIN_S5_VSENSE 45 VOLTAGE=1.5V
=PP3V3_S3_RIO 38 MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS 43 =PP3V3_S3_TPAD
68 =PP1V5_S0_REG PP1V5_S0
=PP3V3_S5_SMC 41 42 78 =PP3V3_S3_USBMUX 26 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V42_G3H_CHGR 61 70 =PP3V3_S3_USB_HUB 26 VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP3V42_G3H_ONEWIREPROT 60 =PP3V3_S3_USB_RESET 26 74 =PP1V5R1V35_GPU_REG PP1V5R1V35_S0GPU
MIN_LINE_WIDTH=0.6 MM
=PP3V42_G3H_PWRCTL 70 =PP3V3_S3_VREFMRGN 33 =PP1V5_S0_AUDIO 53 MIN_NECK_WIDTH=0.2 MM
C 58 =PP3V42_G3H_AUDIO
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
44
40
=PP3V3_S3_WLAN
=PP3V3_S3_GYRO
34
51
=PP3V3R1V5_S0_PCH_VCCSUSHDA 21 23 25
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V35_GPU_FBVDDQ 72 75 76
C
60 =PP3V42_G3H_TDM 68 =PP1V5_S0_RIO_LDO PP1V5_S0_RIO 7
=PP3V42_G3H_TPAD 49 =PP3V3_S3_SMS 51 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V =PP1V35_GPU_S0_FB 73
42 =PP3V42_S3_HALL MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S5_SMCVREF 42 =PP3V3_S3_SDBUF 25
For PCH RTC Power =PP1V5_S0_RIO 38
=PPVBAT_G3_SYSCLK 25 69 =PP3V3_S0_FET PP3V3_S0 7 96
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V 64 33 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 7
25 =PPVRTC_G3_OUT PPVRTC_G3H MIN_NECK_WIDTH=0.075 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_AUDIO 59 VOLTAGE=0.75V
MAKE_BASE=TRUE
5V Rails =PPVRTC_G3_PCH 17 18 21 =PP3V3_S0_AUDIO_DIG 53 58
=PPVTT_S0_DDR_LDO PP0V75_S0_DDRVTT =PP1V8_GPU_FET TP_GPU_PGOOD2
64 7 88
63 =PP5V_S5_LDO PP5V_S5 7 =PP3V3_S0_BKL_VDDIO 86 MIN_LINE_WIDTH=2 mm
MIN_LINE_WIDTH=0.5 MM VOLTAGE=5V MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE =PP3V3_S0_CPUTHMSNS 47 VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP5V_S5_P1V5S3RS0FET 69 =PP3V3_S0_CPU_VCCIO_SEL 13
=PP0V75_S0_MEM_VTT_A 32
=PP5V_S5_P5VSUSFET 69 =PP3V3_S0_DPMUX 82 83
=PP0V75_S0_MEM_VTT_B 32
=PP5V_S5_TPAD 49 =PP3V3_S0_DPMUXI2C 44 74 =PP1V05_S0GPU_REG PP1V0_S0GPU_ISNS
=PPVTT_S0_VTTCLAMP 27 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V
69 =PP5V_SUS_FET PP5V_SUS =PP3V3_S0_DPMUX_UC 35 78 82 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM VOLTAGE=5V 68 =PP1V05_SUS_LDO PP1V05_SUS
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_FAN_LT 48 MIN_LINE_WIDTH=0.4 MM =PP1V0_GPU_DPLL
MIN_NECK_WIDTH=0.2 MM
=PP5V_SUS_PCH 23 =PP3V3_S0_FAN_RT 48 VOLTAGE=1.05V =PP1V0_GPU_DP_AB
MAKE_BASE=TRUE
63 =PP5V_S4_REG PP5V_S4 7 =PP3V3_S0_GPUTHMSNS 47 =PP1V0_GPU_DP_CD
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V =PP1V05_SUS_PCH_JTAG 24
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE =PP3V3_S0_HS_ISNS 46 =PP1V05_GPU_IFPCD_IOVDD 77
67 =PPCPUVCCIO_S0_REG PP1V05_S0 7
=PP5V_S4_RIO 38 =PP3V3_S0_IMVPISNS 46 MIN_LINE_WIDTH=0.6 MM =PP1V05_GPU_IFPEF_IOVDD 77
MIN_NECK_WIDTH=0.2 MM
=PP5V_S4_P5VS0FET 69 =PP3V3_S0_ISNS 45 98 99 VOLTAGE=1.05V =PP1V05_GPU_PEX_IOVDD 73 79
MAKE_BASE=TRUE
=PP5V_S4_P5VS3FET 69 =PP3V3_S0_LCD 81 =PP1V05_GPU_PEX_PLLVDD 77 79
=PP1V05_S0_CPU_VCCIO 10 11 13 14 15
=PP5V_S0_LCD 81 =PP3V3_S0_P1V8GPUFET
=PPVCCIO_S0_XDP 24 45 =PPVCORE_GPU_REG PPVCORE_GPU 7
=PP5V_S3_LTUSB 40 =PP3V3_S0_P3V3TBTFET 37 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.0V
=PPVCCIO_S0_CPUIMVP 65 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP5V_S4_ISNS =PP3V3_S0_PCH 17 23
=PPVCCIO_S0_SMC 42 =PPVCORE_GPU 72 79
=PP5V_S4_TPAD 49 =PP3V3_S0_PCH_GPIO 17 18 19 20 25 37
=PP1V05_S0_VMON 70
=PP5V_S4_AUDIO 53 59 =PP3V3_S0_PCH_VCC3_3_CLK 23
=PP1V05_S0_RMC 98 =PPVCORE_S0_GFX_REG 80
B 69 =PP5V_S3_FET PP5V_S3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
7 =PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
21 23
21 23 87 =PPPCHVCCIO_S0_REG PP1V05_PCHVCCIO_S0
B
MIN_LINE_WIDTH=0.6 MM
=PP5V_S3_ISNS 99 =PP3V3_S0_PCH_VCC3_3_PCI 21 23 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP5V_S3_ALSCAMERA 34 =PP3V3_S0_PCH_VCC3_3_SATA 21 23 MAKE_BASE=TRUE
=PP5V_S3_DDRREG 64 =PP3V3_S0_PCH_VCCADAC 23 =PP1V05_S0_PCH_VCCIO_PLLPCIE 21 GND =LVDS_VCCA 21
MIN_LINE_WIDTH=0.6MM
=PP5V_S3_DEBUG_ADC_AVDD 98 =PP3V3_S0_PWRCTL 70 88 =PP1V05_S0_PCH_VCCADPLL 23 MIN_NECK_WIDTH=0.085MM
VOLTAGE=0V
=PP5V_S3_DEBUG_ADC_DVDD 98 =PP3V3_S0_RSTBUF 25 =PP1V05_S0_PCH_VCCIO 21 23 MAKE_BASE=TRUE
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
36 =PP3V3_S4_TBT_R 37 =PP1V05_TBTLC_FET PP1V05_TBTLC 37
PAGE TITLE
=PP3V3_S4_TPAD
=PP3V3_S4_SMC 25 42
49 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE Backlight Rails Power Aliases
38 =PP3V3_S4_RIO =PP1V05_TBTLC_RTR 36 99 =PPBUS_SW_BKL PPBUS_SW_BKL DRAWING NUMBER SIZE
=PP3V3_S4_BT
69 =PP3V3_SUS_FET PP3V3_SUS
34
37 =PP1V05_TBTCIO_FET PP1V05_TBTCIO
MIN_LINE_WIDTH=0.5 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.6V
Apple Inc. 051-9589 D
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V PPBUS_S0_LCDBKLT_PWR 86 REVISION
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE R
MIN_NECK_WIDTH=0.2 MM
=PP3V3_SUS_P1V05SUSLDO
VOLTAGE=3.3V
68
=PP1V05_TBTCIO_RTR 36
4.18.0
=PP3V3_SUS_PCH_VCCSUS 21 23 41 SMC_T25_EN_L NC_SMC_T25_EN_L 7 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCSUS_GPIO 21 23 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
=PP3V3_SUS_PCH_GPIO 17 18 19 20 37 9 =PP15V_TBT_REG PP15V_TBT THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP3V3_SUS_ROM
52
23 21 =PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_USB 21 23
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=15V
MAKE_BASE=TRUE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 132
=PP3V3_SUS_CNTRL 70 =PPHV_SW_TBTAPWRSW 84 99 37 =PP1V05_S0_P1V05TBTFET PP1V05_S0_P1V05TBTFET SHEET
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
=PP3V3_SUS_SMC 42 =PPHV_SW_TBTBPWRSW 85 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE IV ALL RIGHTS RESERVED 8 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ZT0915 Frame Holes T29 / GMUX JTAG Signals
CPU signals
2.8R2.3
1 GND_BATT_CHGND
ZT0970
TH-NSP CPU_VID<0..6> CPUIMVP_VID<0..6> TP_CPU_VTT_SELECT CPU_VTTSELECT
GND_CHASSIS_MLBCAN1 1 MAKE_BASE=TRUE MAKE_BASE=TRUE
ZT0950
TH-NSP SL-1.1X0.45-1.4x0.75
1 GND_CHASSIS_FAN
ZT0971 27 MEMVTT_EN =DDRVTT_EN 27 64
SL-2.3X3.9-2.9X4.5 TH-NSP MAKE_BASE=TRUE
GND_CHASSIS_MLBCAN2 1
D SL-1.1X0.45-1.4x0.75
GND_CHASSIS_MLBCAN3 1
TH-NSP MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<15..14>
NO_TEST=TRUE
=PEG_D2R_N<15..14> 10
D
ZT0975
TH-NSP SL-1.1X0.45-1.4x0.75
MAKE_BASE=TRUE NO_TEST=TRUE
NC_LVDS_IG_A_DATAP<3> LVDS_IG_A_DATA_P<3> 18 91
NC_PEG_R2D_C_P<15..14> =PEG_R2D_C_P<15..14> 10 MAKE_BASE=TRUE NO_TEST=TRUE
1 GND_CHASSIS_MLBCAN6 MAKE_BASE=TRUE NO_TEST=TRUE
GMUX ALIASES NC_LVDS_IG_A_DATAN<3> LVDS_IG_A_DATA_N<3> 18 91
SL-1.1X0.45-1.4x0.75 ZT0973 NC_PEG_R2D_C_N<15..14> =PEG_R2D_C_N<15..14> 10 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
TH-NSP
GND GND_CHASSIS_MLBCAN4 1 82 EG_RESET_L GPU_RESET_L 71 78 T29 Signals Through PEG
MAKE_BASE=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATAP<3> LVDS_IG_B_DATA_P<3> 18
SL-1.1X0.45-1.4x0.75 MAKE_BASE=TRUE NO_TEST=TRUE
18 LVDS_IG_BKL_ON IG_BKLT_EN 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_D2R_P<3..0> =PEG_D2R_P<11..8> 10 NC_LVDS_IG_B_DATAN<3> LVDS_IG_B_DATA_N<3> 18
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 LVDS_IG_PANEL_PWR IG_LCD_PWR_EN 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_D2R_N<3..0> =PEG_D2R_N<11..8> 10
MAKE_BASE=TRUE
THERMAL MODULE STANDOFFS PEX_CLKREQ_L EG_CLKREQ_IN_L 78 82
PCIE_TBT_R2D_C_P<3..0> =PEG_R2D_C_P<11..8> NC_LVDS_IG_A_CLK_N LVDS_IG_A_CLK_N
MAKE_BASE=TRUE 92 35 10 18 91
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 PEG_CLKREQ_L EG_CLKREQ_OUT_L 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_R2D_C_N<3..0> =PEG_R2D_C_N<11..8> 10 NC_LVDS_IG_A_CLK_P LVDS_IG_A_CLK_P 18 91
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
82 DP_TBTSNK0_HPD_IG DPA_IG_HPD 18 82
SH0920 SH0927 SH0926 MAKE_BASE=TRUE
STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM SH0925 82 DP_TBTSNK1_HPD_IG DPB_IG_HPD
GPU signals
18 82
STDOFF-4.5OD1.8H-SM MAKE_BASE=TRUE NC_LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_N<2..0> 18 91
1 1 1 89 88 71 PEG_D2R_P<7..0> =PEG_D2R_P<7..0> 10 MAKE_BASE=TRUE NO_TEST=TRUE
1 MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_P<2..0> 18 91
89 88 71 PEG_D2R_N<7..0> =PEG_D2R_N<7..0> 10 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
17 PCIE_EXCARD_D2R_N TRUE NC_PCIE_EXCARD_D2R_N
SH0928 PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_P
89 71 PEG_R2D_C_P<7..0> =PEG_R2D_C_P<7..0> 10 NC_LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_N<2..0> 18 91
17 TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
STDOFF-4.5OD2.15H-SM SH0923 MAKE_BASE=TRUE
SH0929 17 PCIE_EXCARD_R2D_C_N TRUE NC_PCIE_EXCARD_R2D_C_N 89 71 PEG_R2D_C_N<7..0> =PEG_R2D_C_N<7..0> 10 NC_LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_P<2..0> 18 91
SH0921 STDOFF-4.5OD2.15H-SM
1 STDOFF-4.5OD1.8H-SM
PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
STDOFF-4.5OD2.15H-SM-1 1
17 TRUE
MAKE_BASE=TRUE NC_LVDS_IG_DDC_CLK LVDS_IG_DDC_CLK 18
1 UNUSED TBT PORTS MAKE_BASE=TRUE NO_TEST=TRUE
1
TBT_D2R_P<3..2> NC_TBT_D2RP<3..2> NC_LVDS_IG_DDC_DATA LVDS_IG_DDC_DATA 18
92 17 PCIE_CLK100M_EXCARD_N TRUE NC_PCIE_CLK100M_EXCARD_N MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
TBT_D2R_N<3..2> NC_TBT_D2RN<3..2>
92 17 PCIE_CLK100M_EXCARD_P TRUE NC_PCIE_CLK100M_EXCARD_P MAKE_BASE=TRUE NO_TEST=TRUE NC_PCIE_FW_D2RN PCIE_FW_D2R_N 17
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
SH0924 TBT_R2D_C_P<3..2> NC_TBT_R2D_CP<3..2>
C SH0922
STDOFF-4.5OD2.15H-SM SH0930
STDOFF-4.5OD1.9H-SM
1
TBT_R2D_C_N<3..2>
MAKE_BASE=TRUE
NC_TBT_R2D_CN<3..2>
MAKE_BASE=TRUE
NO_TEST=TRUE NC_PCIE_FW_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCIE_FW_R2D_CN
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
17
17
C
NO_TEST=TRUE
STDOFF-4.5OD2.15H-SM MAKE_BASE=TRUE NO_TEST=TRUE
1
1 NC_PCIE_FW_R2D_CP PCIE_FW_R2D_C_P 17
DPMUX TX & RX MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_PCH_CLKOUT_DPN TRUE DPLL_REF_CLKN 11 89
MAKE_BASE=TRUE
1 1 1
NC_CPU_FDI_DATA_N<7..0> FDI_DATA_N<7..0> 10 89
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED USB SIGNALS
NC_CPU_FDI_DATA_P<7..0> FDI_DATA_P<7..0> 10 89 NC_USB3_EXTD_TX_P USB3_EXTD_TX_P 19
91 34 USB_BT_N USBHUB_DN1_N 26
1 MAKE_BASE=TRUE NC_USB3_EXTC_TX_P USB3_EXTC_TX_P 19 91
MAKE_BASE=TRUE NO_TEST=TRUEI1188
91 49 USB_TPAD_P USBHUB_DN2_P 26
MAKE_BASE=TRUE NC_USB3_EXTC_TX_N USB3_EXTC_TX_N 19 91
MAKE_BASE=TRUE NO_TEST=TRUEI1189
91 49 USB_TPAD_N USBHUB_DN2_N 26
SH0940 SH0941 SH0944 SH0961 MAKE_BASE=TRUE NC_USB3_EXTC_RX_P USB3_EXTC_RX_P 19 91
2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM MAKE_BASE=TRUE NO_TEST=TRUEI1190
91 41 USB_SMC_P USBHUB_DN3_P 26
MAKE_BASE=TRUE NC_USB3_EXTC_RX_N USB3_EXTC_RX_N 19 91
1 1 1 1 MAKE_BASE=TRUE NO_TEST=TRUEI1192
91 41 USB_SMC_N USBHUB_DN3_N 26
MAKE_BASE=TRUE NC_USB_EXTC_P USB_EXTC_P 19 91
MAKE_BASE=TRUE NO_TEST=TRUEI1191
PU_USBHUB_DN4P USBHUB_DN4_P 26
MAKE_BASE=TRUE NC_USB_EXTC_N USB_EXTC_N 19 91
MAKE_BASE=TRUE
Digital Ground PU_USBHUB_DN4N USBHUB_DN4_N 26
NO_TEST=TRUE
A 20 MLB_RAMCFG3
RAMCFG3:L
MAKE_BASE=TRUE
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
20 MLB_RAMCFG2 PAGE TITLE
SH0942 SH0943 RAMCFG2:L R09131 8 =PP5V_S0_AUDIO_XW
Signal Aliases
2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 20 MLB_RAMCFG1 1K
1 1 RAMCFG1:L R09121 5%
1/20W
DRAWING NUMBER SIZE
20 MLB_RAMCFG0
1
1K MF XW0902
Apple Inc. 051-9589 D
RAMCFG0:L R0911 5%
1/20W
201 2 SM
REVISION
1K MF 1 2 PP5V_S0_AUDIO_AMP_L 57 R
R09101 5%
1/20W
201 2 MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
4.18.0
1K MF VOLTAGE=5V NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% 201 2 XW0903
1/20W SM THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE INC.
201 2 1 2 PP5V_S0_AUDIO_AMP_R 57 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
1
OMIT_TABLE
R1010
U1000 24.9
1%
IVY-BRIDGE 1/16W
MF-LF
BGA
402
2
89 18 DMI_S2N_N<0> N10 DMI_RX0* (1 OF 11) PEG_ICOMPI G2 89 CPU_PEG_COMP
IN
89 18 DMI_S2N_N<1> R10 DMI_RX1* PEG_ICOMPO H1
IN
89 18 DMI_S2N_N<2> R8 DMI_RX2* PEG_RCOMPO F3
IN
89 18 DMI_S2N_N<3> U10 DMI_RX3*
89 24 10 CPU_CFG<0> B57 (IPU) U1000 BB57
NC
IN
F23
89 24 10 CPU_CFG<1> D57 (IPU) IVY-BRIDGE BB43
NC
PEG_RX0* =PEG_D2R_N<0>
IN 9
B55 BGA BB25
CPU_CFG<2>
89 18 IN DMI_S2N_P<0> N8 DMI_RX0 PEG_RX1* H23 =PEG_D2R_N<1>
IN 9
89 24 10 (IPU)
NC
CPU_CFG<3> A54 (5 OF 11) BB17
89 18 DMI_S2N_P<1> T9 DMI_RX1 PEG_RX2* H21 =PEG_D2R_N<2> 9 SIGNAL_MODEL=EMPTY
89 24 10 (IPU)
RESERVED NC
D 89 18
IN
IN DMI_S2N_P<2> R6
U8
DMI_RX2 PEG_RX3* H19
J20
=PEG_D2R_N<3>
IN
IN 9
1 TP
SM BEAD-PROBE BP1004
89 24 10
89 24 10
CPU_CFG<4>
CPU_CFG<5>
A58
D55
(IPU)
(IPU)
OMIT_TABLE BB15
BB13
NC
NC
D
89 18 IN DMI_S2N_P<3> DMI_RX3 PEG_RX4* =PEG_D2R_N<4>
IN 9
C56 BA48
CPU_CFG<6>
PEG_RX5* G18
89 24 10 (IPU)
NC
DMI
=PEG_D2R_N<5> IN 9
CPU_CFG<7> E54 BA16
89 18 OUT DMI_N2S_N<0> N4 DMI_TX0* PEG_RX6* K17 =PEG_D2R_N<6> IN 9
89 24 10 (IPU)
NC
CPU_CFG<8> J54 AY45
89 18 OUT DMI_N2S_N<1> R4 DMI_TX1* PEG_RX7* F15 =PEG_D2R_N<7>
IN 9
89 24 (IPU)
NC
CPU_CFG<9> G56 AY41
89 18 OUT DMI_N2S_N<2> P1 DMI_TX2* PEG_RX8* H15 =PEG_D2R_N<8> IN 9
89 24 (IPU)
CFG NC
CPU_CFG<10> F55 AY17
89 18 OUT DMI_N2S_N<3> U6 DMI_TX3* PEG_RX9* H13 =PEG_D2R_N<9>
IN 9
89 24 (IPU)
NC
CPU_CFG<11> K55 AY15
PEG_RX10* H11 =PEG_D2R_N<10> IN 9
89 24 (IPU)
NC
89 24 CPU_CFG<12> F57 (IPU) AY13
89 18 OUT DMI_N2S_P<0> N2 DMI_TX0 PEG_RX11* J12 =PEG_D2R_N<11>
IN 9
NC
CPU_CFG<13> E58 AW50
89 18 OUT DMI_N2S_P<1> R2 DMI_TX1 PEG_RX12* E8 =PEG_D2R_N<12>
IN 9
89 24 (IPU)
NC
CPU_CFG<14> H57 AW46
89 18 OUT DMI_N2S_P<2> P3 DMI_TX2 PEG_RX13* G10 =PEG_D2R_N<13>
IN 9
89 24 (IPU)
NC
89 24 CPU_CFG<15> H55 (IPU) AW42
89 18 OUT DMI_N2S_P<3> T5 DMI_TX3 PEG_RX14* J8 =PEG_D2R_N<14> IN 9
NC
CPU_CFG<16> D53 AW14
PEG_RX15* F7 =PEG_D2R_N<15> 9
89 24 10 (IPU)
NC
IN CPU_CFG<17> K57 AJ10
89 9 OUT FDI_DATA_N<0> V7 FDI0_TX0*
89 24 (IPU)
NC
AJ6
89 9 OUT FDI_DATA_N<1> W8 FDI0_TX1* PEG_RX0 G22 =PEG_D2R_P<0> IN 9
NC
G64 AH5
FDI_DATA_N<2> AA8 FDI0_TX2* PEG_RX1 K23 =PEG_D2R_P<1> SIGNAL_MODEL=EMPTY NC NC
H9
=PEG_D2R_P<12>
=PEG_D2R_P<13>
IN
IN
9
9
NC
BG26
BG22
L2
K49
NC C
89 9 OUT FDI_DATA_P<4> U2 FDI1_TX0 PEG_RX14 H7 =PEG_D2R_P<14>
IN 9
NC NC
PPCPU_MEM_VREFDQ_B BG4 K47
89 9 OUT FDI_DATA_P<5> W4 FDI1_TX1 PEG_RX15 G6 =PEG_D2R_P<15> IN 9
89 33 (DDR_VREF1) (THERMDA)
NC
MIN_LINE_WIDTH=0.3 mm BF63 K9
89 9 OUT FDI_DATA_P<6> V3 FDI1_TX2 NC NC
MIN_NECK_WIDTH=0.2 mm BF43 K7
89 9 FDI_DATA_P<7> AA6 FDI1_TX3 PEG_TX0* A22 =PEG_R2D_C_N<0> 9
NC NC
OUT OUT BF41 K5
B23
VOLTAGE=0.75V NC RSVD NC
PEG_TX1* =PEG_R2D_C_N<1> OUT 9
BF35 J50
89 9 IN FDI_FSYNC<0> AC8 FDI0_FSYNC PEG_TX2* C18 =PEG_R2D_C_N<2> OUT 9
NC NC
BF25 J4
89 9 IN FDI_FSYNC<1> AA2 FDI1_FSYNC PEG_TX3* D21 =PEG_R2D_C_N<3>
OUT 9
NC NC
BF23 J2
PEG_TX4* B19 =PEG_R2D_C_N<4> OUT 9
NC NC
BF21 H49
89 18 IN FDI_INT AD9 FDI_INT PEG_TX5* E20 =PEG_R2D_C_N<5>
OUT 9
NC NC
BF19 H47
PEG_TX6* A14 =PEG_R2D_C_N<6> 9
NC (THERMDC)
NC
OUT PPCPU_MEM_VREFDQ_A BF3 H5
89 9 IN FDI_LSYNC<1> AB3 FDI1_LSYNC PEG_TX7* D17 =PEG_R2D_C_N<7>
OUT 9
89 33 (DDR_VREF0)
NC
MIN_LINE_WIDTH=0.3 mm BE32 G52
89 9 IN FDI_LSYNC<0> AB7 FDI0_LSYNC PEG_TX8* B15 =PEG_R2D_C_N<8> OUT 9
NC NC
MIN_NECK_WIDTH=0.2 mm BE16 G48
PEG_TX9* E16 =PEG_R2D_C_N<9>
OUT 9
NC NC
VOLTAGE=0.75V BE6 G4
89 82 OUT DP_INT_IG_ML_N<0> AG2 EDP_TX0* PEG_TX10* D13 =PEG_R2D_C_N<10>
OUT 9
NC NC
BD33 F5
89 82 OUT DP_INT_IG_ML_N<1> AF1 EDP_TX1* PEG_TX11* A10 =PEG_R2D_C_N<11>
OUT 9
NC NC
BD29 D49
89 82 OUT DP_INT_IG_ML_N<2> AE6 EDP_TX2* PEG_TX12* B11 =PEG_R2D_C_N<12>
OUT 9
NC NC
BD19 D25
89 82 OUT DP_INT_IG_ML_N<3> AG6 EDP_TX3* PEG_TX13* D9 =PEG_R2D_C_N<13>
OUT 9
NC NC
BD15 D3
EMBEDDED DISPLAY PORT
PEG_TX14* B7 =PEG_R2D_C_N<14>
OUT 9
NC NC
BD13 C52
89 82 OUT DP_INT_IG_ML_P<0> AG4 EDP_TX0 PEG_TX15* E12 =PEG_R2D_C_N<15>
OUT 9
NC NC
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO BC42 C24
89 82 OUT DP_INT_IG_ML_P<1> AF3 EDP_TX1 NC NC
BC30 C4
89 82 OUT DP_INT_IG_ML_P<2> AF7 EDP_TX2 PEG_TX0 C22 =PEG_R2D_C_P<0>
OUT 9
NC NC
BC14 B53
1
89 82 OUT DP_INT_IG_ML_P<3> AG8 EDP_TX3 PEG_TX1 D23 =PEG_R2D_C_P<1> OUT 9
NC NC
R1030 B25
OMIT_TABLE 24.9 PEG_TX2 A18 =PEG_R2D_C_P<2> OUT 9
NC
1 1%
R1031 AE4 B21
1/16W 89 82 BI DP_INT_IG_AUX_P EDP_AUX PEG_TX3 =PEG_R2D_C_P<3> OUT 9
1K MF-LF
402 89 82 DP_INT_IG_AUX_N AE2 EDP_AUX* PEG_TX4 D19 =PEG_R2D_C_P<4> 9
B
5%
1/16W
MF-LF
402
2
2
PLACE_NEAR=U1000.AB1:12.7mm
BI
AB1
PEG_TX5 F21
C14
=PEG_R2D_C_P<5>
OUT
OUT 9 B
89 CPU_EDP_COMP EDP_ICOMPO PEG_TX6 =PEG_R2D_C_P<6>
OUT 9
AC2 EDP_COMPIO PEG_TX7 B17 =PEG_R2D_C_P<7> 9
OUT
PEG_TX8 D15 =PEG_R2D_C_P<8> 9
OUT
DP_INT_IG_HPD_L AE8 EDP_HPD* PEG_TX9 F17 =PEG_R2D_C_P<9> 9
OUT
PEG_TX10 B13 =PEG_R2D_C_P<10> 9
OUT
PEG_TX11 C10 =PEG_R2D_C_P<11> 9
OUT
D 3 PEG_TX12 D11 =PEG_R2D_C_P<12> 9
OUT
PEG_TX13 B9 =PEG_R2D_C_P<13>
Q1031 OUT 9
89 24 10 CPU_CFG<7>
89 24 10 CPU_CFG<6> 89 24 10 CPU_CFG<16> PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
89 24 10 CPU_CFG<5> 89 24 10 CPU_CFG<3>
116S0066 1 RES,MTL FILM,1/16W,1K,0402,SMD,LF R1031 EDP:YES
89 24 10 CPU_CFG<4> 89 24 10 CPU_CFG<1>
A 1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
CPU_CFG<4> should be pulled down to enable EDP These can be Placed close to J2500 and Only for debug access DRAWING NUMBER SIZE
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
THE INFORMATION CONTAINED HEREIN IS THE
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 10 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
CLOCKS
BCLK_ITP* K65 ITPCPU_CLK100M_N
R1103 IN 17 89
C 89 65 42 41 BI CPU_PROCHOT_L 2
56
1
89 41 OUT CPU_CATERR_L H53 CATERR*
BCLK D5 DMI_CLK100M_CPU_P 17 89
C
5%
IN
1/16W CPU_PECI F53 PECI BCLK* C6 DMI_CLK100M_CPU_N
THERMAL
89 42 20 BI IN 17 89
MF-LF
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO 402
PWR MGMT
DDR3 MISC
27 OUT (IPU) BI 24 89
1 PLACE_NEAR=U1000.BG46:12.7mm
R1130
1K PLACE_NEAR=U1000.BJ46:12.7mm
PLACE_NEAR=U1000.BJ44:2.54mm 1%
1/16W
MF-LF
402 2
R11311 1
C1130
1K 0.1UF
PLACE_NEAR=U1000.BJ44:2.54mm 1% 10%
1/16W 16V
MF-LF 2 X7R-CERM
402 2 0402
PLACE_NEAR=U1000.BJ44:2.54mm
A A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
90 29 28 BI MEM_A_DQ<1> AL8 SA_DQ1 IVY-BRIDGE SA_CLK0* BA32 MEM_A_CLK_N<0> OUT 28 32 90 90 31 30 BI MEM_B_DQ<1> AK3 SB_DQ1 IVY-BRIDGE SB_CLK0* BH33 MEM_B_CLK_N<0> OUT 30 32 90
AP7 BGA AP3 BGA
90 29 28 BI MEM_A_DQ<2> SA_DQ2 90 31 30 BI MEM_B_DQ<2> SB_DQ2
90 29 28 MEM_A_DQ<3> AM5 SA_DQ3 (3 OF 11) SA_CKE0 BC18 MEM_A_CKE<0> 28 32 90 90 31 30 MEM_B_DQ<3> AR2 SB_DQ3 (4 OF 11) SB_CKE0 BD25 MEM_B_CKE<0> 30 32 90
BI OUT BI OUT
OMIT_TABLE OMIT_TABLE
D 90 29 28
90 29 28
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AK7
AL10
SA_DQ4
SA_DQ5 SA_CLK1 AW34 MEM_A_CLK_P<1>
OUT 29 32 90
90 31 30
90 31 30
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AL2
AK1
SB_DQ4
SB_DQ5 SB_CLK1 BF37 MEM_B_CLK_P<1>
OUT 31 32 90
D
90 29 28 MEM_A_DQ<6> AN10 SA_DQ6 SA_CLK1* AY33 MEM_A_CLK_N<1> 29 32 90 90 31 30 MEM_B_DQ<6> AP1 SB_DQ6 SB_CLK1* BH37 MEM_B_CLK_N<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<7> AM9 SA_DQ7 90 31 30 MEM_B_DQ<7> AR4 SB_DQ7
BI BI
90 29 28 MEM_A_DQ<8> AR10 SA_DQ8 SA_CKE1 BD17 MEM_A_CKE<1> 29 32 90 90 31 30 MEM_B_DQ<8> AV3 SB_DQ8 SB_CKE1 BJ26 MEM_B_CKE<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<9> AR8 SA_DQ9 90 31 30 MEM_B_DQ<9> AU4 SB_DQ9
BI BI
90 29 28 MEM_A_DQ<10> AV7 SA_DQ10 SA_CS0* BD41 MEM_A_CS_L<0> 28 32 90 90 31 30 MEM_B_DQ<10> BA4 SB_DQ10 SB_CS0* BE40 MEM_B_CS_L<0> 30 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<11> AY5 SA_DQ11 SA_CS1* BD45 MEM_A_CS_L<1> 29 32 90 90 31 30 MEM_B_DQ<11> BB1 SB_DQ11 SB_CS1* BH41 MEM_B_CS_L<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<12> AT5 SA_DQ12 90 31 30 MEM_B_DQ<12> AV1 SB_DQ12
BI BI
90 29 28 MEM_A_DQ<13> AR6 SA_DQ13 SA_ODT0 BB41 MEM_A_ODT<0> 28 32 90 90 31 30 MEM_B_DQ<13> AU2 SB_DQ13 SB_ODT0 BG42 MEM_B_ODT<0> 30 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<14> AW6 SA_DQ14 SA_ODT1 BC46 MEM_A_ODT<1> 29 32 90 90 31 30 MEM_B_DQ<14> BA2 SB_DQ14 SB_ODT1 BH45 MEM_B_ODT<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<15> AT9 SA_DQ15 90 31 30 MEM_B_DQ<15> BB3 SB_DQ15
BI BI
90 29 28 MEM_A_DQ<16> BA6 SA_DQ16 SA_DQS0* AN8 MEM_A_DQS_N<0> 28 29 90 90 31 30 MEM_B_DQ<16> BC2 SB_DQ16 SB_DQS0* AN4 MEM_B_DQS_N<0> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<17> BA8 SA_DQ17 SA_DQS1* AU6 MEM_A_DQS_N<1> 28 29 90 90 31 30 MEM_B_DQ<17> BF7 SB_DQ17 SB_DQS1* AW2 MEM_B_DQS_N<1> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<18> BG6 SA_DQ18 SA_DQS2* BC6 MEM_A_DQS_N<2> 28 29 90 90 31 30 MEM_B_DQ<18> BF11 SB_DQ18 SB_DQS2* BH9 MEM_B_DQS_N<2> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<19> AY9 SA_DQ19 SA_DQS3* BD9 MEM_A_DQS_N<3> 28 29 90 90 31 30 MEM_B_DQ<19> BJ10 SB_DQ19 SB_DQS3* BF15 MEM_B_DQS_N<3> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<20> AW8 SA_DQ20 SA_DQS4* BC50 MEM_A_DQS_N<4> 28 29 90 90 31 30 MEM_B_DQ<20> BC4 SB_DQ20 SB_DQS4* BF51 MEM_B_DQS_N<4> 30 31 90
BI BI BI BI
MEMORY CHANNEL A
90 29 28 MEM_A_DQ<21> BB7 SA_DQ21 SA_DQS5* BB55 MEM_A_DQS_N<5> 28 29 90 90 31 30 MEM_B_DQ<21> BH7 SB_DQ21 SB_DQS5* BH57 MEM_B_DQS_N<5> 30 31 90
BI BI BI BI
BC8 BD59 BH11 AY63
MEMORY CHANNEL B
90 29 28 BI MEM_A_DQ<22> SA_DQ22 SA_DQS6* MEM_A_DQS_N<6>
BI 28 29 90 90 31 30 BI MEM_B_DQ<22> SB_DQ22 SB_DQS6* MEM_B_DQS_N<6> BI 30 31 90
90 29 28 MEM_A_DQ<23> BE4 SA_DQ23 SA_DQS7* AU60 MEM_A_DQS_N<7> 28 29 90 90 31 30 MEM_B_DQ<23> BG10 SB_DQ23 SB_DQS7* AN62 MEM_B_DQS_N<7> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<24> AW12 SA_DQ24 90 31 30 MEM_B_DQ<24> BJ14 SB_DQ24
BI BI
90 29 28 MEM_A_DQ<25> AV11 SA_DQ25 SA_DQS0 AN6 MEM_A_DQS_P<0> 28 29 90 90 31 30 MEM_B_DQ<25> BG14 SB_DQ25 SB_DQS0 AN2 MEM_B_DQS_P<0> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<26> BB11 SA_DQ26 SA_DQS1 AU8 MEM_A_DQS_P<1> 28 29 90 90 31 30 MEM_B_DQ<26> BF17 SB_DQ26 SB_DQS1 AW4 MEM_B_DQS_P<1> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<27> BA12 SA_DQ27 SA_DQS2 BD5 MEM_A_DQS_P<2> 28 29 90 90 31 30 MEM_B_DQ<27> BJ18 SB_DQ27 SB_DQS2 BF9 MEM_B_DQS_P<2> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<28> BE8 SA_DQ28 SA_DQS3 BC10 MEM_A_DQS_P<3> 28 29 90 90 31 30 MEM_B_DQ<28> BF13 SB_DQ28 SB_DQS3 BH15 MEM_B_DQS_P<3> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<29> BA10 SA_DQ29 SA_DQS4 BB51 MEM_A_DQS_P<4> 28 29 90 90 31 30 MEM_B_DQ<29> BH13 SB_DQ29 SB_DQS4 BH51 MEM_B_DQS_P<4> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<30> BD11 SA_DQ30 SA_DQS5 BD55 MEM_A_DQS_P<5> 28 29 90 90 31 30 MEM_B_DQ<30> BH17 SB_DQ30 SB_DQS5 BF57 MEM_B_DQS_P<5> 30 31 90
BI BI BI BI
C 90 29 28
90 29 28
BI MEM_A_DQ<31>
MEM_A_DQ<32>
BE12
BB49
SA_DQ31
SA_DQ32
SA_DQS6
SA_DQS7
BD61
AV61
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
BI 28 29 90
28 29 90
90 31 30
90 31 30
BI MEM_B_DQ<31>
MEM_B_DQ<32>
BG18
BH49
SB_DQ31
SB_DQ32
SB_DQS6
SB_DQS7
AY65
AN64
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
BI 30 31 90
30 31 90
C
BI BI BI BI
90 29 28 MEM_A_DQ<33> AY49 SA_DQ33 90 31 30 MEM_B_DQ<33> BF47 SB_DQ33
BI BI
90 29 28 MEM_A_DQ<34> BE52 SA_DQ34 SA_MA0 BD27 MEM_A_A<0> 28 29 32 90 90 31 30 MEM_B_DQ<34> BH53 SB_DQ34 SB_MA0 BF31 MEM_B_A<0> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<35> BD51 SA_DQ35 SA_MA1 BA28 MEM_A_A<1> 28 29 32 90 90 31 30 MEM_B_DQ<35> BG50 SB_DQ35 SB_MA1 BH31 MEM_B_A<1> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<36> BD49 SA_DQ36 SA_MA2 BB27 MEM_A_A<2> 28 29 32 90 90 31 30 MEM_B_DQ<36> BF49 SB_DQ36 SB_MA2 BB37 MEM_B_A<2> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<37> BE48 SA_DQ37 SA_MA3 AW26 MEM_A_A<3> 28 29 32 90 90 31 30 MEM_B_DQ<37> BH47 SB_DQ37 SB_MA3 BC34 MEM_B_A<3> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<38> BA52 SA_DQ38 SA_MA4 BB23 MEM_A_A<4> 28 29 32 90 90 31 30 MEM_B_DQ<38> BF53 SB_DQ38 SB_MA4 BF27 MEM_B_A<4> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<39> AY51 SA_DQ39 SA_MA5 BA24 MEM_A_A<5> 28 29 32 90 90 31 30 MEM_B_DQ<39> BJ50 SB_DQ39 SB_MA5 BB33 MEM_B_A<5> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<40> BC54 SA_DQ40 SA_MA6 AY21 MEM_A_A<6> 28 29 32 90 90 31 30 MEM_B_DQ<40> BF55 SB_DQ40 SB_MA6 BH27 MEM_B_A<6> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<41> AY53 SA_DQ41 SA_MA7 BD21 MEM_A_A<7> 28 29 32 90 90 31 30 MEM_B_DQ<41> BH55 SB_DQ41 SB_MA7 BG30 MEM_B_A<7> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<42> AW54 SA_DQ42 SA_MA8 BC22 MEM_A_A<8> 28 29 32 90 90 31 30 MEM_B_DQ<42> BJ58 SB_DQ42 SB_MA8 BH29 MEM_B_A<8> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<43> AY55 SA_DQ43 SA_MA9 BB21 MEM_A_A<9> 28 29 32 90 90 31 30 MEM_B_DQ<43> BH59 SB_DQ43 SB_MA9 BF29 MEM_B_A<9> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<44> BD53 SA_DQ44 SA_MA10 AW38 MEM_A_A<10> 28 29 32 90 90 31 30 MEM_B_DQ<44> BJ54 SB_DQ44 SB_MA10 AY37 MEM_B_A<10> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<45> BB53 SA_DQ45 SA_MA11 AW22 MEM_A_A<11> 28 29 32 90 90 31 30 MEM_B_DQ<45> BG54 SB_DQ45 SB_MA11 BJ30 MEM_B_A<11> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<46> BE56 SA_DQ46 SA_MA12 BA20 MEM_A_A<12> 28 29 32 90 90 31 30 MEM_B_DQ<46> BG58 SB_DQ46 SB_MA12 AW30 MEM_B_A<12> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<47> BA56 SA_DQ47 SA_MA13 BB45 MEM_A_A<13> 28 29 32 90 90 31 30 MEM_B_DQ<47> BF59 SB_DQ47 SB_MA13 BA40 MEM_B_A<13> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<48> BD57 SA_DQ48 SA_MA14 BE20 MEM_A_A<14> 28 29 32 90 90 31 30 MEM_B_DQ<48> BA64 SB_DQ48 SB_MA14 BB29 MEM_B_A<14> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<49> BF61 SA_DQ49 SA_MA15 AW18 MEM_A_A<15> 28 29 32 90 90 31 30 MEM_B_DQ<49> BC62 SB_DQ49 SB_MA15 BE28 MEM_B_A<15> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<50> BA60 SA_DQ50 90 31 30 MEM_B_DQ<50> AU62 SB_DQ50
BI BI
90 29 28 MEM_A_DQ<51> BB61 SA_DQ51 90 31 30 MEM_B_DQ<51> AW64 SB_DQ51
BI BI
90 29 28 MEM_A_DQ<52> BE60 SA_DQ52 90 31 30 MEM_B_DQ<52> BA62 SB_DQ52
BI BI
90 29 28 MEM_A_DQ<53> BD63 SA_DQ53 90 31 30 MEM_B_DQ<53> BC64 SB_DQ53
BI BI
90 29 28 MEM_A_DQ<54> BB59 SA_DQ54 90 31 30 MEM_B_DQ<54> AU64 SB_DQ54
BI BI
90 29 28 MEM_A_DQ<55> BC58 SA_DQ55 90 31 30 MEM_B_DQ<55> AW62 SB_DQ55
BI BI
90 29 28 MEM_A_DQ<56> AW58 SA_DQ56 90 31 30 MEM_B_DQ<56> AR64 SB_DQ56
BI BI
B 90 29 28
90 29 28
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AY59
AL60
SA_DQ57
SA_DQ58
90 31 30
90 31 30
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AT65
AL64
SB_DQ57
SB_DQ58
B
90 29 28 MEM_A_DQ<59> AP61 SA_DQ59 90 31 30 MEM_B_DQ<59> AM65 SB_DQ59
BI BI
90 29 28 MEM_A_DQ<60> AW60 SA_DQ60 90 31 30 MEM_B_DQ<60> AR62 SB_DQ60
BI BI
90 29 28 MEM_A_DQ<61> AY57 SA_DQ61 90 31 30 MEM_B_DQ<61> AT63 SB_DQ61
BI BI
90 29 28 MEM_A_DQ<62> AN60 SA_DQ62 90 31 30 MEM_B_DQ<62> AL62 SB_DQ62
BI BI
90 29 28 MEM_A_DQ<63> AR60 SA_DQ63 90 31 30 MEM_B_DQ<63> AM63 SB_DQ63
BI BI
A SYNC_DATE=01/13/2012 A
PAGE TITLE
D D
=PP3V3_S0_CPU_VCCIO_SEL 8 98 45 15 13 8 =PPVCORE_S0_CPU
=PPVCORE_S0_CPU 8 13 15 45 98
For Future Compatibility
1
R1320 R46 U1000 H35
10K
5%
R42 IVY-BRIDGE H31
1/16W
R40 BGA H29
MF-LF
=PPVCCSA_S0_CPU 402
=PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
16 13 8 2 R36 (6 OF 11) H25
R34
CORE POWER G44
OMIT_TABLE
PLACE_NEAR=R1310.1:2.54mm =PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
1
W17 U1000 VCCIO_SEL AJ8 CPU_VCCIO_SEL R29 G40
R1300 1 W15 IVY-BRIDGE R27 G38
75 R1302
130 W12 BGA AV23 R23 G34
1% PLACE_NEAR=U1000.A50:2.54mm =PP1V5_S3_CPU_VCCDQ 8 16
1/16W 1%
MF-LF 1/16W
U17 (9 OF 11) AT23 R21 G32
2
402 MF-LF OMIT_TABLE VCCDQ
402
U15 AP23 N45 G28
R1312 2
89 65 CPU_VIDSOUT 402 1/16W 0 1 2 5% MF-LF CPU_VIDSOUT_R U12 AL23 N43 G26
BI
T16 N39 F45
R1311
89 65 CPU_VIDSCLK 402 1/16W 0 1 2 5% MF-LF CPU_VIDSCLK_R T14 AK65 =PP1V8_S0_CPU_VCCPLL_R 8 15 N37 F43
OUT
T11 AK63 N33 F41
R1310 VCCPLL
89 65 CPU_VIDALERT_L 402 1/16W 1 2 5% MF-LF CPU_VIDALERT_L_R N18 AK61 N30 F37
IN
N16
VCCSA N26 F35
43 PLACE_NEAR=U1000.B51:38mm
N14 AV21 =PP1V05_S0_CPU_VCCPQE 8 15 N24 F31
C =PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
=PPVCORE_S0_CPU 8 13 15 45 98
M12
M11
AL21 M42
M40
E44
E40
C
=PPVCORE_S0_CPU_VCCAXG 8 13 14 =PPVCORE_S0_CPU_VCCAXG 8 13 14 16
16 L18 BJ60 M36 E38
BG2
TP_DC_TEST_BF65
DC_TEST_BH1_BG2
J38
J34
B31
B29
B
CPU_VCC_VALSENSE_P D47 VCC_VAL_SENSE DC_TEST_BG64 BG64 DC_TEST_BG64_BH65 J32 A44
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
CPU POWER
DRAWING NUMBER SIZE
D
BJ16
BJ12
AV38
AV31
AE57
AD16
K1
J64
D
BJ8 AV25 AD14 J60 =PPVCORE_S0_CPU_VCCAXG =PP1V5_S3_CPU_VCCDDR
16 13 8 8 11 16 27
BG60 AV19 AD7 J56
C BE18
BE14
AR47
AR41
V9
V5
G30
G24
AA64
AA62
AV27
AU45
AT12
AR58
AH14
AH11 C
AR56 AF16
BE10 AR35 U64 G20 AA60 AU43
IO POWER DDR3
AR49 AE17
BD7 AR22 U60 G12 Y56 AU37
AR20 AE15
BD3 AP65 U57 G8 W64 AU33
AR18 AE12
BC60 AP63 T7 VSS VSS F39 W62 AU30
AR16 AD11
BC56 AP57 T3 F33 W60 AU26
AR14 AC17
BC52 AP50 T1 F27 V65 AU24
AP55 AC15
BC48 AP44 R57 E60 V63 AT46
VAXG AP53 AC12
BC44 VSS VSS AP38 R50 E56 V61 AT42
AP48 AB16
BC40 AP31 R44 E52 V58 AT40
AN58 AB14
BC36 AP25 R38 E48 V56 VDDQ AT36
AN56 Y16
BC32 AP19 R31 E46 T65 AT34
AN52 Y14
BC28 AP17 R25 E42 T63 AT29
AN49 Y11
BC26 AP15 R19 E36 T61 AT27
B BA58
BA54
AM61
AM7
N47
N41
D33
D27
N60
N58
AP40
AP36
B
BA50 AM3 N35 C58 N56 AP34
BA46 AM1 N28 C54 N52 AP29
A A
PAGE TITLE
PLACEMENT_NOTE (C1600-C16C7):
98 45 13 8 =PPVCORE_S0_CPU
Place on bottom side of U1000
U100.
1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612 1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
D 2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
D
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C16A0 1
C16A1 1
C16A2 1
C16A3 1
C16A4 1
C16A5 1
C16A6 1
C16A7 1
C16A8 1
C16A9 1
C16B0 1
C16B1 1
C16B2 1
C16B3 1
C16B4 1
C16B5 1
C16B6 1
C16B7 1
C16B8 1
C16B9
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
PLACEMENT_NOTE (C1620-C1623):
Place near inductors on bottom side. NOSTUFF NOSTUFF NOSTUFF NOSTUFF
Place near U1000 on bottom side
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1620 1
C1621 1
C1622 1
C1623 1 C1690 1 C1691 1 C1698 1 C1693 1 C1694 1 C1695 1 C1696 1 C1699
10UF 10UF 10UF 10UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V
2
4V
X6S 2
4V
X6S 2
4V
X6S 2
4V
X6S 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 2V
X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
C PLACEMENT_NOTE (C1624-C16D5): C
Place near inductors on bottom side. NOSTUFF NOSTUFF NOSTUFF NOSTUFF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C1624 1
C1625 1
C1626 1
C1627 1
C1628 1
C1629 1
C1630 1
C1631 1
C1632 1
C1633 1
C1634 1
C1635 1
C1636 1
C1637 1
C1638 1
C1639 1
C16D0 1
C16D1 1
C16D2 1
C16D3 1
C16D4 1
C16D5
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V
2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
PLACEMENT_NOTE (C1640-C1645):
PLACEMENT_NOTE (C1646-C1671):
B 1
C1646 1
C1647 1
C1648 1
C1649 1
C1650 1
C1651 1
C1652 1
C1653 1
C1654 1
C1655 1
C1656 1
C1657 1
C1658
R1600
0
=PP1V8_S0_CPU_VCCPLL_R 8 13 B
8 =PP1V8_S0_CPU_VCCPLL 1 2
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF PLACE_NEAR=U1000.AK61:5MM
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5%
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V 1/16W CRITICAL
1
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
MF-LF
402
1
C1685 1
C1686 C1687
1UF
10%
1UF
10%
220UF
20% (Z = 1.2mm, place on short side behind CPU)
10V 10V
2 X6S-CERM 2 X6S-CERM 2 2.5V
TANT
0402 0402 B16
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659 1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665 1
C1666 1
C1667 1
C1668 1
C1669 1
C1670 1
C1671
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF CPU VCCPLL Low pass filter
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
PLACEMENT_NOTE (C1672-C1681):
1
C1672 1
C1673 1
C1674 1
C1675 1
C1676 1
C1677 1
C1678 1
C1679 1
C1680 1
C1681
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
CRITICAL CRITICAL
1
C1682 1
C1683
330UF-6MOHM 330UF-6MOHM (Z = 1.5mm, place on tall side next to CPU & under heat pipe)
20% 20%
3 2 2.0V 3 2 2.0V
A POLY-TANT
D15T-ECGLT-COMBO
POLY-TANT
D15T-ECGLT-COMBO SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402 DRAWING NUMBER SIZE
1%
4.18.0
1/4W
MF
1
C1684 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0603 1UF THE INFORMATION CONTAINED HEREIN IS THE
10%
10V
PROPRIETARY PROPERTY OF APPLE INC.
2 X6S-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VAXG DECOUPLING
INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM , 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
PLACEMENT_NOTE (C1700-C1708):
14 13 8 =PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000
U100.
PLACEMENT_NOTE (C1718-C1723):
NOSTUFF NOSTUFF
1
C1718 1
C1719 1
C1720 1
C1721 1
C1722 1
C1723 1
C1724 1
C1725
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S
0402 0402 0402 0402 0402 0402 0402 0402
PLACEMENT_NOTE (C1726-C1731):
NOSTUFF NOSTUFF
1 C1726 1 C1727 1 C1728 1 C1729 1 C1730 1 C1731 1 C1732 1 C1733
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S
0603 0603 0603 0603 0603 0603 0603 0603
PLACEMENT_NOTE (C1734-C1735):
1
C1738 1
C1739 1
C1740 1
C1741 1
C1742 1
C1743 1
C1744 1
C1745 1
C1746 1
C1747
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
1 C1758 1 C1759 1 C1760 1 C1761 1 C1762
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 1UF 1UF 1UF 1UF 1UF
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10% 10% 10% 10% 10%
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 10V 10V 10V 10V 10V
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402
1
C1748 1
C1749 1
C1750 1
C1751 1
C1752 1
C1753 1
C1754 1
C1755
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
1
C1763 1
C1764 1
C1765 1
C1766 1
C1767
2 2 2 2 2 2 2 2
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM 10UF 10UF 10UF 10UF 10UF
B 0603 0603 0603 0603 0603 0603 0603 0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
B
Place near inductors on bottom side
1 C1756
330UF-0.006OHM CRITICAL
20%
1
2
2V
POLY
C1768
CASE-D2-SM 330UF-6MOHM (Z = 1.5mm, place on tall side next to CPU & under heat pipe)
20%
3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
R1700
0.010
1 2 =PP1V5_S3_CPU_VCCDQ 8 13
1%
1/4W
1
MF
0603
C1757
1UF
10%
10V
2 X6S-CERM
0402
A SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER SIZE
OMIT_TABLE OMIT_TABLE
A20 C38 BG34 E12
91 25 IN SYSCLK_CLK32K_RTC RTCX1 U1800 FWH0/LAD0 LPC_AD_R<0> 17 92 38 7 IN PCIE_ENET_D2R_N PERN1 U1800 SMBALERT*/GPIO11 SMBUS_PCH_ALERT_L 17
C20
RTCX2 PANTHERPOINT FWH1/LAD1 A38 LPC_AD_R<1> PCIE_ENET_D2R_P BJ34
PERP1 PANTHERPOINT
NC MOBILE
17 92 38 7 IN
MOBILE SMBCLK H14 SMBUS_PCH_CLK OUT 44 92
B37 LPC_AD_R<2> =PP3V3_S0_PCH PCIE_ENET_R2D_C_N AV32
FCBGA FWH2/LAD2 17 8 23 92 38 7 OUT PETN1 FCBGA C9
C37 AU32 SMBDATA SMBUS_PCH_DATA BI 44 92
(1 OF 10) FWH3/LAD3 LPC_AD_R<3> 17 92 38 7 OUT PCIE_ENET_R2D_C_P PETP1 (2 OF 10)
D20 (IPU) 1
17 RTC_RESET_L RTCRST* R1820
SMBUS
D36 LPC_FRAME_R_L PCIE_AP_D2R_N BE34
FWH4/LFRAME* 17 92 34 IN PERN2
G22
10K BF34 A12
17 PCH_SRTCRST_L SRTCRST* E36 5% 92 34 IN PCIE_AP_D2R_P PERP2 SML0ALERT*/GPIO60 USB_EXTB_SEL_XHCI OUT 17 26
TP_LPC_DREQ0_L
RTC
LPC
(IPU) LDRQ0* 7 1/20W BB32
K22 K36 MF 92 34 OUT PCIE_AP_R2D_C_N PETN2 C8
17 PCH_INTRUDER_L INTRUDER* LDRQ1*/GPIO23 TBT_PWR_EN_PCH OUT 25
2 201 AY32 SML0CLK SML_PCH_0_CLK OUT 44 92
(IPU) 92 34 PCIE_AP_R2D_C_P PETP2
D 17 PCH_INTVRMEN_L C17
INTVRMEN SERIRQ V5 LPC_SERIRQ BI 7 41 43
9
OUT
IN PCIE_FW_D2R_N BG36
PERN3
SML0DATA G12 SML_PCH_0_DATA BI 44 92
D
PCIE_FW_D2R_P BJ36
9 IN PERP3
HDA_BIT_CLK_R N34 AM3 SATA_HDD_D2R_N PCIE_FW_R2D_C_N AV34 C13 USB_EXTD_SEL_XHCI
92 17 HDA_BCLK SATA0RXN IN 39 91 9 OUT PETN3 SML1ALERT*/PCHHOT*/GPIO74 OUT 17
AM1 SATA_HDD_D2R_P PCIE_FW_R2D_C_P AU34
SATA0RXP IN 39 91 9 OUT PETP3 E14
L34 AP7 SML1CLK/GPIO58 SML_PCH_1_CLK OUT 44 92
92 17 HDA_SYNC_R HDA_SYNC (IPD-BOOT) SATA0TXN SATA_HDD_R2D_C_N OUT 39 91 BF36 M16
AP5 9 IN PCIE_EXCARD_D2R_N PERN4 SML1DATA/GPIO75 SML_PCH_1_DATA BI 44 92
VSel strap not functional (VCCVRM = 1.8V) SATA0TXP SATA_HDD_R2D_C_P OUT 39 91
BE36
T10 9 IN PCIE_EXCARD_D2R_P PERP4
PCI-E*
17 PCH_SPKR SPKR (IPD-PLTRST#) AM10 AY34
SATA1RXN SATA_ODD_D2R_N IN 9 91 9 OUT PCIE_EXCARD_R2D_C_N PETN4
AM8 SATA_ODD_D2R_P PCIE_EXCARD_R2D_C_P BB34
SATA1RXP PETP4
IHDA
K34 IN 9 91 9 OUT
C-LINK
92 17 HDA_RST_R_L HDA_RST* AP11
SATA1TXN SATA_ODD_R2D_C_N OUT 9 91
BG37 M7
AP10 7 TP_PCIE_5_D2RN PERN5 (IPU/IPD) CL_CLK1 TP_CLINK_CLK 7
E34 SATA1TXP SATA_ODD_R2D_C_P OUT 9 91
BH37
92 53 IN HDA_SDIN0 HDA_SDIN0 (IPD) 7 TP_PCIE_5_D2RP PERP5 T11
G34 AD7 AY36 (IPU/IPD) CL_DATA1 TP_CLINK_DATA 7
7 TP_HDA_SDIN1 HDA_SDIN1 (IPD) SATA2RXN TP_SATA_C_D2RN 7 TP_PCIE_5_R2D_CN PETN5
TP_HDA_SDIN2 C34 AD5 TP_SATA_C_D2RP TP_PCIE_5_R2D_CP BB36 P10 TP_CLINK_RESET_L
7 HDA_SDIN2 (IPD) SATA2RXP 7 PETP5 CL_RST1* 7
SATA
ENET_MEDIA_SENSE_RDIV N32 TP_PCIE_7_D2RN BG40
17 IN HDA_DOCK_RST*/GPIO13 AF1 7 PERN7 AB38
SATA3TXP TP_SATA_D_R2D_CP 7 BJ40 CLKOUT_PEG_A_P TP_PCIE_CLK100M_PEGAP
7 TP_PCIE_7_D2RP PERP7
Y7 TP_SATA_E_D2RN TP_PCIE_7_R2D_CN AY40
J3 SATA4RXN 7 7 PETN7
24 IN XDP_PCH_TCK JTAG_TCK (IPD) Y5
=PP1V05_S0_PCH_VCCIO_SATA 8 21 23
BB40
SATA4RXP TP_SATA_E_D2RP 7 7 TP_PCIE_7_R2D_CP PETP7 AV22
H7 AD3 PLACE_NEAR=U1800.Y11:2.54mm CLKOUT_DMI_N DMI_CLK100M_CPU_N OUT 11 89
XDP_PCH_TMS JTAG_TMS (IPU) SATA4TXN TP_SATA_E_R2D_CN
JTAG
24 IN 7
1 TP_PCIE_8_D2RN BE38 AU22 DMI_CLK100M_CPU_P
AD1 R1830 7 PERN8 CLKOUT_DMI_P OUT 11 89
K5 SATA4TXP TP_SATA_E_R2D_CP 7 BC38
24 IN XDP_PCH_TDI JTAG_TDI (IPU) 37.4 7 TP_PCIE_8_D2RP PERP8
Y3 1% AW38
H1 SATA5RXN TP_SATA_F_D2RN 7 1/20W 7 TP_PCIE_8_R2D_CN PETN8
24 OUT XDP_PCH_TDO JTAG_TDO Y1 MF AY38 AM12
C SATA5RXP
SATA5TXN AB3
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
7
7
2 201
=PP1V05_S0_PCH 8 23
7 TP_PCIE_8_R2D_CP PETP8 CLKOUT_DP_N
CLKOUT_DP_P AM13
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
OUT
OUT
9
9
C
AB1 TP_SATA_F_R2D_CP PCIE_CLK100M_ENET_N Y40
SATA5TXP 7 92 38 7 OUT CLKOUT_PCIE0N
Y39 Controlled by PCIECLKRQ5#
T3 92 38 7 OUT PCIE_CLK100M_ENET_P CLKOUT_PCIE0P
SPI_CLK_R 1
92 43 OUT SPI_CLK Y11 R1831 BF18
SATAICOMPO 91 PCH_SATAICOMP J2 CLKIN_DMI_N PCIE_CLK100M_PCH_N IN 17 92
Y14 Y10
49.9 39 17 IN SSD_CLKREQ_L PCIECLKRQ0*/GPIO73 BE18
92 43 OUT SPI_CS0_R_L SPI_CS0* SATAICOMPI 1% CLKIN_DMI_P PCIE_CLK100M_PCH_P IN 17 92
SPI
1/20W
T1 MF AB49
TP_SPI_CS1_L SPI_CS1* AB12 201 92 9 PCIE_CLK100M_FW_N CLKOUT_PCIE1N
2
SATA3RCOMPO AB47
V4 AB13 PLACE_NEAR=U1800.AB12:2.54mm 92 9 PCIE_CLK100M_FW_P CLKOUT_PCIE1P BJ30
92 43 OUT SPI_MOSI_R SPI_MOSI (IPD-BOOT) SATA3COMPI 91 PCH_SATA3COMP CLKIN_GND1_N PCH_CLKIN_GNDN1 17
AH1 PCH_SATA3RBIAS FW_CLKREQ_L M1 BG30 PCH_CLKIN_GNDP1
U3 SATA3RBIAS 17 PCIECLKRQ1*/GPIO18 CLKIN_GND1_P 17
92 43 IN SPI_MISO SPI_MISO (IPU)
PLACE_NEAR=U1800.AH1:2.54mm
SATALED* P3 PCH_SATALED_L 1 PCIE_CLK100M_AP_N AA48
CLKOUT_PCIE2N
17 R1832 92 34 OUT
CLOCKS
750 PCIE_CLK100M_AP_P AA47 G24 PCH_CLK96M_DOT_N
V14 92 34 OUT CLKOUT_PCIE2P CLKIN_DOT_96N IN 17 92
=PPVRTC_G3_PCH 8 18 21 SATA0GP/GPIO21 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 24 1% E24
P1 1/20W V10 CLKIN_DOT_96P PCH_CLK96M_DOT_P IN 17 92
SATA1GP/GPIO19 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 24 MF 34 17 IN AP_CLKREQ_L PCIECLKRQ2*/GPIO20
(IPU) 2 201
Y37
R1802 1
1 PCIE_CLK100M_EXCARD_N
R1803 92 9 OUT CLKOUT_PCIE3N AK7
Y36 CLKIN_SATA_N PCH_CLK100M_SATA_N IN 17 92
20K 20K 92 9 OUT PCIE_CLK100M_EXCARD_P CLKOUT_PCIE3P AK5
5% 5% CLKIN_SATA_P PCH_CLK100M_SATA_P IN 17 92
1/20W 1/20W A8
1 1 EXCARD_CLKREQ_L
R1800 R1801 MF MF 17 IN PCIECLKRQ3*/GPIO25
201 2
330K 1M 2 201
5% 5% Y43 K45
1/20W 1/20W 7 TP_PCIE_CLK100M_PE4N CLKOUT_PCIE4N REFCLK14IN PCH_CLK14P3M_REFCLK IN 17 92
MF MF RTC_RESET_L 17
Y45
201 2
2 201
7 TP_PCIE_CLK100M_PE4P CLKOUT_PCIE4P
PCH_SRTCRST_L 17
B 10%
10V
X5R 2 2
10%
10V
X5R 17 LPC_AD_R<2> R1862 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
LPC_AD<2>
BI
BI 7 41 43 82 92 38 17 7 IN ENET_CLKREQ_L L14
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
XTAL25_OUT V49
NC B
402 402
17 LPC_AD_R<3> R1863 33 1 2 LPC_AD<3> BI 7 41 43 82 92
5% 1/20W MF 201 23 21 8 =PP1V05_S0_PCH_VCCDIFFCLK
17 LPC_FRAME_R_L R1864 33 1 2 LPC_FRAME_L OUT 7 41 43 82 92 7 TP_PCIE_CLK100M_PEBN AB42
CLKOUT_PEG_B_N
5% 1/20W MF 201 AB40
7 TP_PCIE_CLK100M_PEBP CLKOUT_PEG_B_P 1
92 17 HDA_BIT_CLK_R R1810 33 1 2 HDA_BIT_CLK OUT 53 92
R1890
PEGCLKRQB_L_GPIO56 E6
PLACE_NEAR=U1800.N34:1.27mm 5% 1/20W MF 201 17 PEG_B_CLKRQ*/GPIO56 90.9
1%
92 17 HDA_SYNC_R R1811 33 1 2 HDA_SYNC OUT 53 92 1/20W
PLACE_NEAR=U1800.L34:1.27mm 5% 1/20W MF 201 V40 MF
92 71 OUT PEG_CLK100M_N CLKOUT_PCIE6N 201 2
92 17 HDA_RST_R_L R1812 33 1 2 HDA_RST_L OUT 53 92 V42 PLACE_NEAR=U1800.Y47:2.54mm
PLACE_NEAR=U1800.K34:1.27mm 5% 1/20W MF 201 92 71 OUT PEG_CLK100M_P CLKOUT_PCIE6P Y47
XCLK_RCOMP PCH_XCLK_RCOMP
92 25 17 HDA_SDOUT_R R1813 33 1 2 HDA_SDOUT OUT 53 92
T13
PLACE_NEAR=U1800.A36:1.27mm 5% 1/20W MF 201 17 9 IN PEG_CLKREQ_L PCIECLKRQ6*/GPIO45
=PP3V3_SUS_PCH_GPIO 8 18 19 20
CLOCKS
92 35 OUT
NO STUFF V37
PCIE_CLK100M_TBT_P CLKOUT_PCIE7P
FLEX
92 35 OUT F47
CLKOUTFLEX1/GPIO65 TP_PCH_GPIO65_CLKOUTFLEX1
R1840 K12 (IPD-PWROK)
9
0 37 17 IN TBT_CLKREQ_L PCIECLKRQ7*/GPIO46
89 11 ITPCPU_CLK100M_N 1 2 (IPU-RSMRST#) H47
CLKOUTFLEX2/GPIO66 TP_PCH_GPIO66_CLKOUTFLEX2 9
R1877 4.7K 1 2 PCH_SPKR 17 NO STUFF 5%
AK14 (IPD-PWROK)
5% 1/20W MF 201 1/20W 89 24 ITPXDP_CLK100M_N CLKOUT_ITPXDP_N
R1878 4.7K 1 2 PCH_SATALED_L 17
R1841 MF
AK13 K49
5% 1/20W MF 201 201 89 24 ITPXDP_CLK100M_P CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 TP_PCH_GPIO67_CLKOUTFLEX3 9
0 (IPD-PWROK)
R1834 10K 1 2 DP_AUXCH_ISOL 24 25 89 11 ITPCPU_CLK100M_P 1 2
5% 1/20W MF 201
R1833 10K 1 2 SATARDRVR_EN 24 5%
5% 1/20W MF 201 1/20W
MF R1872
R1842 10K 1 2 FW_CLKREQ_L 17 201 604
5% 1/20W MF 201 91 25 IN SYSCLK_CLK25M_SB 1 2 SYSCLK_CLK25M_SB_R 17 91
R1869 10K 1 2 AP_CLKREQ_L 17 34
R1844 10K 1 2
5% 1/20W MF 201
EXCARD_CLKREQ_L
1%
1/16W
1.8V -> 1.1V
17
MF-LF 1
R1845 10K 1 2
5% 1/20W MF 201
JTAG_DPMUXUC_TRST_L 17 Unused clock terminations for FCIM Mode 402 R1873
5% 1/20W MF 201 1K
R1847 10K 1 2 ENET_CLKREQ_L 7 17 38 1%
5% 1/20W MF 201 92 17 PCH_CLK96M_DOT_P R1891 10K 1 2 1/20W
R1814 10K 2 1 PEG_CLKREQ_L
A R1815 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
TBT_CLKREQ_L
9 17
17 37
92 17 PCH_CLK96M_DOT_N R1892 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
MF
2 201 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
92 17 PCH_CLK100M_SATA_P R1893 10K 1 2 PAGE TITLE
R1843 10K 1 2 SSD_CLKREQ_L
R1846 10K 1 2
5% 1/20W MF 201
PEGCLKRQA_L_GPIO47
17 39
17 GPU:2P
92 17 PCH_CLK100M_SATA_N R1894 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH SATA/PCIe/CLK/LPC/SPI
5% 1/20W MF 201 DRAWING NUMBER SIZE
GPU:1P R1848 10K 1 2 PEGCLKRQB_L_GPIO56 R1880 10K 1 2 PEGCLKRQB_L_GPIO56 PCIE_CLK100M_PCH_P R1895 10K 1 2
R1853 10K 1 2
5% 1/20W MF 201
SMBUS_PCH_ALERT_L
17
17
5% 1/20W MF 201
17 92 17
R1855 10K 1 2
5% 1/20W MF 201
USB_EXTD_SEL_XHCI 17
92 17 PCH_CLK14P3M_REFCLK R1897 10K 1 2
5% 1/20W MF 201
4.18.0
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1879 10K 1 2 ENET_MEDIA_SENSE_RDIV 17 17 PCH_CLKIN_GNDP1 R1870 10K 1 2 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
17 PCH_CLKIN_GNDN1 R1871 10K 1 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. 5% 1/20W MF 201
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP1V05_S0_PCH_VCCIO_PCIE 8
PLACE_NEAR=U1800.BJ24:12.7mm
R19051 1
R1900
10K 49.9
5% 1%
1/20W 1/20W
MF MF
201 2 2 201 OMIT_TABLE OMIT_TABLE
89 10 IN DMI_N2S_N<0> BC24 DMI0RXN U1800 FDI_RXN0 BJ14 =FDI_DATA_N<0> IN 9 18 9 OUT LVDS_IG_BKL_ON J47 L_BKLTEN U1800 SDVO_TVCLKINN AP43 TP_SDVO_TVCLKINN 7
DMI_N2S_N<1> BE20 PANTHERPOINT AY14 =FDI_DATA_N<1> LVDS_IG_PANEL_PWR M45 PANTHERPOINT (IPD) AP45 TP_SDVO_TVCLKINP
89 10 IN DMI1RXN MOBILE FDI_RXN1 IN 9 18 9 OUT L_VDD_EN SDVO_TVCLKINP 7
MOBILE (IPD)
D 89 10
89 10
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
BG18
BG20
DMI2RXN
DMI3RXN
FCBGA
(3 OF 10)
FDI_RXN2
FDI_RXN3
BE14
BH13
=FDI_DATA_N<2>
=FDI_DATA_N<3>
IN
IN
9
9
7 OUT LVDS_IG_BKL_PWM P45 L_BKLTCTL FCBGA
(4 OF 10)
SDVO_STALLN
(IPD)
AM42
AM40
TP_SDVO_STALLN 7 D
BC12 T40 SDVO_STALLP TP_SDVO_STALLP 7
BE24 FDI_RXN4 =FDI_DATA_N<4> IN 9 9 OUT LVDS_IG_DDC_CLK L_DDC_CLK (IPD)
89 10 IN DMI_N2S_P<0> DMI0RXP BJ12 K47 AP39
BC20 FDI_RXN5 =FDI_DATA_N<5> IN 9 9 OUT LVDS_IG_DDC_DATA L_DDC_DATA SDVO_INTN TP_SDVO_INTN 7
89 10 IN DMI_N2S_P<1> DMI1RXP BG10 (IPD-PLTRST#) (IPD) AP40
BJ18 FDI_RXN6 =FDI_DATA_N<6> IN 9 T45 SDVO_INTP TP_SDVO_INTP 7
89 10 IN DMI_N2S_P<2> DMI2RXP BG9 7 TP_LVDS_IG_CTRL_CLK L_CTRL_CLK (IPD)
BJ20 FDI_RXN7 =FDI_DATA_N<7> IN 9 P39
89 10 IN DMI_N2S_P<3> DMI3RXP 7 TP_LVDS_IG_CTRL_DATA L_CTRL_DATA P38
BG14 SDVO_CTRLCLK DPA_IG_DDC_CLK 83
FDI_RXP0 =FDI_DATA_P<0> IN 9
AF37 M39
AW24 BB14 PCH_LVDS_IBG LVD_IBG SDVO_CTRLDATA DPA_IG_DDC_DATA 83
89 10 OUT DMI_S2N_N<0> DMI0TXN FDI_RXP1 =FDI_DATA_P<1> IN 9 PLACE_NEAR=U1800.AF37:2.54mm AF36 (IPD-PLTRST#)
AW20 BF14 7 TP_PCH_LVDS_VBG LVD_VBG AT49
89 10 OUT DMI_S2N_N<1> DMI1TXN FDI_RXP2 =FDI_DATA_P<2> IN 9 R19501 DDPB_AUXN DPA_IG_AUX_CH_N 83 95
89 10 DMI_S2N_N<2> BB18 DMI2TXN FDI_RXP3 BG13 =FDI_DATA_P<3> 9 2.37K AE48 LVD_VREFH DDPB_AUXP AT47 DPA_IG_AUX_CH_P 83 95
OUT IN
AV18 BE12 1% AE47 AT40
89 10 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 =FDI_DATA_P<4> IN 9 1/20W LVD_VREFL DDPB_HPD DPA_IG_HPD 9 82
MF
DMI
FDI
BG12 =FDI_DATA_P<5>
LVDS
89 10 DMI_S2N_P<3> AU18 DMI3TXP 91 9 LVDS_IG_A_DATA_N<0> AN48 LVDSA_DATA0* DDPB_1P AV46 TP_DP_IG_B_MLP<1> 9
OUT OUT
FDI_INT AW16 FDI_INT OUT 10 89
AM47 AU48
91 9 OUT LVDS_IG_A_DATA_N<1> LVDSA_DATA1* DDPB_2N TP_DP_IG_B_MLN<2> 9
=PPVRTC_G3_PCH 8 17 21
BJ24 FDI_FSYNC0 AV12 =FDI_FSYNC<0> OUT 9 91 9 OUT LVDS_IG_A_DATA_N<2> AK47 LVDSA_DATA2* DDPB_2P AU47 TP_DP_IG_B_MLP<2> 9
PCH_DMI_COMP DMI_ZCOMP
BG25 FDI_FSYNC1 BC10 =FDI_FSYNC<1> OUT 9
1 91 9 OUT LVDS_IG_A_DATA_N<3> AJ48 LVDSA_DATA3* DDPB_3N AV47 TP_DP_IG_B_MLN<3> 9
DMI_IRCOMP R1915 DDPB_3P AV49 TP_DP_IG_B_MLP<3> 9
FDI_LSYNC0 AV14 =FDI_LSYNC<0> OUT 9 390K 91 9 OUT LVDS_IG_A_DATA_P<0> AN47 LVDSA_DATA0
BH21 5%
PCH_DMI2RBIAS DMI2RBIAS FDI_LSYNC1 BB10 =FDI_LSYNC<1> OUT 9 1/20W 91 9 OUT LVDS_IG_A_DATA_P<1> AM49 LVDSA_DATA1 P46
MF AK49 DDPC_CTRLCLK DPB_IG_DDC_CLK 83
PLACE_NEAR=U1800.BH21:2.54mm 2 201 91 9 OUT LVDS_IG_A_DATA_P<2> LVDSA_DATA2 P42
AJ47 DDPC_CTRLDATA DPB_IG_DDC_DATA 83
1
R1920 LVDS_IG_A_DATA_P<3> LVDSA_DATA3 (IPD-PLTRST#)
DSWVRMEN A18
91 9 OUT
PCH_DSWVRMEN AP47
750 DPB_IG_AUX_CH_N
SYSTEM POWER
DDPC_AUXN 83 95
1% C12
PCH_SUSACK_L DPWROK E22 PM_DSW_PWRGD LVDS_IG_B_CLK_N AF40 AP49 DPB_IG_AUX_CH_P
MANAGEMENT
1/20W 18 SUSACK* (IPU) IN 41 7 OUT LVDSB_CLK* DDPC_AUXP 83 95
MF AF39 AT38
2 201 K3 LVDS_IG_B_CLK_P LVDSB_CLK DDPC_HPD DPB_IG_HPD
WAKE* B9
7 OUT 9 82
41 25 IN PM_SYSRST_L SYS_RESET* PCIE_WAKE_L IN 7 18 34
1
C 70 41 24 IN PM_PCH_SYS_PWROK P12 SYS_PWROK CLKRUN*/GPIO32 N3 PM_CLKRUN_L BI 7 18 41 43
R1909
5%
100K 91 9
91 9
OUT LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
AH45
AH47
LVDSB_DATA0*
LVDSB_DATA1*
DDPC_0N
DDPC_0P
AY47
AY49
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
7
7
C
OUT
L22 1/20W
70 25 IN PM_PCH_PWROK PWROK SUS_STAT*/GPIO61 G8 LPC_PWRDWN_L OUT 7 25 41 43 MF 91 9 OUT LVDS_IG_B_DATA_N<2> AF49 LVDSB_DATA2* DDPC_1N AY43 TP_DP_IG_C_MLN<1> 7
2 201 9 LVDS_IG_B_DATA_N<3> AF45 LVDSB_DATA3* DDPC_1P AY45 TP_DP_IG_C_MLP<1> 7
70 PM_PCH_APWROK L10 APWROK SUSCLK/GPIO62 N14 PM_CLK32K_SUSCLK_R 42
OUT
IN OUT
DDPC_2N BA47 TP_DP_IG_C_MLN<2> 7
91 9 LVDS_IG_B_DATA_P<0> AH43 LVDSB_DATA0
89 27 11 PM_MEM_PWRGD B13 DRAMPWROK SLP_S5*/GPIO63 D10 PM_SLP_S5_L 18 41 70
OUT
DDPC_2P BA48 TP_DP_IG_C_MLP<2>
OUT OUT
91 9 LVDS_IG_B_DATA_P<1> AH49 LVDSB_DATA1
7
OUT BB47 TP_DP_IG_C_MLN<3>
C21 DDPC_3N 7
70 IN PM_RSMRST_L RSMRST* SLP_S4* H4 PM_SLP_S4_L OUT 7 18 27 34 38 40 41 70 91 9 OUT LVDS_IG_B_DATA_P<2> AF47 LVDSB_DATA2 BB49
AF43 DDPC_3P TP_DP_IG_C_MLP<3> 7
K16 9 LVDS_IG_B_DATA_P<3> LVDSB_DATA3
SLP_S3* F4
PCH_SUSWARN_L PM_SLP_S3_L OUT
18 SUSWARN*/SUSPWRDNACK/GPIO30 OUT 7 18 27 38 41 70
CRT
OUT
7 TP_CRT_IG_DDC_CLK T39 CRT_DDC_CLK DDPD_0N BB43 TP_DP_IG_D_MLN<0> 7
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP3V3_S0_PCH_GPIO 8 17 19 20 25 37
=PP3V3_S5_PCH 8
R1985 1K 1 2
5% 1/20W MF 201
PM_PWRBTN_L 18 24 41
7 18 34
R1999 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
5% 1/20W MF 201 MAKE_BASE=TRUE 0 PAGE TITLE
=TBT_WAKE_L
2
5%
1 IN 35 42
PCH DMI/FDI/PM/Graphics
1/20W
R1924 100K 2 1
5% 1/20W MF 201
PM_SLP_S3_L 7 18 27 38 41 70 MF
201
DRAWING NUMBER
051-9589
SIZE
D
R1921 100K 2 1
5% 1/20W MF 201
PM_SLP_S4_L 7 18 27 34 38 40 41 70 Apple Inc. REVISION
R1922 100K 2 1 PM_SLP_S5_L 18 41 70 R
4.18.0
R1923 100K 2 1
5%
5%
1/20W
1/20W
MF
MF
201
201
PM_SLP_SUS_L 18 70
NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1981 100K 2 1
5% 1/20W MF 201
LVDS_IG_BKL_ON 9 18 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
R1984 100K 2 1
5% 1/20W MF 201
LVDS_IG_PANEL_PWR 9 18 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
BG26
TP1 U1800 RSVD1 AY7
NC PANTHERPOINT NC
BJ26 AV7
NC TP2 MOBILE RSVD2 NC
BH25 AU3
NC TP3 FCBGA RSVD3 NC
BJ16
TP4 (5 OF 10) RSVD4 BG4
NC NC
BG16
NC TP5 AT10
AH38 RSVD5 NC
NC TP6 BC8
AH37 RSVD6 NC
NC TP7
AK43 AU2
NC TP8 RSVD7 NC
AK45 AT4
NC TP9 RSVD8 NC
C18 AT3
NC TP10 RSVD9 NC
D NC
N30
H3
TP11 RSVD10 AT1
AY3
NC D
NC TP12 RSVD11 NC
AH12 AT5
NC TP13 RSVD12 NC
AM4 AV3
NC TP14 RSVD13 NC
AM5 AV1
NC TP15 RSVD14 NC
Y13 BB1
NC TP16 RSVD15 NC
K24 BA3
NC TP17 RSVD16 NC
L24 BB5
NC TP18 RSVD17 NC
AB46 BB3
NC TP19 RSVD18 NC
AB45 BB7
NC TP20 RSVD19 NC
BE8
B21 RSVD20 NC
NC TP21 BD4
M20 RSVD21 NC
NC TP22 BF6
AY16 RSVD22 NC
TP_PCH_TP23 TP23
BG46 AV5
NC TP24 RSVD23 NC
AV10
RSVD24 NC
AT8
RSVD25 NC
AY5
RSVD26 NC
BA2
RSVD27 NC
AT12
RSVD28 NC
BF3
RSVD29 NC
USB3_EXTA_RX_N BE28 C24 USB_EXTA_N
91 40 IN USB3RN1 USBP0N BI 40 91
USB3_EXTC_RX_N BE32
91 9 IN USB3RN3 C25
BJ32 USBP1N USB_EXTB_XHCI_N BI 26 91
Ext B (XHCI)
C 91 40
9 IN USB3_EXTD_RX_N
USB3_EXTA_RX_P BC28
USB3RN4
USB3RP1
USBP1P B25 USB_EXTB_XHCI_P BI 26 91 C
IN C26 USB_EXTC_N
BE30 USBP2N BI 9 91
91 38 7 IN USB3_EXTB_RX_P USB3RP2 A26 USB_EXTC_P
Ext C (XHCI/EHCI)
BF32 USBP2P BI 9 91
91 9 IN USB3_EXTC_RX_P USB3RP3
USB3_EXTD_RX_P BG32 K28 USB_EXTD_XHCI_N
9 IN USB3RP4 USBP3N BI 26 91
H28 USB_EXTD_XHCI_P
Ext D (XHCI) (Mobiles: Trackpad?)
USB
USBP3P BI 26 91
USB3_EXTA_TX_N AV26
91 40 OUT USB3TN1 E28
BB26 USBP4N TP_USB_4N
91 38 OUT USB3_EXTB_TX_N USB3TN2 D28 TP_USB_4P
Unused
AU28 USBP4P
91 9 OUT USB3_EXTC_TX_N USB3TN3
USB3_EXTD_TX_N AY30 C28 TP_USB_SDN
9 OUT USB3TN4 USBP5N
A28 TP_USB_SDP
RSVD: SD
AU26 USBP5P
91 40 OUT USB3_EXTA_TX_P USB3TP1
USB3_EXTB_TX_P AY26 C29 TP_USB_WLANN
91 38 OUT USB3TP2 USBP6N
USB3_EXTC_TX_P AV28 B29 TP_USB_WLANP
RSVD: WiFi
91 9 OUT USB3TP3 USBP6P
USB3_EXTD_TX_P AW30
9 OUT USB3TP4 N28
USBP7N USB_HUB_UP_N BI 26 91
M28 USB_HUB_UP_P
USB Hub (All LS/FS Devices)
USBP7P BI 26 91
PCI
5% 1/20W MF 201
R2011 10K 1 2 PCI_INTB_L K38
PIRQB* G30
5% 1/20W MF 201 USBP9N USB_EXTB_EHCI_N BI 26 91
R2012 10K 1 2 PCI_INTC_L H38
PIRQC* E30 Ext B (EHCI)
5% 1/20W MF 201 USBP9P USB_EXTB_EHCI_P BI 26 91
R2013 10K 1 2 PCI_INTD_L G38
PIRQD*
5% 1/20W MF 201 C30
USBP10N USB_EXTD_EHCI_N BI 9
BLC_I2C_MUX_SEL C44
19 OUT REQ2*/GPIO52 L32
E40 USBP11N TP_USB_BT_HSN
19 OUT USE_HDD_OOB_L REQ3*/GPIO54 K32 TP_USB_BT_HSP
RSVD: BT (HS)
USBP11P
B TP_PCH_STRP_BBS1 D47
E42
GNT1*/GPIO51 USBP12N G32
E32
TP_USB_12N
Unused
B
NO STUFF TP_PCH_STRP_ESI_L GNT2*/GPIO53 USBP12P TP_USB_12P
R2054 10K 2 1 PCH_STRP_TOPBLK_SWP_L F46
GNT3*/GPIO55 C32
5% 1/20W MF 201 USBP13N TP_USB_13N
(IPU-PCIERST#) A32 TP_USB_13P
Unused
G42 USBP13P
19 IN BLC_GPIO PIRQE*/GPIO2 (IPD)
AUD_IP_PERIPHERAL_DET G40
59 19 IN PIRQF*/GPIO3 C33
C42 USBRBIAS* 91 PCH_USB_RBIAS
35 19 IN TBT_PWR_REQ_L PIRQG*/GPIO4 B33
D44 USBRBIAS PLACE_NEAR=U1800.B33:2.54mm
58 19 IN AUD_I2C_INT_L PIRQH*/GPIO5 1
R2070
TP_PCI_PME_L K10 A14 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 22.6
7 PME* (IPU) OC0*/GPIO59 IN 19 24
K20 1%
C6 OC1*/GPIO40 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 19 24 1/20W
27 25 OUT PLT_RESET_L PLTRST* B17 MF
OC2*/GPIO41 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24
2 201
LPC_CLK33M_SMC_R H49 C16 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
92 25 OUT CLKOUT_PCI0 OC3*/GPIO42 IN 19 24
A NO STUFF
5% 1/20W MF 201
R2062 10K 1 2
5% 1/20W MF 201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L 19 24
4.18.0
R2068 10K 1 2
5% 1/20W MF 201
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
NOTICE OF PROPRIETARY PROPERTY: BRANCH
19 24
5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
R2067 10K 2 1 AP_PWR_EN 24 34 70 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD
RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
D 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
D
OMIT_TABLE 201
2 2
201 201
2 2
201
(TBT_CIO_PLUG_EVENT_ISOL)
24 20 IN XDP_FC1_PCH_GPIO0 T7
BMBUSY*/GPIO0 U1800 TACH4/GPIO68 C40 9 MLB_RAMCFG3
PANTHERPOINT
FW_PME_L A42 MOBILE B41 MLB_RAMCFG2
20 IN TACH1/GPIO1 TACH5/GPIO69 9
FCBGA
DPMUX_UC_IRQ H36 C41 MLB_RAMCFG1
82 20 IN TACH2/GPIO6 (6 OF 10) TACH6/GPIO70 9
TP_PCH_GPIO8 C10
GPIO8 (IPU-RSMRST#)
WOL_EN C4
20 OUT LAN_PHY_PWR_CTRL/GPIO12
P4 PCH_A20GATE
G2 A20GATE 20
24 IN XDP_FC0_PCH_GPIO15 GPIO15 (IPU)
NO STUFF
24 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH U2
SATA4GP/GPIO16 (IPD) PECI AU16 PCH_PECI R2170 43 1 2 CPU_PECI BI 11 42 89
5% 1/20W
D40 MF 201
43 20 7 BI LPCPLUS_GPIO TACH0/GPIO17 P5
RCIN* PCH_RCIN_L 20
ODD_PWR_EN_L T5
20 OUT SCLOCK/GPIO22
=PP1V8_S0_PCH_VCC_DFTERM 8 21 23
PROCPWRGD AY11 PCH_PROCPWRGD R2140 0 1 2 CPU_PWRGD OUT 11 24 89
CPU/MISC
TBT_GO2SX_BIDIR E8
35 20 GPIO24 5% 1/20W
MF 201
1
41 20 SMC_WAKE_SCI_L E16
GPIO27 (IPU-DeepS4/S5) THRMTRIP* AY10 42 PM_THRMTRIP_L_R R2156 390 1 2 PM_THRMTRIP_L 11 42 89
R2179
IN IN
5% 1/20W 2.2K
P8 MF 201 5%
24 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L GPIO28 (IPU-RSMRST#) T14 1/20W
INIT3_3V* PCH_INIT3V3_L
GPIO
MF
(IPU) R2178 201
37 OUT TBT_SW_RESET_L R2180 0 1 2 20 TBT_SW_RESET_R_L K1
STP_PCI*/GPIO34 2
5% 1/20W AY1 1K
MF 201 K4 DF_TVS PCH_DF_TVS 2 1 CPU_PROC_SEL_L 11 89
24 OUT XDP_DC1_PCH_GPIO35_MXM_GOOD GPIO35 (IPD-PLTRST#?)
NO STUFF 5% DF_TVS:DMI & FDI Term Voltage
1/20W
V8 AH8
24 20 OUT XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL SATA2GP/GPIO36
(IPD-PLTRST#)
TS_VSS1 R2130 1 MF
201
Set to Vss when Low
AK11
C 24 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK M5
SATA3GP/GPIO37
(IPD-PLTRST#)
TS_VSS2
TS_VSS3 AH10 5%
1/20W
MF
1K This has internal pull up and should not pulled low.
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
Set to Vcc when High
C
JTAG_ISP_TDO N2 AK10
20 IN SLOAD/GPIO38 TS_VSS4 201
2
JTAG_ISP_TDI M3
20 OUT SDATAOUT0/GPIO39 P37
NC_1 NC
FW_PWR_EN_PCH V13
25 20 OUT SDATAOUT1/GPIO48
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH V3 BG2
24 OUT SATA5GP/GPIO49/TEMP_ALERT* VSS_NCTF_14
BG48
D6 VSS_NCTF_15
52 43 20 7 BI SPIROM_USE_MLB GPIO57 BH3
VSS_NCTF_16
BH47
VSS_NCTF_17
A4 BJ4
VSS_NCTF_0 VSS_NCTF_18
A44 BJ44
VSS_NCTF_1 VSS_NCTF_19
A45 BJ45
VSS_NCTF_2 VSS_NCTF_20
A46 BJ46
VSS_NCTF_3 VSS_NCTF_21
A5 BJ5
VSS_NCTF_4 VSS_NCTF_22
NCTF
A6 BJ6
VSS_NCTF_5 VSS_NCTF_23
B3 C2
VSS_NCTF_6 VSS_NCTF_24
B47 C48
VSS_NCTF_7 VSS_NCTF_25
BD1 D1
VSS_NCTF_8 VSS_NCTF_26
BD49 D49
VSS_NCTF_9 VSS_NCTF_27
BE1 E1
VSS_NCTF_10 VSS_NCTF_28
BE49 E49
VSS_NCTF_11 VSS_NCTF_29
BF1 F1
VSS_NCTF_12 VSS_NCTF_30
BF49 F49
VSS_NCTF_13 VSS_NCTF_31
B B
JTAG Isolation due to glitch in and out of sleep 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
NOTE: TCK from PCH is Push-Pull CMOS
NOTE: TMS/TDI from PCH is Open Drain 1 C2113
NOTE: TDO from CR is Push-Pull CMOS
0.1UF
10%
=PP3V3_S5_PCH_GPIO 8 CRITICAL CRITICAL 8 2
16V
X5R-CERM
0201
=PP3V3_SUS_PCH_GPIO 8 17 18 19 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO VCC
=PP3V3_TBT_PCH_GPIO 8 20
=PP3V3_S0_PCH_GPIO 8 17 18 19 20 25 37
Q2160 U2100
SOT833
1 1 TBT_PWR_EN goes high for JTAG Programming
R2188 SSM6N15AFE R2163 08
74LVC2G08GT
TBT_PWR_EN JTAG_TBT_TCK
G 2
10K 10K 35 25
1 7 35
5% SOT563 5%
IN A1 Y1 OUT
1/20W 1/20W 24 IN JTAG_ISP_TCK 2
B1
Stuff R2160 or R2574, not both MF MF
TBT_CIO_PLUG_EVENT 5 3 TBT_CIO_PLUG_EVENT_ISOL OUT 24
201 201 35
NO STUFF 2 2 IN A2 Y2
D
17 JTAG_ISP_TMS JTAG_TBT_TMS 35
6 Connects to PCH through
R2160 10K 1 2 XDP_FC1_PCH_GPIO0 IN OUT B2
6
20 24
R2185 10K 1 2
5% 1/20W MF 201
FW_PME_L 1 GND current limiting 1K resistor R2574
20 R2113 1
R2196 10K 1 2
5% 1/20W MF 201
SMC_RUNTIME_SCI_L 20 41 10K R2166 4
R2190 100K 1 2
5% 1/20W MF 201
LPCPLUS_GPIO
CRITICAL 5% 10K
7 20 43 1/20W 5%
5% 1/20W MF 201 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO MF 1/20W
=PP3V3_TBT_PCH_GPIO 8 20 201 2 MF
NO STUFF Must stuff R2197 when R2180 NO STUFFed. Q2160 2 201
R2197 10K 1 2 TBT_SW_RESET_R_L 20
1
R2199 SSM6N15AFE
1
R2161
5% 1/20W MF 201
R2184 10K
G 5
1
2
2
5%
5%
1/20W
1/20W
MF
MF
201
201
TBT_GO2SX_BIDIR
20
20 35
CRITICAL
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
R2193 100K 1 2 SPIROM_USE_MLB 7 20 43 52 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO Q2162 PAGE TITLE
R2191 10K 1 2
5% 1/20W MF 201
SMC_WAKE_SCI_L 20 41
1
SSM3K15FV
=PP3V3_TBT_PCH_GPIO
1
8 20
PCH GPIO/MISC/NCTF
5% 1/20W MF 201 R2186 SOD-VESM-HF R2162 DRAWING NUMBER SIZE
R2111 051-9589 D
G 1
R2198 10K 2 1 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL 20 24 20 OUT JTAG_ISP_TDO JTAG_TBT_TDO IN 35 NOTICE OF PROPRIETARY PROPERTY: BRANCH
3
5% 1/20W MF 201
2
D D
CRT
23
AF23 VCCCORE
VCCSUS3_3_7_USB T23 =PP3V3_SUS_PCH_VCCSUS_USB 8 23
BH23 AG21 VSSADAC U47
VCC CORE
VCCAPLLDMI2 pin left as NC per DG NC VCCAPLLDMI2 T24 VCCCORE
VCCSUS3_3_8_USB AG23
AL29 V23 VCCCORE
23 21 8 =PP1V05_S0_PCH_VCCIO_CLK VCCIO_14_PLLCLK VCCSUS3_3_9_USB AG24
V24 VCCCORE
AL24 VCCSUS3_3_10_USB AG26 CKPLUS_WAIVE=PwrTerm2Gnd
AL24 left as NC per DG NC DCPSUS_3_CLK P24 VCCCORE
VCCSUS3_3_6_USB AG27 VCCALVDS AK36 =LVDS_VCCA 8
AA19 VCCCORE
23 21 8 =PP1V05_S0_PCH_VCCASW VCCASW_1_CLK T26 AG29
AA21 VCCIO_34_PLLUSB =PP1V05_S0_PCH_VCCIO_PLLUSB 8 VCCCORE VSSALVDS AK37
VCCASW_2_CLK AJ23
AA24 VCCCORE
VCCASW_3_CLK V5REF_SUS M26 =PP5V_SUS_PCH_V5REFSUS 23
AJ26
USB
AA26 VCCCORE
VCCASW_4_CLK
LVDS
AA27 DCPSUS_4_USB AN23 NC NC-ed per DG AJ27 VCCCORE
VCCASW_5_CLK AJ29 PP1V8_S0_PCH_VCCTX_LVDS_F 23
AA29 VCCCORE
VCCASW_6_CLK VCCSUS3_3_1_USB AN24 =PP3V3_SUS_PCH_VCCSUS 8 23
AJ31 VCCTX_LVDS AM37
AA31 VCCCORE AM38
VCCASW_7_CLK VCCTX_LVDS
AC26 AP36
C AC27
VCCASW_8_CLK
VCCASW_9_CLK
V5REF P34 =PP5V_S0_PCH_V5REF 23
8 =PP1V05_S0_PCH_VCCIO_PLLPCIE AN19 VCCIO_28_PLLPCIE
VCCTX_LVDS
VCCTX_LVDS AP37 C
AC29 VCCASW_10_CLK VCCSUS3_3_2_GPIO N20 =PP3V3_SUS_PCH_VCCSUS_GPIO 8 23
TP_1V05_S0_PCH_VCCAPLLEXP BJ22 VCCAPLLEXP
CLK/MISC
AC31 VCCASW_11_CLK VCCSUS3_3_3_GPIO N22
AD29 P20 AN16 VCCIO_15_FDI =PP3V3_S0_PCH_VCC3_3_HVCMOS 8 23
VCCASW_12_CLK VCCSUS3_3_4_GPIO 23 8 =PP1V05_S0_PCH_VCCIO
VCC3_3_6_HVCMOS V33
HVCMOS
AD31 VCCASW_13_CLK VCCSUS3_3_5_GPIO P22 AN17 VCCIO_16_FDI
PCI/GPIO/
W21 VCCASW_14_CLK
W23 VCC3_3_1_GPIO AA16 =PP3V3_S0_PCH_VCC3_3_GPIO 8 23
AN21 VCCIO_17_PCIE VCC3_3_7_HVCMOS V34
VCCASW_15_CLK
LPC
VCC3_3_8_GPIO W16 AN26 VCCIO_18_PCIE
VCCIO
W24 VCCASW_16_CLK
W26 VCC3_3_4_GPIO T34 AN27 VCCIO_19_PCIE
VCCASW_17_CLK AP21
W29 VCCIO_20_PCIE
VCCASW_18_CLK AP23
W31 VCCIO_21_PCIE VCCVRM_3_DMI AT16 =PP1V8R1V5_S0_PCH_VCCVRM 8 21
VCCASW_19_CLK VCC3_3_2_SATA AJ2 =PP3V3_S0_PCH_VCC3_3_SATA 8 23
AP24
W33 VCCIO_22_PCIE
PCH output, for decoupling only VCCASW_20_CLK
DMI
VCCIO_5_PLLSATA AF13 =PP1V05_S0_PCH_VCCIO_SATA 8 17 21 23
AP26 VCCIO_23_PCIE VCCDMI_1_DMI AT20 =PP1V05_S0_PCH_VCC_DMI 8 23
PLACE_NEAR=U1800.N16:2.54mm N16 DCPRTC AT24
PPVOUT_G3_PCH_DCPRTC VCCIO_24_PCIE
MIN_LINE_WIDTH=0.2 mm VCCIO_12_SATA3 AH13
MIN_NECK_WIDTH=0.2 mm Y49 VCCVRM_4_CLK VCCCLKDMI AB36 PP1V05_S0_PCH_VCCCLKDMI_F 23
1 VOLTAGE=3.3V
=PP1V8R1V5_S0_PCH_VCCVRM VCCIO_13_SATA3 AH14 AN33 VCCIO_25_DP
C2210 21 8
AN34 VCCIO_26_DP
0.1UF 23 PP1V05_S0_PCH_VCCADPLLA_F BD47 VCCADPLLA VCCIO_6_PLLSATA3 AF14
20%
10V PP1V05_S0_PCH_VCCADPLLB_F BF47 VCCADPLLB =PP3V3_S0_PCH_VCC3_3_PCI BH29 VCC3_3_3_PCIE
CERM 2 23 23 8
VCCAPLLSATA AK1
SATA
DFT/SPI
8 17 21 23
55mA Max, 5mA Idle AF34 VCCDIFFCLKN VCCAFDIPLL pin left as NC per DG BG6 VCCAFDIPLL VCCDFTERM AJ16
FDI
VCCIO_3_SATA AC17 NC
AG34 VCCDIFFCLKN VCCDFTERM AJ17
VCCIO_4_SATA AD17 8 =PP1V05_S0_PCH_VCCIO_PLLFDI AP17 VCCIO_27_PLLFDI
23 8 =PP1V05_S0_PCH_VCCSSC AG33 VCCSSC
8 =PP1V05_S0_PCH_VCCDMI_FDI AU20 VCCDMI_2_FDI VCCSPI V1 =PP3V3_SUS_PCH_VCC_SPI 8 23
MIN_LINE_WIDTH=0.2 mm
B C2222 1
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
NC-ed per DG NC
T17 DCPSUS_1_CLK
V19 DCPSUS_2_CLK
VCCASW_23_MISC V21
VCCASW_21_MISC T19
B
0.1UF PLACE_NEAR=U1800.V16:2.54mm NC
20%
10V
CPU
=PP3V3R1V5_S0_PCH_VCCSUSHDA 8 23 25
A22 VCCRTC
RTC
A SYNC_MASTER=D2_CLEAN SYNC_DATE=03/19/2012 A
PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE
A G36 VSS
G48 VSS
VSS
VSS
AP1
BE16 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
H12 VSS BC16
H18 VSS
VSS
VSS BG28 PCH GROUNDS
H22 VSS BJ28 DRAWING NUMBER SIZE
VSS
H24 VSS Apple Inc. 051-9589 D
H26 VSS REVISION
R
H30 VSS 4.18.0
H32 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
NC
NC
1/16W 1/16W 10%
SOT-363 SOT-363 0.1UF 0.1UF 6.3V 2
MF-LF 3 MF-LF 6 10% 10% CERM
402 1 402 1 25V 25V 402
2 X5R 2 X5R
402 402 PLACE_NEAR=U1800.AG33:2.54mm
PP5V_SUS_PCH_V5REFSUS PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM <1 mA S0-S5 MIN_NECK_WIDTH=0.2 MM <1 mA PLACE_NEAR=U1800.T34:2.54mm
VOLTAGE=5V VOLTAGE=5V PLACE_NEAR=U1800.AA16:2.54mm
C2438 1 MAKE_BASE=TRUE C2439 1 MAKE_BASE=TRUE
0.1UF 1UF
D 20%
10V
CERM 2
=PP5V_SUS_PCH_V5REFSUS 21
10%
10V
X5R 2
=PP5V_S0_PCH_V5REF 21 21 17 8 =PP1V05_S0_PCH_VCCDIFFCLK D
402 402
PLACE_NEAR=U1800.M26:2.54mm PLACE_NEAR=U1800.P34:2.54mm 21 8 =PP3V3_S0_PCH_VCC3_3_HVCMOS C2434 1
1UF
10%
C2424 1 6.3V 2
CERM
0.1UF 402
10% PLACE_NEAR=U1800.AF34:2.54mm
16V
X7R-CERM 2
0402
PLACE_NEAR=U1800.V33:2.54mm
NO STUFF PP1V8_S0_PCH_VCCTX_LVDS_F 21
MIN_LINE_WIDTH=0.5 MM =PP1V05_S0_PCH_VCCIO_CLK
L2407 MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
21 8
=PP1V8_S0_PCH_VCCTX_LVDS 0.1UH
8
1 2 21 8 =PP3V3_S5_PCH_VCCDSW 21 8 =PP3V3_S0_PCH_VCC3_3_PCI C2469 1
1UF
0805 10%
NOSTUFF NO STUFF 1 C2499 1 C2421 1 6.3V 2
CERM
NO STUFF R2401 0.1UF 0.1UF 402
C2400 1 1 C2406 1 C2408 5%
0 20%
10V
10%
16V PLACE_NEAR=U1800.AF17:2.54mm
22UF 0.01UF 0.01UF CERM 2 X7R-CERM 2
20% 10% 10% 1/20W 402 0402
6.3V MF
X5R-CERM-1 2 2 16V
X7R-CERM 2 16V
X7R-CERM 2 201 PLACE_NEAR=U1800.T16:2.54mm PLACE_NEAR=U1800.BH29:2.54mm
603 0402 0402 PLACE_NEAR=U1800.AM37:2.54MM
PLACE_NEAR=U1800.AM37:2.54mm 21 17 8 =PP1V05_S0_PCH_VCCIO_SATA
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
21 8 =PP3V3_SUS_PCH_VCC_SPI 21 8 =PP3V3_S0_PCH_VCC3_3_SATA
C2444 1 C2452 1
PLACE_NEAR=U1800.U48:2.54mm
C2476 1 C2446 1
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm PCH VCCSUSHDA BYPASS 21 8 =PP1V05_S0_PCH_VCCASW
B CRITICAL PCH VCCADPLLA Filter
25 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
B
L2490 (PCH DPLLA PWR) C2441 1 C2420 1 C2428 1 1 C2426 1 C2456 1 C2496
8 =PP1V05_S0_PCH_VCCADPLL R2490 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLA_F 21
0.1UF
20%
22UF
20%
22UF
20%
1UF
10%
1UF
10%
1UF
10%
0 MIN_LINE_WIDTH=0.4 MM 10V 6.3V 6.3V 6.3V 6.3V 6.3V
1 2 PP1V05_S0_PCH_VCCADPLLA_R 1 2 MIN_NECK_WIDTH=0.2 MM 68 mA CERM 2 X5R-CERM-1 2 X5R-CERM-1 2 2 CERM 2 CERM 2 CERM
MIN_LINE_WIDTH=0.4 MM 0603
VOLTAGE=1.05V 402 603 603 402 402 402
5% MIN_NECK_WIDTH=0.2 MM
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.P32:2.54mm
MF-LF
402
CRITICAL NO STUFF PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
C2491 1 1 C2492 PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
220UF 1UF PLACE_NEAR=U1800.AC27:2.54mm
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20% 10% PCH VCCCORE BYPASS
2.5V 2 6.3V
2 CERM
TANT
B16 402 21 20 8 =PP1V8_S0_PCH_VCC_DFTERM (PCH 1.05V CORE PWR)
21 8 =PP1V05_S0_PCH_VCC_CORE
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM C2440 1
0.1UF
20%
CRITICAL PCH VCCADPLLB Filter 10V
CERM 2 C2460 1 1 C2481 1 C2482 1 C2483
L2491 (PCH DPLLB PWR) 402 10UF 1UF 1UF 1UF
20% 10% 10% 10%
R2491 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLB_F 21
PLACE_NEAR=U1800.AJ16:2.54mm 6.3V
X5R 2
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
0 MIN_LINE_WIDTH=0.4 MM 603 402 402 402
1 2 PP1V05_S0_PCH_VCCADPLLB_R 1 2 MIN_NECK_WIDTH=0.2 MM 69 mA
MIN_LINE_WIDTH=0.4 MM 0603 VOLTAGE=1.05V
5% MIN_NECK_WIDTH=0.2 MM PLACE_NEAR=U1800.AG26:2.54mm
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.AD21:2.54mm
MF-LF
402
CRITICAL NO STUFF =PP1V05_S0_PCH_V_PROC_IO PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
C2493 1 1 C2494 21 8
220UF 1UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20% 10%
2.5V 2 6.3V
2 CERM
TANT
B16 402 C2416 1 1 C2417 1 C2430
4.7UF 0.1UF 0.1UF
PLACE_NEAR=U1800.BF47:2.54MM 20% 10% 10%
PLACE_NEAR=U1800.BF47:2.54MM 6.3V 2 2 16V 2 16V
X5R X7R-CERM X7R-CERM
402 0402 0402
A CRITICAL
L2406
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
SYNC_MASTER=D2_CLEAN SYNC_DATE=03/19/2012 A
PAGE TITLE
=PP1V05_S0_PCH 10UH-0.58A-0.35OHM R2415 PP1V05_S0_PCH_VCCCLKDMI_F
17 8
1 2 PP1V05_S0_PCH_VCCCLKDMI_R 1
0 2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
21
PCH DECOUPLING
1098AS-SM MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.05V DRAWING NUMBER SIZE
MIN_NECK_WIDTH=0.25 MM 5%
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) VOLTAGE=1.05V 1/16W
MF-LF
21 8 =PP1V05_S0_PCH_VCC_DMI
Apple Inc. 051-9589 D
402 REVISION
R
C2419 1 4.18.0
C2411 1 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
10%
10UF 6.3V
20% CERM 2 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
6.3V 402
X5R 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE_NEAR=U1800.AT20:2.54mm
PLACE_NEAR=U1800.AB36:2.54mm
603 PCH VCCIO BYPASS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
24 OF 132
PCH VCC3_3 BYPASS
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
(PCH PCI 3.3V PWR)
IV ALL RIGHTS RESERVED 23 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
24 8 =PPVCCIO_S0_XDP CPU Micro2-XDP 24 8 =PPVCCIO_S0_XDP
CRITICAL NOTE: This is not the standard XDP pinout. XDP PLACE_NEAR=J2500.52:2.54mm
XDP_CONN Use with 921-0133 Adapter Flex to 89 24 11 XDP_CPU_TDO R2510 51 2 1
5% 1/20W MF 201
=PP3V3_S0_XDP J2500 support chipset debug.
8 XDP PLACE_NEAR=U1000.K61:2.54mm
DF40RC-60DP-0.4V
NO STUFF M-ST-SM 89 24 11 XDP_CPU_TDI R2511 51 2 1
1 5% 1/20W MF 201
R2540 62 61 XDP PLACE_NEAR=U1000.H59:2.54mm
1K
5% 89 24 11 XDP_CPU_TMS R2512 51 2 1
1/16W 5% 1/20W MF 201
MF-LF
402 2 1 XDP PLACE_NEAR=U1000.J58:2.54mm
2
89 11 XDP_CPU_PREQ_L OBSFN_A0 4 3
OBSFN_C0 CPU_CFG<16> 10 89 89 24 11 XDP_CPU_TCK R2513 51 2 1
D 89 11
BI
IN XDP_CPU_PRDY_L OBSFN_A1 6
8
5
7
OBSFN_C1 CPU_CFG<17>
IN
IN 10 89
XDP
5% 1/20W MF
PLACE_NEAR=U1000.H63:2.54mm
201
D
89 24 11 XDP_CPU_TRST_L R2514 51 2 1
(R2560-R2563) 89 11 IN XDP_BPM_L<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> IN 10 24 89 5% 1/20W MF 201
12 11
XDP_CPU:BPM 89 11 IN XDP_BPM_L<1> OBSDATA_A1 OBSDATA_C1 CPU_CFG<1> IN 10 89
89 11 IN XDP_BPM_L<4> R2560 0 1 2 14 13
5% 1/20W MF 201
89 11 IN XDP_BPM_L<5> R2561 0 1 2 89 11 IN XDP_BPM_L<2> OBSDATA_A2 16 15
OBSDATA_C2 CPU_CFG<2> IN 10 89
5% 1/20W MF 201
89 11 IN XDP_BPM_L<6> R2562 0 1 2 89 11 IN XDP_BPM_L<3> OBSDATA_A3 18 17
OBSDATA_C3 CPU_CFG<3> IN 10 89
5% 1/20W MF 201
89 11 IN XDP_BPM_L<7> R2563 0 1 2 20 19
5% 1/20W MF 201
89 10 IN CPU_CFG<10> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<8> IN 10 89
60
57
59 XDP_PRESENT#
XDP_CPU_TMS OUT 11 24 89
C
(R2520-R2537) XDP XDP
XDP SIGNALS XDP PCH SIGNALS C2500 1
64 63
1 C2501
PCH SIGNALS Non-XDP Signals
0.1UF 0.1UF
24 OUT XDP_DA0_USB_EXTA_OC_L R2520 33 1 2 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L IN 19 24
10%
16V
10%
16V
5% 1/20W MF 201 2 2
24 OUT XDP_DA1_USB_EXTB_OC_L R2521 33 1 2
5% 1/20W MF 201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 19 24
X7R-CERM
0402 998-2516 X7R-CERM
0402
24 OUT XDP_DA2_USB_EXTC_OC_L R2522 33 1 2 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24 19 OUT XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L R2590 0 1 2 USB_EXTA_OC_L IN 40
5% 1/20W MF 201 5% 1/20W MF 201
24 OUT XDP_DA3_USB_EXTD_OC_L R2523 33 1 2 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L IN 19 24 19 OUT XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2591 0 1 2 USB_EXTB_OC_L IN 7 38
5% 1/20W MF 201 5% 1/20W MF 201
24 19 IN XDP_DB2_PCH_GPIO10_AP_PWR_EN R2596 0 1 2 AP_PWR_EN OUT 19 34 70
5% 1/20W MF 201
24 OUT XDP_DB0_USB_EXTB_OC_EHCI_L R2524 33 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L IN 19 24 19 OUT XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE R2597 0 1 2 SDCONN_STATE_CHANGE IN 25
5% 1/20W MF 201 5% 1/20W MF 201
24 OUT XDP_DB1_USB_EXTD_OC_EHCI_L R2525 33 1 2 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L IN 19
5% 1/20W MF 201 NOTE: This is not the standard XDP pinout. 24 17 IN XDP_DC3_PCH_GPIO19_SATARDRVR_EN R2573 0 1 2 SATARDRVR_EN OUT 17
24 IN XDP_DB2_AP_PWR_EN R2526 33 1 2 XDP_DB2_PCH_GPIO10_AP_PWR_EN OUT 19 24 5% 1/20W MF 201
XDP_DB3_SDCONN_STATE_CHANGE R2527 33 1 2
5% 1/20W MF 201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
Use with 921-0133 Adapter Flex to
24 OUT IN 19 24
5% 1/20W MF 201 support chipset debug. 24 20 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L R2570 0 1 2 ISOLATE_CPU_MEM_L OUT 27
24 OUT XDP_FC0 R2528 33 1 2 XDP_FC0_PCH_GPIO15 IN 20 5% 1/20W MF 201
5% 1/20W MF 201
24 17 IN XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL R2572 0 1 2 DP_AUXCH_ISOL OUT 17 25
5% 1/20W MF 201
XDP_FC1 R2529 33 1 2 XDP_FC1_PCH_GPIO0
24 OUT
5% 1/20W MF 201
IN 20 24
24 20 OUT XDP_FC1_PCH_GPIO0 R2574 1K 1 2
5% 1/20W MF 201
TBT_CIO_PLUG_EVENT_ISOL IN 20
24 IN XDP_DC1_MXM_GOOD R2531 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT 20 PCH Micro2-XDP =PP3V3_S5_XDP 8
24 XDP_DB2_AP_PWR_EN OBSDATA_B2 34 33
OBSDATA_D2 XDP_DD2_AUD_IPHS_SWITCH_EN 24 XDP PLACE_NEAR=U1800.H7:2.54mm
24 XDP_DB3_SDCONN_STATE_CHANGE OBSDATA_B3 36 35
OBSDATA_D3 XDP_DD3_ENET_LOW_PWR 24 24 17 XDP_PCH_TMS R2552 51 2 1
38 37 5% 1/20W MF 201
XDP
XDP PLACE_NEAR=U1800.J3:2.54mm
70 41 IN ALL_SYS_PWRGD R2584 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 TP_XDP_PCH_HOOK4
PLACE_NEAR=J2550.39:2.54mm 5% 1/20W MF 201 24 17 XDP_PCH_TCK R2556 51 2 1
XDP_PCH_PWRBTN_L HOOK1 42 41
ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5 5% 1/20W MF 201
XDP
PM_PWRBTN_L R2585 0 1 2
VCC_OBS_AB 44 43
VCC_OBS_CD
41 24 18 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 TP_XDPPCH_HOOK2 HOOK2 46 45
RESET#/HOOK6 XDPPCH_PLTRST_L IN 25 1K series R on PCH Support Page
TP_XDPPCH_HOOK3 HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L OUT 11 24 25 89
50 49
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 44 24
44 24
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 17 24
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
IN PAGE TITLE
24 17 OUT XDP_PCH_TCK
TCK1
TCK0
NC
56
58
55
57
TDI
TMS
XDP_PCH_TDI
XDP_PCH_TMS
OUT 17 24
OUT 17 24
CPU & PCH XDP
DRAWING NUMBER SIZE
60 59 XDP_PRESENT#
XDP XDP Apple Inc. 051-9589 D
REVISION
C2580 1 1
C2581 R
0.1UF
64 63
0.1UF 4.18.0
10% 10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
16V 16V
2 2
X7R-CERM
0402 998-2516 X7R-CERM
0402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
25 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 24 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPIO Glitch Prevention PCH Reset Button Platform Reset Connections
25 19 8 =PP3V3_S3_PCH_GPIO
70 8 =PP3V3_S0_SB_PM
CRITICAL 8 1 C2650 Unbuffered R2681 LPC_RESET_L
0.1UF 33 OUT 92
VCC 20% 1
R2695 27 19 IN PLT_RESET_L 1 2 LPCPLUS_RESET_L OUT 7 43
U2650
SOT833
10V
2 CERM
4.7K
MAKE_BASE=TRUE
5%
MAKE_BASE=TRUE
402
08 XDP
5%
1/16W
1/16W
MF-LF R2683
74LVC2G08GT
24 20 9 IN ENET_LOW_PWR_PCH 1
A1 Y1
7 ENET_LOW_PWR OUT 9 MF-LF 402 33
R2696 2 402
1 2 SMC_LRESET_L OUT 41
70 25 18 IN PM_PCH_PWROK 2
B1
FW_PWR_EN_PCH 5 3 FW_PWR_EN XDP_DBRESET_L 1
0 2 PM_SYSRST_L
5%
20 9 89 24 11 18 41 1/16W
IN A2 Y2 OUT IN OUT
6
B2 5% OMIT R2671 MF-LF
402
D GND
1/16W
MF-LF
402
1
R2697 1
0 2 PCA9557D_RESET_L OUT 33 D
4 0 5%
1/16W
XDP
5%
1/16W
MF-LF
MF-LF
402 R2689
2 402
1K
1 2 XDPPCH_PLTRST_L OUT 24
SILK_PART=SYS RESET 5%
1/16W
25 19 8 =PP3V3_S3_PCH_GPIO R2687 MF-LF
402
0
1 2 DPMUX_LRESET_L
CRITICAL 8 1 C2652 SDCONN_STATE_CHANGE ISOLATION 5%
OUT 82
0.1UF 1/16W
VCC 20% =PP3V3_S3_SDBUF 8 MF-LF
U2652
SOT833
10V
2 CERM =PP3V3_S4_SMC 8 25 42 402
402 1
C2630
08 24 SDCONN_STATE_CHANGE
74LVC2G08GT
TBT_PWR_EN_PCH 1 7 TBT_PWR_EN OUT 0.1UF 1
17 IN A1 Y1 OUT 20 35
10% R2641
43 41 18 7 IN LPC_PWRDWN_L 2
B1 CRITICAL 2
6.3V
X5R 470K
5%
25 8 =PP3V3_S0_RSTBUF Buffered R2685
0
24 20 IN AUD_IPHS_SWITCH_EN_PCH 5
A2 Y2
3 AUD_IPHS_SWITCH_EN OUT 58
TC7SZ08AFEAPE
SOT665
201
1/20W 1 2 SSD_RESET_L OUT 39
MF
70 25 18 IN PM_PCH_PWROK 6
B2
5
201 2 5%
A
2
CRITICAL 1/16W
MF-LF
GND 4
Y
5 MC74VHC1G08 R2686 402
4
U2630 1 SC70-HF =ENET_RESET_L OUT 38
B
1 SDCONN_STATE_CHANGE_RIO IN 7 38 0
U2680 4 PLT_RST_BUF_L 1 2 ENET_RESET_L 7
3 2 MAKE_BASE=TRUE MAKE_BASE=TRUE
5%
42 25 8 =PP3V3_S4_SMC 1
1/16W
3 R2680 MF-LF
402
R2640 1
Q2640 C2680 1 5%
100K =TBT_RESET_L OUT 37
G 2
1/20W SOT563 CERM 2 2 402
MF 402 0
201 2 1 2 AP_RESET_L OUT 34
Q2640 5%
SSM6N15FEAPE 1/16W
R2693
S
G 5
SDCONN_STATE_CHANGE_INV MF-LF
0
C 402
C
6
SOT563
1
1 2 BKLT_PLT_RST_L OUT 86
5%
1/16W
S
42 OUT SDCONN_STATE_CHANGE_SMC MF-LF
402
4
25 8 =PP3V3_S0_RSTBUF Buffered CPU reset
CRITICAL
LPC 33MHz Clock R2655
Series Termination DP_AUXIO_EN INVERSION
R2630
10K
5 U2690
74LVC1G07
SC70
PLACE_NEAR=U1800.N52 37 20 19 18 17 8 =PP3V3_S0_PCH_GPIO 1 2
22 2 4 PLT_RST_CPU_BUF_L CPU_RESET_L OUT 11 24
92 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 41 92 5% DP_AUXIO_EN OUT 84 85 MAKE_BASE=TRUE
1/20W
5% MF NC VTT pullup on CPU page
1
1/20W
MF
R2656
201
D 3 1 3 R2690
PLACE_NEAR=U1800.P53 1
201
22 C2639 1
C2690 1 5%
100K
19 IN LPC_CLK33M_LPCPLUS_R 2 LPC_CLK33M_LPCPLUS OUT 7 43 92
Q2630 0.1UF NC 1/16W
SOD-VESM-HF 0.1UF 20% MF-LF
5% 10% 10V
1/20W
SSM3K15FV 16V CERM 2 2 402
X5R-CERM 2 402
PLACE_NEAR=U1800.P46 R2657 MF
201 1 G S 2 0201
LPC_CLK33M_DPMUX_UC_R 1
22 2 LPC_CLK33M_DPMUX_UC DP_AUXCH_ISOL
OUT 82 24 17 IN
MAKE_BASE=TRUE
5%
TP_PCI_CLK33M_OUT2 1/20W 1 NO STUFF
19 IN R2631
MF
201 R2659 10K
PLACE_NEAR=U1800.P48 1 22 5%
19 IN PCH_CLK33M_PCIOUT 2 PCH_CLK33M_PCIIN OUT 17 92 1/20W
MF
5%
1/20W 2 201
MF
201
B System RTC Power Source & 32kHz / 25MHz Clock Generator PCH ME Disable Strap B
=PPVBAT_G3_SYSCLK PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
8
VDDIO_25M_A: SB power rail for XTAL circuit. If high, ME is disabled. This allows for full re-flashing of SPI ROM.
Coin-Cell: VBAT (300-ohm & 10uF RC)
VDDIO_25M_B: Ethernet power rail for XTAL circuit. SMC controls strap enable to allow in-field control of strap setting.
No Coin-Cell: 3.42V G3Hot (no RC)
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
8 =PP3V3_S5_SYSCLK
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered. 23 8 =PP5V_S0_PCH
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5 1
No Coin-Cell: 3.3V S5 R2620
100K
GreenClk 25MHz Power 8 =PP3V3_S0_SYSCLK No bypass necessary 5%
1/20W
Q2620 MF
NO STUFF SSM6N37FEAPE 2 201
SPI_DESCRIPTOR_OVERRIDE_LS5V
G 5
R2607 SOT563
0
1 2 SYSCLK_25M_B_GND
MIN_LINE_WIDTH=0.3MM 23 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
Ethernet XTAL Power (Unused on 15" MBP) 5% MIN_NECK_WIDTH=0.2MM
4 S
1/16W VOLTAGE=0V SPI_DESCRIPTOR_OVERRIDE
+3.42V 13
+V3.3A 2
3
8
402
TBT XTAL Power 8 =PPVDDIO_TBT_CLK 1
VBAT and +V3.3A are R2621
internally ORed to Q2620 D 6 1K
5%
NO STUFF create VDD_RTC_OUT. SSM6N37FEAPE 1/20W
1
C2624 1 C2622 1 C2620 1 R2608 C2602 1
SOT563 MF
2 201
0.1UF 0.1UF 0.1UF 5%
0 1UF U2600 +V3.3A should be first
20%
10V
20%
10V
20%
10V 1/16W 10%
10V 2 SLG3NB148A available ~3.3V power HDA_SDOUT_R OUT 17 92
CERM 2 CERM 2 CERM 2 MF-LF X5R TQFN 2 G S 1
402 402 402 2 402 402-1 to reduce VBAT draw. IPD = 9-50k
CRITICAL SPI_DESCRIPTOR_OVERRIDE_L
42 41 IN
11 VDDIO_25M_A 32KHZ_A 12 SYSCLK_CLK32K_RTC 17 91
OUT
6 CKPLUS_WAIVE=PwrTerm2Gnd
A C2605 14
VDDIO_25M_B
VDDIO_25M_C 25MHZ_A 9 SYSCLK_CLK25M_SB OUT 17 91 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
12PF R2605 25MHZ_B 8 TP_SYSCLK_CLK25M_ENET PAGE TITLE
0
2 1 SYSCLK_CLK25M_X2 1 2 SYSCLK_CLK25M_X2_R 3
4
X2 25MHZ_C 15 SYSCLK_CLK25M_TBT OUT 35 91 Chipset Support
5%
5% NO STUFF X1 =PPVRTC_G3_OUT 8 DRAWING NUMBER SIZE
CRITICAL 1/16W
50V MF-LF 1
R2606 VDD_RTC_OUT 1 For SB RTC Power 051-9589 D
1
C0G-CERM
0402 NC Y2605 402
1M
Apple Inc. REVISION
4 2
5% GND THRM
NC SM-3.2X2.5MM 1/16W PAD 1 C2610 R
4.18.0
C2606 25.000MHZ-12PF-20PPM
10
16
17
MF-LF
3
HUB_ALLREM HUB_NONREM1_0,HUB_NONREM0_0
TABLE_BOMGROUP_ITEM
HUB_1NONREM HUB_NONREM1_0,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0
USB MUX FOR LS/FS INTERNAL DEVICES HUB_3NONREM HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
D 26 8 =PP3V3_S3_USB_HUB
BYPASS=U27000.5::5MM 0
0
1
1
:
:
:
:
0
1
0
1
ALL PORTS ARE REMOVABLE
PORT 1 IS NON REMOVABLE
PORT 1&2 ARE NON REMOVABLE
PORT 1&2&3 ARE NON REMOVABLE
D
C2700 1
C2701 1 1
C2702 1
C2703 CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
4.7UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10%
6.3V 16V 16V 16V
X5R 2 X7R-CERM 2 2 X7R-CERM 2 X7R-CERM
603 0402 0402 0402
BOM TABLE TABLE_5_HEAD
10
15
23
29
36
14
34
16V 16V
CRITICAL VOLTAGE=1.8V
5
2 X7R-CERM 2 X5R
Y2700 BYPASS=U2700.5::2MM 1
C2711 1
C2712 0402 402
0.1UF 1UF
CRFILT
PLLFILT
SM-2 BYPASS=U2650.23::2MM VDD33 10% 10%
24.000MHZ-16PF 16V 16V
2 X7R-CERM 2 X5R
1 3
0402 402
C2709 1 1
C2710 NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
18PF 18PF USB2513B 1 1 1 1 1 1
5% 5% R2701 QFN
R2716 R2717 R2718 R2719 R2722 R2723
50V
2
R2700 2
50V
100 10K 10K 10K 10K 10K 10K
C0G-CERM C0G-CERM USB_HUB_TEST 11 1 USBHUB_DN1_N
HUB_NONREM1_1 HUB_NONREM0_1 0402
1M 0402
1 2 TEST USBDM_DN1/PRT_DIS_M1 BI 9 5% 5% 5% 5% 5% 5%
1 2
OMIT 2
BLUETOOTH FOR 15" MBP & MBP OG 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
5% USBDP_DN1/PRT_DIS_P1 USBHUB_DN1_P BI 9 MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
1 1 5% 1/16W USB_HUB_RESET_L 26 RESET*
R2702 R2703
C 10K
5%
10K
5%
1/16W
MF-LF
402
MF-LF
402
26
USB_HUB_XTAL1 33 XTALIN/CLKIN
USBDM_DN2/PRT_DIS_M2 3
4
USBHUB_DN2_N 9 26
TRACKPAD/KEYBOARD FOR 15" MBP & MBP OG
2
402
2 402
2 402
2 402
2 402
2 402
C
1/16W 1/16W CRITICAL 32
USBDP_DN2/PRT_DIS_P2 USBHUB_DN2_P 9 26
MF-LF MF-LF USB_HUB_XTAL2 XTALOUT 26 9 USBHUB_DN3_N
402 402
2 2
USBDM_DN3/PRT_DIS_M3 6 USBHUB_DN3_N USBHUB_DN3_P
BI 9 26 26 9
USB_HUB_NONREM0 28
SUSP_IND/LOCAL_PWR/NON_REM0 7
SMC DEBUG PORT FOR 15" MBP, IR for MBP OG
USBDP_DN3/PRT_DIS_P3 USBHUB_DN3_P BI 9 26
USB_HUB_NONREM1 22 USBHUB_DN4_N
SDA/SMBDATA/NON_REM1 8
26 9
NC USBHUB_DN4_N BI 9 26
NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG 26 9 USBHUB_DN4_P
USB_HUB_CFG_SEL0 24 9 USBHUB_DN4_P
HUB_NONREM1_0 HUB_NONREM0_0 SCL/SMBCLK/CFG_SEL0 NC BI 9 26
25 12
R2704 1
1 USB_HUB_CFG_SEL1 TP_USB_HUB_PRTPWR1 USBHUB_DN2_N
R2705 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 26 9
37
R2720
27
91 19 BI USB_EXTD_XHCI_N 1 2 USB_TPAD_R_N BI 49 96
B 1 TO PCH XHCI
NOSTUFF
R2721
5%
1/16W
MF-LF
TO TP/KB B
R2712 27 402
10K 91 19 BI USB_EXTD_XHCI_P 1 2 USB_TPAD_R_P BI 49 96
5%
1/16W 5%
MF-LF 1/16W
MF-LF
2 402 402
USB_HUB_RESET_L 26
C2715 1
0.1UF
10%
16V
X7R-CERM 2
0402
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
8 =PP3V3_S3_USBMUX
C2760 1
9
0.1UF
20%
10V VCC
CERM 2
19 USB_EXTB_EHCI_P 402 5 M+ Y+ 1 USB_EXTB_P 7 38 91
BI BI
PCH PORT 9 (EHCI2) 91
USB_EXTB_EHCI_N 4 M- Y- 2 USB_EXTB_N
TO CONNECTOR
91 19 BI U2760 BI 7 38 91
A 19 BI USB_EXTB_XHCI_P 7 D+
PI3USB102ZLE
TQFN SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PCH PORT 1 (XHCI) 91
USB_EXTB_XHCI_N 6 D- CRITICAL PAGE TITLE
91 19 BI
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE USB HUB & MUX
8 OE* SEL 10 USB_EXTB_SEL_XHCI 17
DRAWING NUMBER SIZE
IN
PCH GPIO60 051-9589 D
GND SEL=0 CHOOSE USB EHCI2 PORT Apple Inc. REVISION
SEL=1 CHOOSE USB XHCI PORT
3
R
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
27 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 26 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
10K 1
R2822
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
P1V5CPU_EN 2 402 D Q2820
CRITICAL OUT 69
R28201
27.4K DMB53D0UV
8 =PP3V3_S3_MEMRESET CPUMEM_S0 1% SOT-563
1/16W
CPUMEM_S0 Q2805 D 6 MF-LF
402 2
PM_MEM_PWRGD_L 2 G
R28011 SSM6N15FEAPE
SOT563
100K
5% 3 CRITICAL
1/16W
MF-LF
402 2 2 G S 1 P1V5_S0_DIV 5 Q2820 S
DMB53D0UV 1
P1V5CPU_EN_L SOT-563
CRITICAL CRITICAL OMIT_TABLE 4
CPUMEM_S0
D 3 3 D
CPUMEM_S0 R28211 C2820 1
Q2800 Q2805 33.2K
1% 4700PF
SSM6N15FEAPE SSM6N15FEAPE 10%
C SOT563 SOT563
1/16W
MF-LF
402 2
100V
CERM 2
402
C
5 G S 4 G 5
4 S
24 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 7 18 38 41 70
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN OUT 9
=PP5V_S3_MEMRESET
27 8
CPUMEM_S0 CPUMEM_S0
CRITICAL
CPUMEM_S0
Q2810 D 6
MEMVTT Clamp
1 1 SSM6N15FEAPE Ensures CKE signals are held low in S3
R2815 R2802 SOT563
100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2 2 G S 1 8 =PPVTT_S0_VTTCLAMP
MEMVTT_EN_L CPUMEM_S0
CRITICAL
CRITICAL CRITICAL R28501
CPUMEM_S0 CPUMEM_S0 10 75mA max load @ 0.75V
CPUMEM_S0 D 6 3 D 5%
Q2815 Q2800 Q2810 1/10W
MF-LF
60mW max power
SSM6N15FEAPE SSM6N15FEAPE 603 2
SSM6N15FEAPE SOT563 SOT563
VTTCLAMP_L
G 2
SOT563 CRITICAL
2 G S 1 4 S G 5 27 8 =PP5V_S3_MEMRESET CPUMEM_S0
Q2850 D 6
B CPUMEM_S0 B
6 D
1 S
PLT_RESET_L IN 19 25
SSM6N15FEAPE
R28511 SOT563
100K
5%
NOSTUFF 1/16W
MF-LF
C2817 1 CRITICAL
402 2 2 G S 1
0.047UF =PP1V5_S3_MEMRESET 8
10%
6.3V CPUMEM_S0 CRITICAL VTTCLAMP_EN
X5R 2 CPUMEM_S0
201 Q2815 1 CPUMEM_S0
SSM6N15FEAPE R2816 1 C2816 CPUMEM_S0
NO STUFF
MEMRESET_ISOL_LS5V_L
1K 0.1UF Q2850 D 3
C2851 1
5
3 D
64 9 IN =DDRVTT_EN
CPUMEM_S3
R2817
1
0 2
5%
1/16W
MF-LF
402
to 5
6
0
0
1
1
1
1
1
1
0 (*)
1
1
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
Apple Inc. 051-9589 D
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 28 OF 132
II NOT TO REPRODUCE OR COPY IT
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 27 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A
89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29
C2907 1
C2917 1 C2927 1 C2937 1
0.47UF C2908 1 1 C2909 C2918 1 1 C2919 C2928 1 1 C2929 C2938 1 1 C2939
20% 0.47UF 0.47UF 0.47UF
4V 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
CERM-X5R-1 2
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
201 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90 32
28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC
D
29
90
28 12
32 29
MEM_A_A<1> L8
L4
A1 U2900
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2910
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2920
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2930
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
90 32
MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<0> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<14> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<22> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<31>
28 12
29 90
A3 (SYM VER 2) DQ0 12 29
90
A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 90
90 90
32 29
28 12 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<6> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<9> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<21> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<24> 12 29 90
90 90 90
90
28
32
12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<7> 28 12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<10> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<16> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<27> 12 29 90
29 90 32 29 90 90
28
90
12 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<5> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<15> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<17> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<28> 12 29 90
32 29 90 90 90
MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<3> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<11> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<18> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<30> 12 29 90
90 90 90
90 32
28 12 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<1> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<13> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<23> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<25> 12 29 90
29 90 90 90
90
28 12 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<2> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<8> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<20> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<26> 12 29 90
32 29 90 90 90
28 12 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<4> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<12> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<19> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<29> 12 29 90
32 29 90 90 90
32
28 12
90 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11
29
K8 DQS C4 MEM_A_DQS_P<0> 12 29 K8 DQS C4 MEM_A_DQS_P<1> 12 29 K8 DQS C4 MEM_A_DQS_P<2> 12 29 K8 DQS C4 MEM_A_DQS_P<3> 12 29
9090 32
28 12 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
29
N4 DQS* D4 MEM_A_DQS_N<0> 12 29 N4 DQS* D4 MEM_A_DQS_N<1> 12 29 N4 DQS* D4 MEM_A_DQS_N<2> 12 29 N4 DQS* D4 MEM_A_DQS_N<3> 12 29
90
28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
32 29 90 32 29 28 90 32 29 28 90 32 29 28
28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8
32 29
90 90 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28 12
32 29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
28 12 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 32 90
32 29 32 90 32 90 32 90
28 12 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 32 90
32 29 32 90 32 90 32 90
90
28 12
90 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
32 29 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90
90
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 32
12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 32 90
32 29 90 32 90 32 90
MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS*
A1 A1 A1 A1
90
28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC
32 29 A4 A4 A4 A4
NC NC NC NC
28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_A_ZQ<0> H9 ZQ NC MEM_A_ZQ<1> H9 ZQ NC MEM_A_ZQ<2> H9 ZQ NC MEM_A_ZQ<3> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
C R2900 R2910 R2920 R2930 C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C2947 1
C2948 1 1 C2949 C2957 1
C2958 1 1 C2959 C2967 1 C2968 1 1 C2969 C2977 1 C2978 1 1 C2979
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC
N11 N11 N11 N11
32 29
MEM_A_A<1> L8 A1 U2940 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U2950 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U2960 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U2970 NC
N3 MEM_RESET_L
L4 DDR3-1333 RESET* 90 27 28 29
L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 27 28 29 30 31
90
28 12 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
32 29
MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<32> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<40> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<48> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<56>
28 12 A3 DQ0 12 29 A3 DQ0 12 29 A3 DQ0 12 29 A3 DQ0 12 29 90
32 29
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8
90
28 12
32 29
90 MEM_A_A<4> A4 DQ1 MEM_A_DQ<33> 12 29
90
MEM_A_A<4> A4 DQ1 MEM_A_DQ<41> 12 29 MEM_A_A<4> A4 DQ1 MEM_A_DQ<49> 12 29 MEM_A_A<4> A4 DQ1 MEM_A_DQ<57> 12 29 90
90 90
90
28 12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<34> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<42> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<50> 28 12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<58> 12 29 90
32 29 90 90 90 32 29
MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<35> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<43> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<51> 28 12 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<59> 12 29 90
90 90 90 32 29
90
28 12 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<36> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<44> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<52> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<60> 12 29 90
32 29 90 90 90
28 12 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<37> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<45> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<53> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<61> 12 29 90
32 29 90 90 90
M4 D3 M4 D3 M4 D3 M4 D3
B 90
28 12
32 29
90
90
28 12
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<38>
MEM_A_DQ<39>
12 29
90
12 29
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<46>
MEM_A_DQ<47>
12 29
90
12 29
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<54>
MEM_A_DQ<55>
12 29
90
12 29
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<62>
MEM_A_DQ<63>
12 29 90
12 29 90
B
32 29 90 90 90
MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11
K8 DQS C4 MEM_A_DQS_P<4> 12 29 K8 DQS C4 MEM_A_DQS_P<5> 12 29 K8 DQS C4 MEM_A_DQS_P<6> 12 29 K8 DQS C4 MEM_A_DQS_P<7> 12 29
90 32
28 12 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
29 90
N4 DQS* D4 MEM_A_DQS_N<4> 12 29
N4 DQS* D4 MEM_A_DQS_N<5> 12 29 N4 DQS* D4 MEM_A_DQS_N<6> 12 29 N4 DQS* D4 MEM_A_DQS_N<7> 12 29
32 29
28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
90 32 29 28 90 32 29 28 90 32 29 28
90 32
28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8
29
90
MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28 12
32 29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
32 29
28 12 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 32 90
32 90 32 90 32 90
90
28
32
12 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 32 90
29 32 90 32 90 32 90
28
90
12 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
32 29 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90
90
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 32 90
32 29 32 90 32 90 32 90
MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS*
A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
90
28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC
32 29 A4 A4 A4 A4
NC NC NC NC
28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_A_ZQ<4> H9 ZQ NC MEM_A_ZQ<5> H9 ZQ NC MEM_A_ZQ<6> H9 ZQ NC MEM_A_ZQ<7> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
R2940 R2950 R2960 R2970
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3007 1
C3008 1 1 C3009 C3017 1
C3018 1 1 C3019 C3027 1 C3028 1 1 C3029 C3037 1 C3038 1 1 C3039
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC
D
32 29
MEM_A_A<1> L8
L4
A1 U3000
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3010
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3020
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3030
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
90
28 12 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
32 29
MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<6> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<9> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<21> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<24>
28 12 A3 (SYM VER 2) DQ0 12 28 A3 (SYM VER 2) DQ0 12 28 A3 (SYM VER 2) DQ0 12 28 A3 (SYM VER 2) DQ0 12 28 90
32 29 90 90 90
90
28 12
90 MEM_A_A<3> L9 A4 DQ1 C8 MEM_A_DQ<0> 12 28 MEM_A_A<3> L9 A4 DQ1 C8 MEM_A_DQ<14> 12 28 MEM_A_A<3> L9 A4 DQ1 C8 MEM_A_DQ<22> 12 28 MEM_A_A<3> L9 A4 DQ1 C8 MEM_A_DQ<31> 12 28 90
32 29 90 90 90
90
28 12 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<5> 12 28 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<15> 12 28 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<17> 12 28 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<28> 12 28 90
32 29 90 90 90
MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<7> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<10> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<16> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<27> 12 28 90
90 90 90
90
28 12 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<4> 12 28 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<12> 12 28 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<19> 12 28 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<29> 12 28 90
32 29 90 90 90
28 12 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<2> 12 28 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<8> 12 28 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<20> 12 28 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<26> 12 28 90
32 29 90 90 90
90
28 12
90 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<1> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<13> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<23> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<25> 12 28 90
32 29 90 90 90
90
28 12 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<3> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<11> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<18> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<30> 12 28 90
32 29 90 90 90
MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11
K8 DQS C4 MEM_A_DQS_P<0> 12 28 K8 DQS C4 MEM_A_DQS_P<1> 12 28 K8 DQS C4 MEM_A_DQS_P<2> 12 28 K8 DQS C4 MEM_A_DQS_P<3> 12 28
90
28 12 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
32 29
N4 DQS* D4 MEM_A_DQS_N<0> 12
90
28 N4 DQS* D4 MEM_A_DQS_N<1> 12 28 N4 DQS* D4 MEM_A_DQS_N<2> 12 28 N4 DQS* D4 MEM_A_DQS_N<3> 12 28
MEM_A_A<13> A13 90 32 29 28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
90 32 29 28 90 32 29 28
90
28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8
32 29
MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28
32
12
29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90 90
32
28
29
12 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 28 12 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 32 90
90 32 29 32 90 32 90
90 32
28 12 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 32 90
29 32 90 32 90 32 90
90
28 12 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
32 29 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90
90 32
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 32
12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 32 90
29 90 32 29 32 90 90
90
28 12 MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS* 90 32 29 28 12 MEM_A_CAS_L G4 CAS*
32 29 A1 A1 A1 A1
28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC
32 29 A4 A4 A4 A4
90
G2 A11
NC NC NC NC
29 12 MEM_A_ODT<1> ODT NC NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_A_ZQ<8> H9 ZQ NC MEM_A_ZQ<9> H9 ZQ NC MEM_A_ZQ<10> H9 ZQ NC MEM_A_ZQ<11> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
C R3000 R3010 R3020 R3030 C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3047 1
C3048 1 1 C3049 C3057 1
C3058 1 1 C3059 C3067 1 C3068 1 1 C3069 C3077 1 C3078 1 1 C3079
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC 90 32 29 28 12 MEM_A_A<0> K4 A0 NC
N11 N11 N11 N11
32 29
MEM_A_A<1> L8 A1 U3040 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U3050 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U3060 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U3070 NC
N3 MEM_RESET_L
L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 27 90
L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 27 28 29 30 31
90
28 12 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 28
31
29 30 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
32 29
MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<33> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<41> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<49> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<57>
28 12 A3 DQ0 28 12 A3 DQ0 12 28 A3 DQ0 12 28 A3 DQ0 12 28 90
32 29
L9 (SYM VER 2) C8 90 32 29
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8
90
28 12
32 29
90 MEM_A_A<3> A4 DQ1 MEM_A_DQ<32> 12 28 MEM_A_A<3> A4 DQ1 MEM_A_DQ<40> 12 28 MEM_A_A<3> A4 DQ1 MEM_A_DQ<48> 12 28 MEM_A_A<3> A4 DQ1 MEM_A_DQ<56> 12 28 90
90 90 90
90
28 12 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<35> 12 28 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<43> 28 12 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<51> 12 28 MEM_A_A<6> L3 A5 DQ2 C3 MEM_A_DQ<59> 12 28 90
32 29 90 90 32 29 90
MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<34> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<42> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<50> 12 28 MEM_A_A<5> M9 A6 DQ3 C9 MEM_A_DQ<58> 12 28 90
90 90 90
90
28 12 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<39> 12 28 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<47> 28 12 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<55> 12 28 MEM_A_A<8> M3 A7 NF/DQ4 E4 MEM_A_DQ<63> 12 28 90
32 29 90 90 32 29 90
28 12 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<38> 28 12 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<46> 12 28 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<54> 12 28 MEM_A_A<7> N9 A8 NF/DQ5 E9 MEM_A_DQ<62> 12 28 90
32 29 90 32 29 90 90
M4 D3 M4 D3 M4 D3 M4 D3
B 90
28 12
32 29
90
90
28 12
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<37>
MEM_A_DQ<36>
28
90 32
12 28
12
29
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<45>
MEM_A_DQ<44>
12 28
90
12 28
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<53>
MEM_A_DQ<52>
12 28
90
12 28
MEM_A_A<9>
MEM_A_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_A_DQ<61>
MEM_A_DQ<60>
12 28 90
12 28 90
B
32 29 90 90 90
MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11
K8 DQS C4 MEM_A_DQS_P<4> 12 28 K8 DQS C4 MEM_A_DQS_P<5> 12 28 K8 DQS C4 MEM_A_DQS_P<6> 12 28 K8 DQS C4 MEM_A_DQS_P<7> 12 28
90 32
28 12 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
29 90
N4 DQS* D4 MEM_A_DQS_N<4> 90
12 28 N4 DQS* D4 MEM_A_DQS_N<5> 90
12 28 N4 DQS* D4 MEM_A_DQS_N<6> 12 28 N4 DQS* D4 MEM_A_DQS_N<7> 12 28
32 29
28 12 MEM_A_A<13> A13 90 32 29 28 12 MEM_A_A<13> A13 90 32 29 28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
90 32 29 28
90
28
32
12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8
29
90
MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28
32
12
29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
32 29
28 12 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 32 90
32 90 32 90 32 90
90
28
32
12 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 28 12 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 MEM_A_BA<0> K9 BA1 CKE G10 MEM_A_CKE<1> 12 29 32 90
29 90 32 29 32 90 32 90
28
90
12 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
32 29 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90 CK F8 MEM_A_CLK_P<1> 12 29 32 90
90 32
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 32 90
29 90 32 29 32 90 32 90
90
28 12 MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS*
32 29 A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC 90 32 29 28 12 MEM_A_WE_L H4 WE* NC
32 29 A4 A4 A4 A4
90 NC NC NC NC
29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC 90 32 29 12 MEM_A_ODT<1> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_A_ZQ<12> H9 ZQ NC MEM_A_ZQ<13> H9 ZQ NC MEM_A_ZQ<14> H9 ZQ NC MEM_A_ZQ<15> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
R3040 R3050 R3060 R3070
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3107 1
C3108 1 1 C3109 C3117 1
C3118 1 1 C3119 C3127 1 C3128 1 1 C3129 C3137 1 C3138 1 1 C3139
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90 32
30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC
D
31
90
30 12
32 31
MEM_B_A<1> L8
L4
A1 U3100
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3110
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3120
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3130
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2
90 32
MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<6> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<14> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<18> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<27>
30 12
31 90
A3 (SYM VER 2) DQ0 30 12
90 32 31
A3 (SYM VER 2) DQ0 30 12 A3 (SYM VER 2) DQ0 30 12 A3 (SYM VER 2) DQ0 12 31 90
90 32 31 90 32 31
32 31
30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<1> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<9> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<20> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<25> 12 31 90
90 32 31 90 32 31 90 32 31
90
30
32
12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<3> 12 31 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<11> 30 12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<19> 12 31 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<26> 12 31 90
31 90 90 32 31 90
30
90
12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<5> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<13> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<16> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<29> 12 31 90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<2> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<10> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<23> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<30> 12 31 90
90 32 31 90 32 31 90 32 31
90 32
30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<4> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<12> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<21> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<28> 12 31 90
31 90 32 31 90 32 31 90 32 31
90
30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<7> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<15> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<22> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<31> 12 31 90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<0> MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<8> 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<17> 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<24> 12 31 90
90 32 31 90 32 31
90
30 12 MEM_B_A<11> M8 A11 90 32
30 12 MEM_B_A<11> M8 A11 90
30 12 MEM_B_A<11> M8 A11 90
30 12 MEM_B_A<11> M8 A11
32 31
K8 DQS C4 MEM_B_DQS_P<0> 31
K8 DQS C4 MEM_B_DQS_P<1> 32 31
K8 DQS C4 MEM_B_DQS_P<2> 32 31
K8 DQS C4 MEM_B_DQS_P<3> 12 31
30 12 MEM_B_A<12> A12/BC*
90
MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* 90
DQS* D4
30 12
DQS* D4
30 12
DQS* D4
30 12
32 31
N4 MEM_B_DQS_N<0> 32 31
N4 MEM_B_DQS_N<1> 32 31
N4 MEM_B_DQS_N<2> 32 31
N4 DQS* D4 MEM_B_DQS_N<3> 12 31
90
30 12
90 MEM_B_A<13> A13 90 32 31 30 12 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90
32 31
90
30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8
32 31
MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
90
30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
90
30 12
90 MEM_B_BA<2> J4 BA2 30 12 MEM_B_BA<2> J4 BA2 30 12 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<0> 32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90
90 90
90
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 32
12 30 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 12 30 32 90
32 31 90 32 31 32 31 90
MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS*
A1 A1 A1 A1
90
30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC
32 31 A4 A4 A4 A4
NC NC NC NC
30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_B_ZQ<0> H9 ZQ NC MEM_B_ZQ<1> H9 ZQ NC MEM_B_ZQ<2> H9 ZQ NC MEM_B_ZQ<3> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
C R3100 R3110 R3120 R3130 C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3147 1
C3148 1 1 C3149 C3157 1
C3158 1 1 C3159 C3167 1 C3168 1 1 C3169 C3177 1 C3178 1 1 C3179
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
30
32
12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC
N11 N11 N11 N11
31
30
90
12 MEM_B_A<1> L8 A1 U3140 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3150 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3160 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3170 NC
N3 MEM_RESET_L
32 31
L4 DDR3-1333 RESET* 90
L4 DDR3-1333 RESET* 90
L4 DDR3-1333 RESET* 90
L4 DDR3-1333 RESET* 27 28 29 30 31
MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2
90 32
MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<32> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<40> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<48> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<56>
30 12 A3 DQ0 12 31 A3 DQ0 30 12 A3 DQ0 30 12 A3 DQ0 12 31 90
31 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90 32 31
L9 (SYM VER 2) C8 90 32 31
L9 (SYM VER 2) C8
32 31
30 12 MEM_B_A<4> A4 DQ1 MEM_B_DQ<33> 30 12
90 32 31
MEM_B_A<4> A4 DQ1 MEM_B_DQ<41> 30 12 MEM_B_A<4> A4 DQ1 MEM_B_DQ<49> 30 12 MEM_B_A<4> A4 DQ1 MEM_B_DQ<57> 12 31 90
90 32 31 90 32 31
90 32
30 12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<34> 30 12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<42> 30 12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<50> 30 12 MEM_B_A<5> L3 A5 DQ2 C3 MEM_B_DQ<58> 12 31 90
31 90 32 31 90 32 31 90 32 31
90
30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<35> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<43> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<51> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<59> 12 31 90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<36> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<44> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<52> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<60> 12 31 90
90 32 31 90 32 31 90 32 31
90 32
30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<37> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<45> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<53> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<61> 12 31 90
31 90 32 31 90 32 31 90 32 31
M4 D3 M4 D3 M4 D3 M4 D3
B 90
30 12
32 31
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<38>
MEM_B_DQ<39>90
30
90 32
30 12
12
31
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<46>
MEM_B_DQ<47>90
30
90 32
30 12
12
31
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<54>
MEM_B_DQ<55>90
30
90 32
30 12
12
31
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<62>
MEM_B_DQ<63>
12 31 90
12 31 90
B
32 31 32 31 32 31
90
30 12 MEM_B_A<11> M8 A11
90
30 12 MEM_B_A<11> M8 A11
90
30 12 MEM_B_A<11> M8 A11
90
30 12 MEM_B_A<11> M8 A11
32 31
K8 DQS C4 MEM_B_DQS_P<4> 32 31
K8 DQS C4 MEM_B_DQS_P<5> 32 31
K8 DQS C4 MEM_B_DQS_P<6> 32 31
K8 DQS C4 MEM_B_DQS_P<7> 12 31
30 12 MEM_B_A<12> A12/BC* 30 12 MEM_B_A<12> A12/BC* 30 12 MEM_B_A<12> A12/BC* 30 12 MEM_B_A<12> A12/BC* 90
32 31
N4 DQS* D4 MEM_B_DQS_N<4> 32 31
N4 DQS* D4 MEM_B_DQS_N<5> 32 31
N4 DQS* D4 MEM_B_DQS_N<6> 32 31
N4 DQS* D4 MEM_B_DQS_N<7> 12 31
90
30 12
32 31
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90
90
30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8
32 31
MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
90
30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
90
30 12
90 MEM_B_BA<2> J4 BA2 30 12 MEM_B_BA<2> J4 BA2 30 12 MEM_B_BA<2> J4 BA2 30 12 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<0> 32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90
90 90 90
90
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 12 30 32 90
32 31 90 32 31 32 31 90 32 31
MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS*
A1 90 32 31 30 12 A1 90 32 31 30 12 A1 90 32 31 30 12 A1
90
30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC
32 31 A4 A4 A4 A4
NC NC NC NC
30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_B_ZQ<4> H9 ZQ NC MEM_B_ZQ<5> H9 ZQ NC MEM_B_ZQ<6> H9 ZQ NC MEM_B_ZQ<7> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
R3140 R3150 R3160 R3170
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3207 1
C3208 1 1 C3209 C3217 1
C3218 1 1 C3219 C3227 1 C3228 1 1 C3229 C3237 1 C3238 1 1 C3239
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC
D
32 31
MEM_B_A<1> L8
L4
A1 U3200
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3210
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3220
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L 32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3230
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
90
30 12 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2
32 31
MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<1> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<9> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<20> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<25>
30 12
32 31
A3 (SYM VER 2) DQ0 12 30
90
A3 (SYM VER 2) DQ0 12 30 A3 (SYM VER 2) DQ0 12 30 A3 (SYM VER 2) DQ0 12 30 90
90 90
90
30 12
90 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<6> 30 12 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<14> 12 30 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<18> 12 30 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<27> 12 30 90
32 31 90 32 31 90 90
90
30 12 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<5> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<13> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<16> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<29> 12 30 90
32 31 90 90 90
MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<3> 30 12 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<11> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<19> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<26> 12 30 90
90 32 31 90 90
90
30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<0> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<8> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<17> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<24> 12 30 90
32 31 90 90 90
30 12 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<7> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<15> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<22> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<31> 12 30 90
32 31 90 90 90
90
30 12
90 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<4> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<12> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<21> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<28> 12 30 90
32 31 90 90 90
90
30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<2> 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<10> 12 30 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<23> 12 30 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<30> 12 30 90
32 31 90 32 31 90 90
MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11
K8 DQS C4 MEM_B_DQS_P<0> 12 30 K8 DQS C4 MEM_B_DQS_P<1> 12 30 K8 DQS C4 MEM_B_DQS_P<2> 12 30 K8 DQS C4 MEM_B_DQS_P<3> 12 30
90 32
30 12 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90
31 90
N4 DQS* D4 MEM_B_DQS_N<0> 12 30 N4 DQS* D4 MEM_B_DQS_N<1> 12 30 N4 DQS* D4 MEM_B_DQS_N<2> 12 30 N4 DQS* D4 MEM_B_DQS_N<3> 12 30
32 31
30 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90
90 32 31 30 90 32 31 30 90 32 31 30
90 32
30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8
31
90
MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
32 31
30 12 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 32 90
32 90 32 90 32 90
90 32
30 12 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 32 90
31 32 90 32 90 32 90
90
30 12 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90
90 32
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 32 90
31 32 90 32 90 32 90
90
30 12 MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS* 90 32 31 30 12 MEM_B_CAS_L G4 CAS*
32 31 A1 A1 A1 A1
30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC
32 31 A4 A4 A4 A4
90 NC NC NC NC
31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_B_ZQ<8> H9 ZQ NC MEM_B_ZQ<9> H9 ZQ NC MEM_B_ZQ<10> H9 ZQ NC MEM_B_ZQ<11> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
C R3200 R3210 R3220 R3230 C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
C3247 1
C3248 1 1 C3249 C3257 1
C3258 1 1 C3259 C3267 1 C3268 1 1 C3269 C3277 1 C3278 1 1 C3279
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC
NC
NC
NC
OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC OMIT_TABLE N1 NC
90
30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC 90 32 31 30 12 MEM_B_A<0> K4 A0 NC
N11 N11 N11 N11
32 31
MEM_B_A<1> L8 A1 U3240 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3250 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3260 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3270 NC
N3 MEM_RESET_L
L4 DDR3-1333 RESET* 90
L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 90 27 28 29 L4 DDR3-1333 RESET* 27 28 29 30 31
90
30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2
32 31
MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<33> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<41> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<49> MEM_B_A<4> K3 FBGA B4 MEM_B_DQ<57>
A3 DQ0 12 30 A3 DQ0 12 30 A3 DQ0 12 30 A3 DQ0 12 30 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8 90
L9 (SYM VER 2) C8
90
30 12
32 31
MEM_B_A<3> A4 DQ1 MEM_B_DQ<32> 12 30 MEM_B_A<3> A4 DQ1 MEM_B_DQ<40> 12 30 MEM_B_A<3> A4 DQ1 MEM_B_DQ<48> 12 30 MEM_B_A<3> A4 DQ1 MEM_B_DQ<56> 12 30 90
90 90 90
MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<35> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<43> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<51> 30 12 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<59> 12 30 90
90 90 90 32 31
90 32
30 12 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<34> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<42> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<50> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<58> 12 30 90
31 90 90 90
90
30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<39> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<47> 30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<55> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<63> 12 30 90
32 31 90 90 32 31 90
30 12 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<38> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<46> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<54> 12 30 MEM_B_A<7> N9 A8 NF/DQ5 E9 MEM_B_DQ<62> 12 30 90
32 31 90 90 90
M4 D3 M4 D3 M4 D3 M4 D3
B 90
30 12
32 31
90
90
30 12
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<37>
MEM_B_DQ<36>
12 30
90
12 30
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<45>
MEM_B_DQ<44>
12 30
90
12 30
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<53>
MEM_B_DQ<52>
12 30
90
12 30
MEM_B_A<9>
MEM_B_A<10> H8
A9
A10/AP
NF/DQ6
NF/DQ7 E8
MEM_B_DQ<61>
MEM_B_DQ<60>
12 30 90
12 30 90
B
32 31 90 90 90
MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11
K8 DQS C4 MEM_B_DQS_P<4> 12 30 K8 DQS C4 MEM_B_DQS_P<5> 12 30 K8 DQS C4 MEM_B_DQS_P<6> 12 30 K8 DQS C4 MEM_B_DQS_P<7> 12 30
90 32
30 12 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90
31 90
N4 DQS* D4 MEM_B_DQS_N<4> 12 30 N4 DQS* D4 MEM_B_DQS_N<5> 12 30 N4 DQS* D4 MEM_B_DQS_N<6> 12 30 N4 DQS* D4 MEM_B_DQS_N<7> 12 30
32 31
30 12 MEM_B_A<13> A13 90
90 32 31
12
30
MEM_B_A<13> A13 90
90 32 31
12
30
MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90
90 32 31 30
90
30
32
12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8
31
90
MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8
30
32
12
31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
32 31
30 12 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 MEM_B_BA<1> J3 BA0 CS* H3 MEM_B_CS_L<1> 12 31 32 90
32 90 32 90 32 90
90 32
30 12 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 30 12 MEM_B_BA<0> K9 BA1 CKE G10 MEM_B_CKE<1> 12 31 32 90
31 32 90 32 90 90 32 31
90
30 12 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90
90 32
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 32 90
31 32 90 32 90 32 31
90
30 12 MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS*
32 31 A1 90 32 31 30 12 A1 90 32 31 30 12 A1 90 32 31 30 12 A1
30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC 90 32 31 30 12 MEM_B_WE_L H4 WE* NC
32 31 A4 A4 A4 A4
90 NC NC NC NC
31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC 90 32 31 12 MEM_B_ODT<1> G2 ODT NC
A11
NC
90 32
F2 F2 F2 F2
MEM_B_ZQ<12> H9 ZQ NC MEM_B_ZQ<13> H9 ZQ NC MEM_B_ZQ<14> H9 ZQ NC MEM_B_ZQ<15> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
2 2 2 2
R3240 R3250 R3260 R3270
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
8 =PP0V75_S0_MEM_VTT_A
90 29 12 MEM_A_CS_L<1> RP3305 36 1 8
IN
90 28 12 MEM_A_CKE<0> RP3301 36 4 5 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<0> RP3302 36 2 7 5% 1/32W 4X0201 1 C3300
IN
90 29 28 12 MEM_A_A<7> RP3306 36 2 7 5% 1/32W 4X0201 0.47UF
IN 20%
90 29 28 12 MEM_A_A<5> RP3303 36 1 8 5% 1/32W 4X0201
2 4V
IN CERM-X5R-1
90 29 28 12 MEM_A_BA<0> RP3302 36 1 8 5% 1/32W 4X0201 201
IN
90 28 12 MEM_A_ODT<0> RP3301 36 2 7 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<15> RP3305 36 2 7 5% 1/32W 4X0201
D 90 29 28 12
IN
IN MEM_A_BA<1> RP3303 36 2 7
5% 1/32W 4X0201 1 C3302
0.47UF
1 C3303
0.47UF
D
90 29 28 12 MEM_A_A<14> RP3307 36 3 6 5% 1/32W 4X0201 20% 20%
IN 4V 4V
90 29 28 12 MEM_A_A<8> RP3306 36 1 8 5% 1/32W 4X0201 2 CERM-X5R-1 2 CERM-X5R-1
IN 201 201
5% 1/32W 4X0201
90 29 28 12 MEM_A_A<12> RP3305 36 3 6
IN
90 29 28 12 MEM_A_A<9> RP3306 36 4 5 5% 1/32W 4X0201 1 C3304 1 C3305
IN
90 29 28 12 MEM_A_BA<2> RP3302 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
90 29 12 MEM_A_ODT<1> RP3304 36 3 6 5% 1/32W 4X0201
2 4V 2 4V
IN CERM-X5R-1 CERM-X5R-1
90 29 28 12 MEM_A_A<4> RP3303 36 4 5 5% 1/32W 4X0201 201 201
IN
90 29 28 12 MEM_A_RAS_L RP3304 36 1 8 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<1> RP3307 36 2 7 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_WE_L RP3302 36 4 5 5% 1/32W 4X0201 1 C3306 1 C3307
IN
90 29 28 12 MEM_A_A<6> RP3303 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
90 29 28 12 MEM_A_A<2> RP3307 36 1 8 5% 1/32W 4X0201
2 4V 2 4V
IN CERM-X5R-1 CERM-X5R-1
90 29 28 12 MEM_A_A<3> RP3305 36 4 5 5% 1/32W 4X0201 201 201
IN
5% 1/32W 4X0201
RP3307
1 C3308
90 29 28 12 IN MEM_A_A<13> 36 4 5 0.47UF
20%
90 29 12 MEM_A_CKE<1> RP3304 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
IN
90 29 28 12 MEM_A_A<10> RP3304 36 4 5 5% 1/32W 4X0201 201
IN
90 29 28 12 MEM_A_CAS_L RP3301 36 3 6 5% 1/32W 4X0201
IN
90 28 12 MEM_A_CS_L<0> RP3301 36 1 8 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<11> RP3306 36 3 6 5% 1/32W 4X0201 1 C3310
IN
5% 1/32W 4X0201 0.47UF
20%
4V
2 CERM-X5R-1
C 201
C
8 =PP0V75_S0_MEM_VTT_B
90 30 12 MEM_B_ODT<0> RP3322 36 2 7
IN
90 31 30 12 MEM_B_A<13> RP3325 36 1 8 5% 1/32W 4X0201 1 C3320
IN
5% 1/32W 4X0201 0.47UF
90 31 30 12 MEM_B_A<15> RP3328 36 1 8 20%
IN 4V
90 31 30 12 MEM_B_A<11> RP3325 36 2 7 5% 1/32W 4X0201 2 CERM-X5R-1
IN 201
5% 1/32W 4X0201
90 31 30 12 MEM_B_CAS_L RP3328 36 2 7
IN
90 31 30 12 MEM_B_A<1> RP3325 36 3 6 5% 1/32W 4X0201
IN
5% 1/32W 4X0201
MEM Clock Termination 90 30 12 MEM_B_CS_L<0> RP3320 36 2 7 1 C3322 1 C3323
IN
Place RC end termination after last DRAM 90 31 30 12 MEM_B_A<14> RP3326 36 4 5 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
Place Source Cterm at neckdown at first DRAM 90 31 30 12 MEM_B_A<0> RP3330 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
IN
90 31 30 12 MEM_B_BA<2> RP3320 36 3 6 5% 1/32W 4X0201 201 201
IN
MEM_B_BA<1> RP3330 36 1 8 5% 1/32W 4X0201
R3350 C3351 90 31 30 12 IN
RP3330 36 3 6 5% 1/32W 4X0201
0.1UF 90 31 30 12 IN MEM_B_A<4>
30 RP3324 5% 1/32W 4X0201
90 28 12 IN MEM_A_CLK_N<0> 1 2 MEM_A_CLK0_TERM_R 1 2 90 31 12 IN MEM_B_CS_L<1>
RP3326
36 4 5
5% 1/32W 4X0201
1 C3324 1 C3325
5% 90 31 30 12 IN MEM_B_A<6> 36 2 7 0.47UF 0.47UF
10% 20% 20%
C3350 1
1/20W
MF 6.3V 90 31 30 12 MEM_B_A<12> RP3324 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
X5R IN
3.3PF 201
201 90 31 30 12 MEM_B_A<9> RP3326 36 3 6 5% 1/32W 4X0201 201 201
5% IN
PLACE_NEAR=U2900.F7:3.2mm 25V
MEM_B_CKE<0> RP3322 36 3 6 5% 1/32W 4X0201
CERM 2 90 30 12 IN
201 R3351 90 31 30 12 IN MEM_B_A<7> RP3326 36 1 8 5% 1/32W 4X0201
30 RP3330 36 5% 1/32W 4X0201
B 90 28 12 IN MEM_A_CLK_P<0> 1 2 90 31 30 12 IN MEM_B_A<5>
RP3324
4 5
5% 1/32W 4X0201
1 C3326 1 C3327 B
5% 90 31 30 12 IN MEM_B_A<3> 36 3 6 0.47UF 0.47UF
20% 20%
1/20W
MF 90 31 30 12 MEM_B_A<2> RP3324 36 2 7 5% 1/32W 4X0201
2 4V 2 4V
IN CERM-X5R-1 CERM-X5R-1
201
90 31 30 12 MEM_B_A<8> RP3325 36 4 5 5% 1/32W 4X0201 201 201
IN
R3355 C3356 5% 1/32W 4X0201
0.1UF
MEM_A_CLK_N<1> 30 RP3320 36
1 2 MEM_A_CLK1_TERM_R 1 2 MEM_B_BA<0> 4 5
90 29 12 IN
5%
90 31 30 12 IN
MEM_B_A<10> RP3320 36 1 8 5% 1/32W 4X0201 1 C3328
1/20W 10% 90 31 30 12 IN
RP3322 5% 1/32W 4X0201
0.47UF
C3355 1 MF 6.3V 90 31 30 12 IN MEM_B_RAS_L 36 1 8 20%
3.3PF 201 X5R
201 5% 1/32W 4X0201 2 4V
CERM-X5R-1
5% 201
PLACE_NEAR=U3000.F7:3.2mm 25V
CERM 2
201 R3356
30 RP3328 36
90 29 12 MEM_A_CLK_P<1> 1 2 90 31 12 MEM_B_ODT<1> 4 5
IN
5%
IN
MEM_B_CKE<1> RP3328 36 3 6 5% 1/32W 4X0201 1 C3330
1/20W
90 31 12 IN
RP3322 5% 1/32W 4X0201
0.47UF
MF 90 31 30 12 IN MEM_B_WE_L 36 4 5 20%
4V
201 5% 1/32W 4X0201 2 CERM-X5R-1
201
R3360 C3361
0.1UF
30
90 30 12 IN MEM_B_CLK_N<0> 1 2 MEM_B_CLK0_TERM_R 1 2
5%
1/20W 10%
C3360 1 MF
201
6.3V
X5R
PLACE_NEAR=U3170.F7:3.2mm3.3PF
5%
201
25V
CERM 2
201
R3361
30
90 30 12 IN MEM_B_CLK_P<0> 1 2
5%
1/20W
MF
201
A R3365 C3366
0.1UF
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
30 PAGE TITLE
MEM_B_CLK_N<1> MEM_B_CLK1_TERM_R 1 2
90 31 12 IN 1
5%
2
10%
DDR3 Termination
1/20W DRAWING NUMBER SIZE
C3365 1 MF
201
6.3V
X5R 051-9589 D
3.3PF 201 Apple Inc.
PLACE_NEAR=U3270.F7:3.2mm 5% REVISION
25V
CERM 2 R
201 R3366 4.18.0
30 NOTICE OF PROPRIETARY PROPERTY: BRANCH
90 31 12 IN MEM_B_CLK_P<1> 1 2
THE INFORMATION CONTAINED HEREIN IS THE
5% PROPRIETARY PROPERTY OF APPLE INC.
1/20W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF
201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
8 =PP3V3_S3_VREFMRGN
buffers at once or VRef source may be overloaded.
VREFDQ:LDO_DAC
OMIT
=PPVTT_S3_DDR_BUF R3403
R3418 64 8
200 PLACE_NEAR=J2900.1:2.54mm
1
SHORT
2 PP3V3_S3_VREFMRGN_DAC
10mA max load 1 2
MIN_LINE_WIDTH=0.3 mm CRITICAL 1%
NONE MIN_NECK_WIDTH=0.2 mm DDRVREF_DAC DDRVREF_DAC 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE C3400 1 1 C3401 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFDQ_A
402
2.2UF 0.1UF DDRVREF_DAC 28 29 33 89
20% 20% CRITICAL C3403 1
B1 U3402 MIN_LINE_WIDTH=0.3 mm
VREFDQ:LDO_DAC MIN_NECK_WIDTH=0.2 mm
D
6.3V
CERM
402-LF
2 2
10V
CERM
402
DDRVREF_DAC
U3400
0.1UF
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
A1
R3404
133
VOLTAGE=0.75V
D
8
402
VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD
A3 A4 1% PLACE_NEAR=R3403.2:1mm
44 IN =I2C_VREFDACS_SCL 6 SCL
MSOP VOUTA 1 VREFMRGN_SODIMMA_DQ V- 1/16W
MF-LF
B4
DAC5574
402
44 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF VREFDQ:LDO_DAC
NC
100K MF-LF
OMIT 5% 402
1/16W DDRVREF_DAC PP0V75_S3_MEM_VREFDQ_B 30 31 33 89
R3419 MF-LF VREFDQ:LDO_DAC MIN_LINE_WIDTH=0.3 mm
2 402 C2
B1 U3402 MIN_NECK_WIDTH=0.2 mm
SHORT MAX4253 R3406 VOLTAGE=0.75V
1 2 PP3V3_S3_VREFMRGN_CTRL V+ UCSP
MIN_LINE_WIDTH=0.3 mm
C1
133
NONE VREFMRGN_DQ_SODIMMB_BUF 1 2
16
C3402 1 V- MF-LF
Power aliases required by this page: 0.1UF VCC
B4 402
- =PP3V3_S3_VREFMRGN 20%
10V
2 U3401
NC
CERM
- =PPVTT_S3_DDR_BUF 402 PCA9557 VREFCA:LDO_DAC
- =PPDDR_S3_MEMVREF QFN
6
DDRVREF_DAC R3409
(OD) P0 NC 1
R3402 200 PLACE_NEAR=J2900.126:2.54mm
3 A0 P1 7 VREFMRGN_DQ_SODIMMA_EN 1 2
Signal aliases required by this page: 100K CRITICAL
Addr=0x30(WR)/0x31(RD) 4 A1 P2 9 VREFMRGN_DQ_SODIMMB_EN 5% 1%
- =I2C_VREFDACS_SCL 5 10 VREFMRGN_CA_SODIMMA_EN
1/16W 1/16W
A2 P3 MF-LF MF-LF
- =I2C_VREFDACS_SDA 11 VREFMRGN_CA_SODIMMB_EN 2
402 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFCA_A
P4 DDRVREF_DAC 28 29 89
- =I2C_PCA9557D_SCL C3404
C - =I2C_PCA9557D_SDA =I2C_PCA9557D_SCL 1
P5
P6
12
13
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
0.1UF
20%
1
A2
B1
V+
U3403
MAX4253
VREFCA:LDO_DAC
R3410
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
C
44 IN SCL 10V UCSP
CERM 2
A1
133
BOM options provided by this page: 44 BI =I2C_PCA9557D_SDA 2
SDA P7 14
NC 402
VREFMRGN_CA_SODIMMA_BUF 1 2
17
8
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs. R3411
200 PLACE_NEAR=J3100.126:2.54mm
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs. 1 2
1%
25 IN PCA9557D_RESET_L DDRVREF_DAC 1/16W
NC
MF-LF
1
R3407 CRITICAL 402
RST* on ’platform reset’ so that system DDRVREF_DAC PP0V75_S3_MEM_VREFCA_B 30 31 89
100K VREFCA:LDO_DAC MIN_LINE_WIDTH=0.3 mm
watchdog will disable margining. 5%
C2
B1 U3403 MIN_NECK_WIDTH=0.2 mm
1/16W MAX4253 R3412 VOLTAGE=0.75V
MF-LF V+ UCSP
NOTE: Margining will be disabled across all 2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133
2
soft-resets and sleep/wake cycles.
C3 C4 1% PLACE_NEAR=R3411.2:1mm
33 8 =PPDDR_S3_MEMVREF V- 1/16W
MF-LF
B4 402
CRITICAL PLACE_NEAR=Q3420.6:1mm
PLACE_NEAR=Q3420.6:2mm
NC
VREFDQ:M1_M3 VREFDQ:M1_M3
VREFDQ:M1_M3 1
Q3420 R3421 DDRVREF_DAC
1
C3420 1
SSM6N15FEAPE 0.1UF 1K R3408
1%
2
2 X7R-CERM MF-LF 5%
0402 2
402 1/16W DDRVREF_DAC DDRVREF_DAC
MF-LF DDRVREF_DAC
2 402
C3405 1
C2
B1 U3404
MAX4253 R3414
S
89 10 PPCPU_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A 28 29 33 89
0.1UF V+ UCSP
B 20% 33.2K
B
6
1
NC
33 8 DDRVREF_DAC
DDRVREF_DAC 1
CRITICAL PLACE_NEAR=Q3420.3:1mm 1 R3413 DDRVREF_DAC
VREFDQ:M1_M3 PLACE_NEAR=Q3420.3:2mm VREFDQ:M1_M3 R3416 100K B1 U3404 DDRVREF_DAC Required zero ohm resistors when no VREF margining circuit stuffed
0 A2
5% MAX4253
Q3420 VREFDQ:M1_M3 1
R3441 5% 1/16W V+ UCSP CRITICAL
1
R3417
1/16W MF-LF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SSM6N15FEAPE 1 C3440 1K MF-LF
2
402 A1 0
1% 402 5%
0.1UF
5
89 10 PPCPU_MEM_VREFDQ_B PP0V75_S3_MEM_VREFDQ_B 30 31 33 89
NC
3
4
VREFDQ:M1_M3 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1
R3442 DDRVREF_DAC
1
114S0218 4 RES,MTL FILM,1K,1%,0402,SM,LF R3421,R3422,R3441,R3442 VREFDQ:M1_DAC
1K R3415
1%
PLACE_NEAR=R3441.2:1mm 1/16W 100K 114S0171 2 RES,MTL FILM,332,1%,0402,SM,LF R3404,R3406 VREFDQ:M1_DAC
MF-LF 5%
402 1/16W
2
MF-LF
402
2
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
DAC Channel: A B C C D D
DDR3/FRAMEBUF VREF MARGINING
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
Apple Inc. 051-9589 D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
4.18.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.000V - 2.000V (+/- 500mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.000V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VRef current: +3.4mA - -3.4mA (- = sourced) +61uA - -61uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
34 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output
IV ALL RIGHTS RESERVED 33 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
L3570 PLACE_NEAR=J3501.15:2.54MM
92 PCIE_AP_R2D_PI_P C3531
1 2 1 2
0.1UF PCIE_AP_R2D_C_P 17 92
IN
10% 16V X7R-CERM0402
0.6NH+/-0.1NH-0.85A
0201 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
NOSTUFF
NOSTUFF
1 C3570 117S0002 4 RES, 0OHM, 0201 L3570,L3571,L3573,L3574
1 C3571
D 2
0.1UF
10%
16V
X5R-CERM
0.1UF
10%
16V
D
0201
2 X5R-CERM
0201
L3571
1 2 92 PCIE_AP_R2D_PI_N 1 2
0.1UF PCIE_AP_R2D_C_N IN 17 92
LOADING 1 A (EDP)
OMIT_TABLE
L3573 CRITICAL
1 2 PCIE_AP_D2R_P OUT 17 92
Q3550
NOSTUFF
DMP2018LFK
92 7 PCIE_AP_R2D_P 0.6NH+/-0.1NH-0.85A DFN2563-6
1 C3574 0201 1 C3575
92 7 PCIE_AP_R2D_N 155S0367
0.1UF 0.1UF
10% 10% 2
2 16V
NOSTUFF
2 16V
L3504 CURRENT SENSE
S
X5R-CERM X5R-CERM 4 1
CRITICAL 0201 0201 1A PEAK FERR-120-OHM-3A
L3574 42 7 PP3V3_WLAN 1 2 PP3V3_WLAN_F IN 34 99 OUT PP3V3_WLAN_R =PP3V3_S3_WLAN 8 34
514S0335 MIN_LINE_WIDTH=1 mm
0603
MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=1 mm
G
J3501 1 2 PCIE_AP_D2R_N OUT 17 92
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
1
SSD-K99 NOSTUFF C3522 1
C3521 1
3 C3551 1 R3551
F-RT-SM1 0.6NH+/-0.1NH-0.85A 10K
1 C3576 0201 1 C3577 0.1uF 0.1uF 0.033UF 5%
C 1
2 2
0.1UF
10%
16V
NOSTUFF
OMIT_TABLE
2
0.1UF
10%
16V
20%
10V
CERM
402
2
20%
10V
CERM
402
2
C3550
0.1UF
10%
16V
X5R
402
2
R3550 2
1/16W
MF-LF
402
C
X5R-CERM X5R-CERM
3 0201 0201
PLACE_NEAR=J3501.29:2.54MM PLACE_NEAR=J3501.29:2.54MM 33K
92 7 PCIE_AP_D2R_PI_P 1 2 P3V3WLAN_SS 1 2 PM_WLAN_EN_L IN 70
4
5
92 7 PCIE_AP_D2R_PI_N
CRITICAL
L3501
AIRPORT 10%
16V
X7R-CERM
5%
1/16W
MF-LF
402
6 90-OHM-100MA 0402
DLP11S
7 SYM_VER-1
8 96 7 PCIE_CLK100M_AP_CONN_P 1 2 PCIE_CLK100M_AP_P 17 92
IN
9
10
11
96 7 PCIE_CLK100M_AP_CONN_N 4 3 PCIE_CLK100M_AP_N IN 17 92
12 PLACE_NEAR=J3501.11:2.54MM
SIGNAL_MODEL=EMPTY
13
BLUETOOTH PP3V3_S3RS4_BT_F 7 34
BTPWR:S4
=BT_WAKE_L OUT 42
14
PCIE_WAKE_L OUT 7 18
Q3510
SSM3K15FV D 3
15 NOSTUFF BTPWR:S3 NOSTUFF SOD-VESM-HF
16 91 7 USB_BT_CONN_N
1
R3517 R35181 1 C3510 1
R3514
15K 0 0.1UF 15K
17 USB_BT_CONN_P 10%
9
91 7 1% 5% 6.3V 1%
18 BTPWR:S4 1/20W 1/20W 2 X5R 1/20W
PP3V3_S3RS4_BT_F MF MF VCC MF
L3505 201
MIN_LINE_WIDTH=0.5 mm
2 201 201 2 2 201 1 G S 2
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1 Y+ M+ 5 91 USB_BT_WAKE_P
19 2 1 =PP3V3_S4_BT 8
1 C3532 2 Y- M- 4 91 USB_BT_WAKE_N
20
0.01UF FERR-120-OHM-1.5A NOSTUFF NOSTUFF U3510 BTPWR:S4 NOSTUFF
21 1 PI3USB102ZLE
2
10%
16V
0402-LF
PLACE_NEAR=J3501.27:2.54MM
R3515 1R3516 TQFN
D+ 7 USB_BT_P BI 9 91
1
R3512 1R3513
X7R-CERM
15K 15K CRITICAL 15K 15K
0402
1% 1% D- 6 USB_BT_N BI 9 91 1% 1%
BTPWR:S3 1/20W 1/20W 1/20W 1/20W
MF MF MF MF
L3506 2 201 2 201 2 201 2 201
B 2 1 =PP3V3_S3_BT 8
10 SEL
GND
OE* 8 Supervisor & CLKFREG # Isolation B
BTPWR:S4
FERR-120-OHM-1.5A Delay = 130 ms +/- 20%
3
0402-LF R3511
PLACE_NEAR=J3501.27:2.54MM
1
0 2
PP3V3_WLAN_F =PP3V3_S3_WLAN
IN PM_SLP_S4_L BTMUX_SEL 34 99 8 34
5%
1/20W
SEL OUTPUT
NOSTUFF
MF
1
CRITICAL
201 C3511 1 L USB_BT_WAKE 1
R3553
1
R3554 VDD
0.01UF H USB_BT 100K 232K 1
C3540
10%
16V
X7R-CERM 2
1%
1/16W
1%
1/16W U3540 0.1uF
20%
0402
2
MF-LF
402
2
MF-LF
402
SLG4AP041V 2
10V
CERM
TDFN 402
P3V3WLAN_VMON
2 SENSE
+
VREF -
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
518S0767 1 CONN,HDR,TWIN-AX,P=0.4MM,6P,HF J3502 CRITICAL DLY
7 AP_RESET_CONN_L
4 RESET* AP_RESET_L
OMIT MR* 3 IN 25
CRITICAL
J3502 AP_PWR_EN
EN 6 IN 19 24 70
CCR20-6K710S
F-RT-SM 7 AP_CLKREQ_Q_L OUT 8 OUT 17
7 IN (OD)
8 AP_CLKREQ_L
THRM
PAD GND
1
5
6 =I2C_ALS_SDA 44
R3555
BI
100K
5 =I2C_ALS_SCL IN 44 1%
275 mA peak 1/16W
4 7 PP5V_S3_ALSCAMERA_F PLACE_NEAR=J3502.6:2.54MM MF-LF
MIN_LINE_WIDTH=0.5 mm 206 mA nominal max 402
3 91 7 USB_CAMERA_CONN_N MIN_NECK_WIDTH=0.2 mm 2
A
2
1
91 7 USB_CAMERA_CONN_P
VOLTAGE=5V
ALS L3508
FERR-120-OHM-1.5A
A
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012
2 1 =PP5V_S3_ALSCAMERA 8
PAGE TITLE
7
CRITICAL
L3507
CAMERA 0402-LF
X29/ALS/CAMERA CONNECTOR
90-OHM
1
C3552 DRAWING NUMBER SIZE
DLP0NS
SYM_VER-1
0.1uF
20%
Apple Inc. 051-9589 D
10V
1 2
2 CERM REVISION
USB_CAMERA_N 19 91 R
BI 402
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
4 3 USB_CAMERA_P BI 19 91 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
PLACE_NEAR=J3502.3:2.54MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
NO_TEST=TRUE
NO_TEST=TRUE
92 9 IN PCIE_TBT_R2D_C_P<0> C3600 1 2
AB9 OMIT_TABLE AD5
C3640 1 2 PCIE_TBT_D2R_P<0> OUT 9 92
10% 16V X5R-CERM0201 92 PCIE_TBT_R2D_P<0> PERP_0 PETP_0 92 PCIE_TBT_D2R_C_P<0> 10% 16V X5R-CERM 0201
0.1UF 0.1UF
92 PCIE_TBT_R2D_N<0> AA10
PERN_0 U3600 PETN_0 AD7 92 PCIE_TBT_D2R_C_N<0>
92 9 IN PCIE_TBT_R2D_C_N<0> C3601 1 2
CACTUSRIDGE4C C3641 1 2
PCIE_TBT_D2R_N<0> OUT 9 92
10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
0.1UF FCBGA NO_TEST=TRUE 0.1UF
NO_TEST=TRUE NO_TEST=TRUE
(SYM 1 OF 2)
92 9 IN PCIE_TBT_R2D_C_P<1> C3602 1 2 C3642 1 2 PCIE_TBT_D2R_P<1> OUT 9 92
PCIE GEN2
PCIE_TBT_R2D_P<1> AA12 AD9 PCIE_TBT_D2R_C_P<1>
10% 16V X5R-CERM 0201 92 PERP_1 PETP_1 92 10% 16V X5R-CERM 0201
0.1UF AB13 AD11
0.1UF
92 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 92 PCIE_TBT_D2R_C_N<1>
RECEIVE
TRANSMIT
92 9 IN PCIE_TBT_R2D_C_N<1> C3603 1 2
C3643 1 2
PCIE_TBT_D2R_N<1> OUT 9 92
10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
0.1UF NO_TEST=TRUE 0.1UF
NO_TEST=TRUE
NO_TEST=TRUE
92 9 PCIE_TBT_R2D_C_P<2> C3604 1 2 C3644 1 2 PCIE_TBT_D2R_P<2> 9 92
D
IN
0.1UF
10% 16V X5R-CERM 0201 92
92
PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>
AB15
AA16
PERP_2
PERN_2
PETP_2
PETN_2
AD13
AD15
92
92
PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>
0.1UF
10% 16V X5R-CERM 0201
OUT
D
92 9 IN PCIE_TBT_R2D_C_N<2> C3605 1 2 C3645 1 2 PCIE_TBT_D2R_N<2> OUT 9 92
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF NO_TEST=TRUE NO_TEST=TRUE 0.1UF
37 36 35 =PP3V3_S4_TBT
NO_TEST=TRUE NO_TEST=TRUE
92 9 IN PCIE_TBT_R2D_C_P<3> C3606 1 2
AA18 AD17
C3646 1 2 PCIE_TBT_D2R_P<3> OUT 9 92
10% 16V X5R-CERM0201 92 PCIE_TBT_R2D_P<3> PERP_3 PETP_3 92 PCIE_TBT_D2R_C_P<3> 10% 16V X5R-CERM 0201
R36101 0.1UF
92 PCIE_TBT_R2D_N<3> AB19
PERN_3 PETN_3 AD19 92 PCIE_TBT_D2R_C_N<3>
0.1UF
47K 92 9 IN PCIE_TBT_R2D_C_N<3> C3607 1 2 C3647 1 2 PCIE_TBT_D2R_N<3> OUT 9 92
5% 10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
1/20W 0.1UF NO_TEST=TRUE 0.1UF
MF R6 U20 37 36 35 =PP3V3_S4_TBT
201 2 37 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE
37 IN TBT_PWR_ON_POC_RST_L J2
PWR_ON_POC_RSTN W20
RBIAS TBT_RBIAS 1
R3655
NO STUFF
1K R36851 1
R3686
=PP3V3_TBTLC_RTR 8 35 36 37 C3610 1 TP_TBT_MONDC0 AD23
MONDC0
NC U4 1% 10K
5%
10K
5%
0.1UF OMIT TP_TBT_MONDC1 AC24
MONDC1 NC 1/20W
MF 1/20W 1/20W
10% 201 MF MF
16V 1
X5R-CERM 2
0201
R3615 DEBUG: For monitoring current/voltage
2
201 2 2 201
C3690 1
R3692 1
1
R3693 NOSTUFF TBT_MONOBSP W18
MONOBS_P
R3690 1
1
R3691 1UF NONE W16 84 35 TBT_A_DP_PWRDN
3.3K 3.3K NONE TBT_MONOBSN MONOBS_N
3.3K 3.3K 10%
5% 5% NONE Not used in host mode. 85 35 TBT_B_DP_PWRDN
PCIE RESET
6.3V
5% 5% 2 1/20W 1/20W 0201 2 DEBUG: For monitoring clock
MISC
1/20W 1/20W
CERM
402 CRITICAL MF MF Y7 PCIE_RST_0_N N6 TP_TBT_PCIE_RESET0_L 7 84 37 35 TBT_A_HV_EN
MF MF 201 201 47 TP_TBT_THERM_DP THERMDA
201
2 2
201 8 OMIT_TABLE 2 2 Use AA8 GND ball for THERM_DN PCIE_RST_1_N T1 TP_TBT_PCIE_RESET1_L 7 85 37 35 TBT_B_HV_EN
Y5 TP_TBT_PCIE_RESET2_L
VCC R4 PCIE_RST_2_N 7
93 TBT_SPI_MOSI EE_DI U2 TP_TBT_PCIE_RESET3_L R36881 1
R3687
EEPROM
5 2 P5 PCIE_RST_3_N 7
(TBT_SPI_MOSI) D U3690
M95256-RMC6XG
Q (TBT_SPI_MISO) 93 TBT_SPI_MISO
TBT_SPI_CS_L AD3
EE_DO
10K 10K
6
93 EE_CS_N W6 5% 5%
(TBT_SPI_CLK) C MLP W4 PCIE_CLKREQ_OD_N =TBT_CLKREQ_L OUT 37 1/20W 1/20W
93 TBT_SPI_CLK EE_CLK =PP3V3_TBTLC_RTR 8 35 36 37 MF MF
201 2 2 201
(TBT_SPI_CS_L) 1 S*
K5 TBT_EN_LC_PWR
JTAG/TEST PORT
V1 EN_LC_PWR OUT 37
20 IN JTAG_TBT_TDI TDI 1
R3698
TBTROM_WP_L 3 W*
JTAG_TBT_TMS AB3
20 IN TMS 10K
REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P IN 17 92 5%
7 HOLD* AA6
C TBTROM_HOLD_L
VSS THM
PAD
20
20
IN
OUT
JTAG_TBT_TCK
JTAG_TBT_TDO R2
TCK
TDO
REFCLK_100_IN_N AD21 PCIE_CLK100M_TBT_N IN 17 92
2
1/20W
MF
201
R3695
C
TBT_TEST_EN N4
CLOCKS
TEST_EN 806
4 9 XTAL_25_IN AA24 91 SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT 25 91
TBT_TEST_PWR_GOOD AB5 IN
TEST_PWR_GOOD AB23
XTAL_25_OUT TP_TBT_XTAL25OUT 7 1%
1/20W
Divides 3.3V to 1.8V
MF
1 1
R3625 R3629 95 35 7 DP_TBTSNK0_ML_P<3> E14
DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
201
0 0
5% 5% 95 35 7 DP_TBTSNK0_ML_N<3> D13
DPSNK0_3_N TMU_CLK_IN Y3 TBT_TMU_CLK_IN 37 36 35 8 =PP3V3_TBTLC_RTR
1/20W 1/20W
MF MF E16 NO STUFF
201 2 2 201 95 35 7 DP_TBTSNK0_ML_P<2> DPSNK0_2_P 1
95 35 7 DP_TBTSNK0_ML_N<2> D15
DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 7
R3697 R3699
1 1
R3696 R36801
DISPLAYPORT
100K 10K
SINK PORT 0
B15
10K 1K
E18 DPSRC_3_N TP_DP_TBTSRC_ML_CN<3> 7 5% 5% 5% 5%
95 35 7 DP_TBTSNK0_ML_P<1> DPSNK0_1_P 1/20W 1/20W 1/20W 1/20W
D17 A12 MF MF MF MF
DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2>
95 35 7 7
2 201 201 2 2 201 201 2
B13 TP_DP_TBTSRC_ML_CN<2>
DPSRC_2_N 7
DP_TBTSNK0_ML_P<0> E20 TBT_DDC_XBAR_EN_L
SOURCE PORT 0
95 35 7 DPSNK0_0_P 82 35
82 OUT DP_TBTSNK0_HPD U6
DPSNK0_HPD
DPSRC_0_N B9 TP_DP_TBTSRC_ML_CN<0> 7
5%
0 R36831 1
R3682
95 77 7 IN DP_TBTSNK0_ML_C_P<0> C3620 1 2 DP_TBTSNK0_ML_P<0> 7 35 95 C2 1/20W 10K 10K
10% 16V DPSRC_AUX_P TP_DP_TBTSRC_AUXCH_CP 7 MF 5% 5%
0.1UF X5R-CERM 0201
DP_TBTSNK1_ML_P<3> E6 D3 TP_DP_TBTSRC_AUXCH_CN 2 201 1/20W 1/20W
DP_TBTSNK0_ML_C_N<0> C3621 1 2 DP_TBTSNK0_ML_N<0> R3630 1 95 35 7 DPSNK1_3_P DPSRC_AUX_N 7 MF
201 2
MF
95 77 7 IN
10% 16V
7 35 95
100K 95 35 7 DP_TBTSNK1_ML_N<3> D5
DPSNK1_3_N 2 201
0.1UF V3 DP_TBTSRC_HPD
X5R-CERM0201 5% DPSRC_HPD_OD
1/20W E8
MF 95 35 7 DP_TBTSNK1_ML_P<2> DPSNK1_2_P
95 77 7 IN DP_TBTSNK0_ML_C_P<1> C3622 1 2 DP_TBTSNK0_ML_P<1> 7 35 95 201 D7
10% 16V
2
95 35 7 DP_TBTSNK1_ML_N<2> DPSNK1_2_N R3632 1
TBT_GO2SX_BIDIR
SINK PORT 1
0.1UF Y1
X5R-CERM 0201 GPIO_2/GO2SX BI 20
100K
95 77 7 IN DP_TBTSNK0_ML_C_N<1> C3623 1 2
10% 16V
DP_TBTSNK0_ML_N<1> 7 35 95 95 35 7 DP_TBTSNK1_ML_P<1> E10
DPSNK1_1_P (FORCE_PWR) GPIO_3 W2 TBT_PWR_EN IN 20 25 5%
1/20W
CR HPD INPUTS (S4) FORWARDED TO GMUX (S0)
0.1UF X5R-CERM 0201 95 35 7 DP_TBTSNK1_ML_N<1> D9
DPSNK1_1_N GPIO_4/WAKE_N_OD J4 =TBT_WAKE_L 18 42 MF 82 78 35 8 =PP3V3_S0_DPMUX_UC
B 95 77 7 IN DP_TBTSNK0_ML_C_P<2> C3624 1 2 DP_TBTSNK0_ML_P<2> 7 35 95
82 OUT
95 35 7 DP_TBTSNK1_ML_P<0> E12
DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2 TBT_CIO_PLUG_EVENT
OUT
OUT 20
201
2
NOSTUFF
U3610
B
10% 16V D11 GPIO_6/CIO_SDA_OD AB1 =I2C_TBTRTR_SDA BI 44 74LVC2G126GT/S500
0.1UF X5R-CERM 0201 R3631 1 95 35 7 DP_TBTSNK1_ML_N<0> DPSNK1_0_N 8 SOT833
GPIO_7/CIO_SCL_OD AC2 =I2C_TBTRTR_SCL IN 44
95 77 7 IN DP_TBTSNK0_ML_C_N<2> C3625 1 2 DP_TBTSNK0_ML_N<2> 7 35 95 100K VCC DP_TBTPB_HPD_BUF
10% 16V 5% 95 35 7 DP_TBTSNK1_AUXCH_P A4
DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* P3
(TBT_EN_CIO_PWR_L) TBT_PWR_REQ_L 19 85 35 IN DP_TBTPB_HPD 5
A Y
3
OUT 82
0.1UF X5R-CERM0201 1/20W
MF 95 35 7 DP_TBTSNK1_AUXCH_N B3
DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* M5 35 TBT_GPIO_9 GND
201 TBT_EN_CIO_PWR_L OUT 37 OE
95 77 7 IN DP_TBTSNK0_ML_C_P<3> C3626 1 2
DP_TBTSNK0_ML_P<3> 7 35 95
2
T5 GPIO_14 T3 TBT_GPIO_14 35 MAKE_BASE=TRUE 4
10% 16V DP_TBTSNK1_HPD DPSNK1_HPD 7
0.1UF X5R-CERM0201 GPIO_15 V5 TBT_DDC_XBAR_EN_L OUT 35 82
R3644
1
PORT0
PORT2
95 83 7 BI 7 35 95
10% 16V 93 84 7 IN TBT_A_D2R_P<0> G22
PA_CIO0_RX_P PB_CIO2_RX_P R22 TBT_B_D2R_P<0> IN 7 85 93 1/20W
0.1UF X5R-CERM0201 MF
93 84 7 IN TBT_A_D2R_N<0> E22
PA_CIO0_RX_N PB_CIO2_RX_N N22 TBT_B_D2R_N<0> IN 7 85 93 201
95 83 7 BI DP_TBTSNK0_AUXCH_C_N C3629 1 2 DP_TBTSNK0_AUXCH_N 7 35 95
10% 16V 82 78 35 8 =PP3V3_S0_DPMUX_UC
0.1UF X5R-CERM 0201 84 82 OUT TBT_A_CONFIG1_BUF K1
PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO P1 TBT_B_CONFIG1_BUF OUT 82 85
PORT1
PORT3
95 77 7 IN DP_TBTSNK1_ML_C_N<0> C3631 1 2 DP_TBTSNK1_ML_N<0> 7 35 95 93 84 7 IN TBT_A_D2R_P<1> L22
PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> IN 7 85 93 4
0.1UF
10% 16V
X5R-CERM0201 93 84 7 TBT_A_D2R_N<1> J22
PA_CIO1_RX_N PB_CIO3_RX_N U22 TBT_B_D2R_N<1> 7 85 93
1 R36451
IN IN
100K
DP_TBTSNK1_ML_C_P<1> C3632 1 2 DP_TBTSNK1_ML_P<1> TBT_A_LSTX N2 L6 TBT_B_LSTX NOSTUFF 5%
95 77 7 IN 7 35 95 84 OUT PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO OUT 85
R3643 1/20W
10% 16V MF
0.1UF X5R-CERM0201 84 IN TBT_A_LSRX J6
PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE G6 TBT_B_LSRX IN 85
1
1K
2
201
2
82 78 35 8 =PP3V3_S0_DPMUX_UC DP_TBTPA_HPD_BUF_EN
95 77 7 IN DP_TBTSNK1_ML_C_N<1> C3633 1 2 DP_TBTSNK1_ML_N<1> 7 35 95
10% 16V 5%
DP_TBTPA_ML_C_P<1> DP_TBTPB_ML_C_P<1>
PORTS
0.1UF A16 A20
X5R-CERM 0201 93 84 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT 85 93 1/20W
MF
DP_TBTPA_ML_C_N<1> B17 B21 DP_TBTPB_ML_C_N<1>
A 95 77 7 IN DP_TBTSNK1_ML_C_P<2> C3634
0.1UF
1 2
10% 16V
X5R-CERM 0201
DP_TBTSNK1_ML_P<2> 7 35 95
93 84
93 84
OUT
DP_TBTPA_ML_C_P<3> A18
PA_DPSRC_1_N
PA_DPSRC_3_P
PB_DPSRC_1_N
85 93
SYNC_MASTER=D2_KEPLER
201
SYNC_DATE=01/13/2012 A
OUT OUT PAGE TITLE
DP_TBTSNK1_ML_C_N<2> C3635 1 2 DP_TBTSNK1_ML_N<2> DP_TBTPA_ML_C_N<3> B19
PA_DPSRC_3_N PB_DPSRC_3_N B23 DP_TBTPB_ML_C_N<3>
95 77 7 IN
0.1UF
10% 16V
X5R-CERM0201
7 35 95 93 84 OUT OUT 85 93
Thunderbolt Host (1 of 2)
DRAWING NUMBER SIZE
DP_TBTPA_AUXCH_C_P F3
PA_AUX_P PB_AUX_P D1 DP_TBTPB_AUXCH_C_P
95 77 7 IN DP_TBTSNK1_ML_C_P<3> C3636 1 2
10% 16V
DP_TBTSNK1_ML_P<3> 7 35 95
93 84
93 84
BI
DP_TBTPA_AUXCH_C_N F1
PA_AUX_N PB_AUX_N E2 DP_TBTPB_AUXCH_C_N
BI 85 93
10% 16V
DP_TBTSNK1_ML_N<3> 7 35 95 84 35 IN DP_TBTPA_HPD H1
PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 35 85 4.18.0
0.1UF X5R-CERM 0201
TBT_A_HV_EN G2 M1 TBT_B_HV_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH
84 37 35 OUT GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 OUT 35 37 85
THE INFORMATION CONTAINED HEREIN IS THE
84 OUT TBT_A_CIO_SEL M3
GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 L2 TBT_B_CIO_SEL OUT 85 PROPRIETARY PROPERTY OF APPLE INC.
95 83 7 BI DP_TBTSNK1_AUXCH_C_P C3638 1 2 DP_TBTSNK1_AUXCH_P 7 35 95 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 16V TBT_A_DP_PWRDN H3
GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 L4 TBT_B_DP_PWRDN
0.1UF X5R-CERM 0201
84 35 OUT OUT 35 85
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 132
95 83 7 BI DP_TBTSNK1_AUXCH_C_N C3639 1 2 DP_TBTSNK1_AUXCH_N 7 35 95
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
10% 16V For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF X5R-CERM 0201 IV ALL RIGHTS RESERVED 35 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP1V05_TBTLC_RTR
???? mW (Single Port)
250 mW (Dual Port) =PP1V05_TBTCIO_RTR 8
CRITICAL
D EDP: 1600 mA C3700
10UF
20%
1 1
C3710
1.0UF
20%
1
C3711
1.0UF
20%
1
C3712
1.0UF
20%
1
C3713
1.0UF
20%
1
C3714
1.0UF
20% J10 OMIT_TABLE K11
???? mW (Single-Port)
2700 mW (Dual-Port)
D
6.3V 10V 10V 10V 10V 10V VCC1P0_ON VCC1P0
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM J12 U3600 K15 EDP: 1100 mA
0402-1 0201-1 0201-1 0201-1 0201-1 0201-1 VCC1P0_ON VCC1P0
J14
VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10
C3740 1
C3741 1
C3742 1
C3743 1
C3744 1
C3745 1 1
C3705
J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
J8 M11 10V 10V 10V 10V 10V 10V 6.3V
VCC1P0_ON VCC1P0 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 CERM-X5R
K17 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
VCC1P0_ON VCC1P0
C3701 1 1 C3715 1 C3716 1 C3717 T15 N10
10UF 1.0UF 1.0UF 1.0UF VCC1P0_ON VCC1P0
20% 20% 20% 20% U14 N14
6.3V 10V 10V 10V VCC1P0_ON VCC1P0
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM V7 P11
0402-1 0201-1 0201-1 0201-1 VCC1P0_ON VCC1P0
W8 P15
VCC1P0_ON VCC1P0
R10
G10 VCC1P0
VCC1P0_PE
VCC
R14
G12 VCC1P0
VCC1P0_PE T11
G14 VCC1P0
VCC1P0_PE U10
G16 VCC1P0
VCC1P0_PE V11
G18 VCC1P0
VCC1P0_PE W10
=PP3V3_TBTLC_RTR 8 35 37
H19 VCC1P0
VCC1P0_PE ??? mW (Single-Port)
K19
VCC1P0_PE M7 250 mW (Dual-Port)
M19 VCC3P3
VCC1P0_PE P7 EDP: 240 mA
P19 VCC3P3
VCC1P0_PE T7
T19 VCC3P3 C3770 1
C3771 1
C3772 1
C3773 1
C3774 1 1
C3760
VCC1P0_PE 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
V15 L18 20% 20% 20% 20% 20% 20%
VCC1P0_PE VCC3P3_CIO 10V 10V 10V 10V 10V 6.3V
V19 N18 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 CERM-X5R
VCC1P0_PE VCC3P3_CIO 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
W12 R18
VCC1P0_PE VCC3P3_CIO
W14
VCC1P0_PE H11
VCC3P3_DP
H13
C G8
H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP H15 C
H17
VCC3P3_DP
AD1 H7
VSS VCC3P3_DPAUX
K13 PP3V3_S4_TBT
VSS
K9
VSS
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
R3790
L12 =PP3V3_S4_TBT 1
0 2 =PP3V3_S4_TBT_R
VSS 37 35 8
L16 K7 5%
VSS VCC3P3_POC EDP: 10 mA
1/16W
L8 MF-LF
VSS
402
M13 C22
VSS VSSPE C3790 1
M17
VSS VSSPE C24 1.0UF
20%
M9 C4 10V
VSS VSSPE X5R-CERM 2
N12 C6 0201-1
VSS VSSPE
N16 C8
VSS VSSPE
N8 D21
VSS VSSPE
P13 D23
VSS VSSPE
P17 E4
VSS VSSPE
P9 F11
VSS VSSPE
R12 F13
VSS VSSPE
R16 F15
VSS VSSPE
R8 F17
VSS VSSPE
T13 F19
VSS VSSPE
T17 F21
VSS VSSPE
T9 F23
VSS VSSPE
U12 F5
VSS VSSPE
GND
U16 F7
VSS VSSPE
B U8
V9
VSS
VSS
VSSPE
VSSPE
F9
G20
B
H21
VSSPE
A2 H23
VSSPE VSSPE
A24 J18
VSSPE VSSPE
AA14 J20
VSSPE VSSPE
AA20 K21
VSSPE VSSPE
AA22 K23
VSSPE VSSPE
AA8 L20
VSSPE VSSPE
AB11 M21
VSSPE VSSPE
AB17 M23
VSSPE VSSPE
AB7 N20
VSSPE VSSPE
AC10 P21
VSSPE VSSPE
AC12 P23
VSSPE VSSPE
AC14 R20
VSSPE VSSPE
AC16 T21
VSSPE VSSPE
AC18 T23
VSSPE VSSPE
AC20 U18
VSSPE VSSPE
AC22 V13
VSSPE VSSPE
AC4 V17
VSSPE VSSPE
AC6 V21
VSSPE VSSPE
AC8 V23
VSSPE VSSPE
B1 Y11
VSSPE VSSPE
B7 Y13
VSSPE VSSPE
C10 Y15
VSSPE VSSPE
C12 Y17
VSSPE VSSPE
A C14
C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19
2 3
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input) 8 1 2
Changes required MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
D
4
- =PP1V05_TBTLC_FET (1.05V FET Output) MIN_NECK_WIDTH=0.25 mm TBTBST:Y TBTBST:Y PIMB063T-SM MIN_NECK_WIDTH=0.25 mm
for 2S. SWITCH_NODE=TRUE
Signal aliases required by this page:
TBTBST:Y TBTBST:Y Voltage not specified here,
add property on another page.
C3860 1 C3861 1 DIDT=TRUE
10UF 10UF
R38801 C3880 TBTBST_SNS1
D
G
- =TBT_CLKREQ_L 1 TBTBST:Y 20% 20%
D - =TBT_RESET_L
470K
5%
1/16W 10%
0.1UF
R3891 1
25V
X5R-CERM 2
0603
25V
X5R-CERM 2
0603
TBTBST:Y
R38891 1 2
1
25V 200K CRITICAL
27
8
9
20
21
38
MF-LF 2 X5R
BOM options provided by this page: 402 2 402 1% 0
1/16W VIN 5% TBTBST:Y
TBTBST:Y - Stuffs 15V boost circuitry. MF-LF SW 1/20W
TBTBST_PWREN_DIV_L 402 2 CRITICAL MF
201 2
D3895
TBTBST:Y <R1> TBTBST_EN_UVLO 25 EN/UVLO TBTBST:Y PDS540XF
SNS1 6 PWRDI5
1 TBTBST_SNS2 3
R3881 U3890 3
330K LT3957 SNS2
5%
1/16W TBTBST_INTVCC 28 INTVCC QFN
XW3895
SM
MF-LF 2 1
402 2 PLACE_NEAR=C3895.1:2 mm
30 VC
1 TBTBST_VSNS
TBTBST_PWREN_L TBTBST_VC 2 TBTBST:Y
TBTBST:Y
TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y NC 10
NC TBTBST:Y R38951
Q3805 D 6 Q3805 D 3 C3890 1 C3891 1 C3892 1 1 C3887 R38931 TBTBST_RT 33 RT 35 1 C3888 137K
SSM6N37FEAPE SSM6N37FEAPE 2.2UF 2.2UF 2.2UF 68PF 49.9K 36 10PF 1% =PP15V_TBT_REG 8 9
20% 20% 20% 5% 1% 5% 1/16W
SOT563 SOT563 1/16W MF-LF
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
50V
2 COG-CERM MF-LF
402 2 TBTBST_SS 32 SS
50V
2 C0G-CERM 402 2
TBTBST:Y NO STUFF
Vout = 15.47V
402 402 402 0402 0402 <Ra> 1 C3895 1 C3897 Max Current = 2A?
2 G S 1 5 G S 4 TBTBST_VC_RC FBX 31 TBTBST_FBX 10UF 10UF
TBTBST:Y TBTBST:Y
TBTBST:Y
34 SYNC
NO STUFF
TBTBST:Y 10%
2 25V
10%
2 25V
Freq = 300KHz
1 1 1 X5R X5R
R3892 1 C3893 R3894 1 C3894 1 C3889 R3896 1206-2 805
84 35 IN TBT_A_HV_EN 73.2K 0.0033UF 28.7K 0.33UF 100PF 15.8K TBTBST:Y
1% 1% 10%
SGND GND 5% 1% TBTBST:Y
TBT_B_HV_EN 1/16W 10%
50V 1/16W 6.3V 50V 1/16W
MF-LF C3896 1 1 C3899
23
24
37
12
13
14
15
16
17
85 35 IN MF-LF 2 X7R-CERM MF-LF 2 CERM-X5R 2 CERM
20%
4
2 402 0402 402 2 402 402 402 2 0.001UF
25V
<R2> GND_TBTBST_SGND <Rb> POLY-TANT 2
10%
2 50V
MIN_LINE_WIDTH=0.5 mm X7R-CERM
0402
UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN_NECK_WIDTH=0.25 mm CASE-D3L
VOLTAGE=0V
UVLO(rising) = UVLO(falling) + (2uA * R1) 33UF-0.06OHM
SGND shorted to
UVLO = 4.55V (falling), 4.95 (rising) Vout = 1.6V * (1 + Ra / Rb) C
C GND inside package,
no XW necessary.
Supervisor & CLKREQ# Isolation
8 =PP3V3_S0_TBTPWRCTL
TBTBST:Y
6 D
C3800 1 =PP3V3_TBTLC_RTR
Q3888 TBTBST:Y
8 35 36 37
SSM6N37FEAPE 1
R3888
0.1UF SOT563
10%
16V 1
330K
CRITICAL R3807 5%
1
X5R-CERM 2
0201 1/16W
1 VDD 100K MF-LF
Q3840 R3840 5%
1 S G 2 Max Vgs: 10V 2 402
U3800 1/20W
G 1
SSM3K15FV 10K MF
5%
SLG4AP016V 2
201 TBTBST_SHDN_DIV
SOD-VESM-HF 1/20W
MF TDFN PP1V05_TBTLC 8 TBTBST:Y
2 201 1 TBTBST:Y
+ SENSE
2
R3887 3 D Q3888
D
SSM6N37FEAPE
2
5%
1/16W SOT563
MF-LF
Platform (PCIe) Reset DLY
2 402
RESET* 4 TBT_PCIE_RESET_L OUT 35
=TBT_RESET_L 3 MR* G 5
25 IN
DLY = 60 ms +/- 20% 4 S
SMC_DELAYED_PWRGD IN 41 42 70
6 EN
=TBT_CLKREQ_L IN 35
17 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
MAKE_BASE=TRUE
Pull-ups provided by SB page. THRM
GND PAD
5
1
U3810 Pull-up: R3610
=PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBTLC_FET VDD =PP3V3_S0_PCH_GPIO
8 8 8 17 18 19 20 25
CSP
A2 A1 Max Current = 2A (85C) 2 SENSE
U3830 RESET* 6 TBT_PWR_ON_POC_RST_L OUT 35
VIN VOUT 1
R3811
B2 B1
TPS3808 R3830
36.5K2
CRITICAL U3810 TBTPOCRST_CT 3 CT QFN MR* 4 TBTPOCRST_MR_L Q3825 5%
100K
THRM
G 5
C3810 1 1 TBT_EN_LC_3V3 C2 ON GND PAD SSM6N37FEAPE 1/20W
Part TPS22924C MF
1UF
20%
1%
C3811 1
GND 1 C3831 C3830 1 SOT563 2 201
7
1/20W
0.0047UF 0.1UF
C1
6.3V
X5R 2 MF
201 1UF Type Load Switch 10% 10% TPS3808G25
S
0201 10%
6.3V 2 25V
CERM
25V 2
X5R Vt = 2.33V +/- 2% TBT_SW_RESET_L IN 20
CERM 2 R(on) 18.3 mOhm Typ
3
0402 402
4
402 Delay = 27.3ms
@ 2.5V 24 mOhm Max
TBT_EN_LC_ISOL
1 C3825
330PF
10%
16V
R38161 2 X7R-CERM
0201
0
5%
1/20W
1.05V TBT "CIO" Switch
MF 99 37 8 =PP1V05_S0_P1V05TBTFET
201 2
=PP3V3_TBTLC_RTR
TBT_EN_LC_1V05
1.05V TBT "LC" Switch
37 36 35 8
U3820
1
TPS22920 =PP1V05_TBTCIO_FET 8
99 37 8 =PP1V05_S0_P1V05TBTFET U3815 R3820 A2
CSP
A1 Max Current = 4A (85C)
TPS22924 =PP1V05_TBTLC_FET 8 100K B2 B1
5% VIN VOUT
A2
CSP
A1 Max Current = 2A (85C)
1/20W
MF C2 C1 U3820
A B2 VIN
CRITICAL
VOUT B1
U3815
2 201
TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
C3815 1 C2 ON GND Type Load Switch
1UF GND Part TPS22924C Thunderbolt Power Support
D1
1 C3820
20%
Q3825 D 6 R(on) 8 mOhm Typ DRAWING NUMBER SIZE
1UF
C1
6.3V
2 Type Load Switch
X5R
0201
SSM6N37FEAPE
SOT563
20%
6.3V
2 X5R
@ 1.05V 11.5 mOhm Max
Apple Inc. 051-9589 D
R(on) 20.3 mOhm Typ 0201 REVISION
R
NOSTUFF @ 1.0V 28.6 mOhm Max 4.18.0
C3816 1 2 G S 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1UF THE INFORMATION CONTAINED HEREIN IS THE
10% PROPRIETARY PROPERTY OF APPLE INC.
6.3V
CERM 2 C3816 must be 10% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 RC guarantees minimum 5ms to reach 0.5V
35 TBT_EN_CIO_PWR_L
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 132
IN
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 37 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
J4400
20525-130E-01
F-RT-SM
SIGNAL_MODEL=EMPTY 31
TP 1
BP4405 BEAD-PROBE SM
SIGNAL_MODEL=EMPTY 1
TP 1 91 26 7 BI USB_EXTB_P
BP4406 BEAD-PROBE SM 2
91 26 7 BI USB_EXTB_N
SIGNAL_MODEL=EMPTY GND_VOID=TRUE GND_VOID=TRUE 3
TP 1 C4401 0.1UF
BP4401 BEAD-PROBE SM 91 19 IN USB3_EXTB_TX_P 1 2 97 7 USB3_EXTB_TX_C_P GND_VOID=TRUE 4
TP 1 C4402 0.1UF
BP4402 BEAD-PROBE SM 91 19 IN USB3_EXTB_TX_N 1 2 X5R-CERM 0201 10% 16V 97 7 USB3_EXTB_TX_C_N GND_VOID=TRUE 5
33
34 34
35
36
37
38
39
40
41
B B
32
518S0829
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
RIO CONNECTOR
DRAWING NUMBER SIZE
D D
CRITICAL
PLACE_NEAR=J4501.9:3mm R4599
CRITICAL 0.005
1%
1W
L4500 MF
0612
FERR-26-OHM-6A PP3V3_S0_SSD_R 2 1 =PP3V3_S0_SSD 8
MIN_LINE_WIDTH=0.6mm
PP3V3_S0_SSD_FLT MIN_NECK_WIDTH=0.25mm 4 3
MIN_LINE_WIDTH=0.6mm VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25mm 0603
VOLTAGE=3.3V ISNS_SSD_P OUT 97 99
1
C4501 1
C4502 ISNS_SSD_N OUT 97 99
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
8 =PP3V3_S0_SATAMUX
1
C4505 1
C4514 1
C4519
514S0393 0.1UF 0.1UF 0.01UF
C CRITICAL 2
20%
10V
CERM 2
20%
10V
CERM 2
20%
16V
X7R-CERM
C
402 402 0402
J4501 Per PCIe spec, only TX side should have AC cap
SSD-J5 1 PLACE_NEAR=U4510.10:2 mm
F-RT-SM R4505 PLACE_NEAR=U4510.6:2 mm
GND_VOID=TRUE 100K
1 GND_VOID=TRUE 5%
GND_VOID=TRUE 1/16W
2 GND_VOID=TRUE MF-LF GND_VOID=TRUE
2 402 GND_VOID=TRUE
GND_VOID=TRUE
3
R4526
VDD 10
GND_VOID=TRUE
1 2 0
VDD 1
VDD 6
92 PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_P<1> 9 92
4 GND_VOID=TRUE 5% 1/20W MF 201 OUT
SIGNAL_MODEL=EMPTY
5 GND_VOID=TRUE 92 PCIE_SSD_D2R_C_N<1> R4525 1 2 0 PCIE_SSD_D2R_N<1>
OUT 9 92 92 PCIE_SSD_D2R_MUX_OUT_P R4518 1 2 0 PCIE_SSD_D2R_P<0>
OUT 9 92
1 TP
SM BEAD-PROBE BP4501
5% 1/20W MF 201 5% 1/20W MF 201
6
SIGNAL_MODEL=EMPTY
7 GND_VOID=TRUE 91 SATA_SSD_D2R_P U4510 92 PCIE_SSD_D2R_MUX_OUT_N R4517 1 2 0 PCIE_SSD_D2R_N<0> 9 92
1 TP
SM BEAD-PROBE BP4502
8 GND_VOID=TRUE 91 SATA_SSD_D2R_N CBTL02043ABQ 5% 1/20W MF 201 OUT
9 3 VQFN B0_P 19
92 PCIE_SSD_R2D_P<1> C4521 0.1UF 1 2 PCIE_SSD_R2D_C_P<1>
A0_P
0.1UF
10 GND_VOID=TRUE IN 9 92
4 A0_N B0_N 18 92 PCIE_SSD_R2D_MUX_IN_P C4513 1 2 PCIE_SSD_R2D_C_P<0>
IN 9 92
X5R-CERM 10% 16V 0201
11 GND_VOID=TRUE 92 PCIE_SSD_R2D_N<1> C4520 0.1UF 1 2 PCIE_SSD_R2D_C_N<1> 9 92
10% 16V 0201
IN 7
12 X5R-CERM 10% 16V 0201
A1_P B1_P 17 X5R-CERM
8 CRITICAL C4512 0.1UF
13 GND_VOID=TRUE A1_N B1_N 16 92 PCIE_SSD_R2D_MUX_IN_N 1 2 PCIE_SSD_R2D_C_N<0>
IN 9 92
91 SATA_SSD_R2D_P
10% 16V 0201
14 GND_VOID=TRUE 91 SATA_SSD_R2D_N C0_P 15 X5R-CERM
15 9
SEL C0_N 14 GND_VOID=TRUE
16 GND_VOID=TRUE
PCIE_CLK100M_SSD_P IN 17 92 2 GND_VOID=TRUE
17
SATAMUX_EN_L XSD C1_P 13 GND_VOID=TRUE
PCIE_CLK100M_SSD_N IN 17 92 SIGNAL_MODEL=EMPTY
18 C1_N 12 C4516 0.01UF 1 2 1 TP
SM BEAD-PROBE
91 SATA_SSD_D2R_MUX_OUT_P SATA_HDD_D2R_P
OUT 17 91 BP4503
THRM
PAD
VSS
VSS
VSS
10% 25V X7R 402
1
19
R4510 C4515 0.01UF 1 2
SSD_CLKREQ_L IN 17 10K 91 SATA_SSD_D2R_MUX_OUT_N SATA_HDD_D2R_N
OUT 17 91
5
11
20
21
20 5% 10% 25V X7R 402
SSD_RESET_L 25 1/20W
B 21
22
SATA_PCIE_SEL
IN
MF
2 201
C4511 0.01UF 1 2
B
SMC_OOB1_RX_L OUT 91 SATA_SSD_R2D_MUX_IN_P SATA_HDD_R2D_C_P
IN 17 91
23 SMC_OOB1_TX_L IN
R4520 10% 25V X7R 402
24 SSD_P3V3S0_EN 1
0 2 =P3V3S0_EN IN 69 70
C4510 0.01UF 1 2
91 SATA_SSD_R2D_MUX_IN_N SATA_HDD_R2D_C_N 17 91
25 5% IN
1/20W 10% 25V X7R 402
26 MF
201
27
28
29 353S3361
30
31
32
33
34
35
SSD CONNECTOR
DRAWING NUMBER SIZE
D D
USB Port Power Switch
Left USB Port A
8 =PP5V_S3_LTUSB
CRITICAL
70 41 38 34 27 18 7
PM_SLP_S4_L CRITICAL
U4600 L4605
TPS2557DRB We can add protection to 5V if we want, but leaving NC for now
1 FERR-120-OHM-3A
R4690 SON
2 IN_0 Place L4605 and L4615 at connector pin
5.1K OUT1 6 PP5V_S3_LTUSB_A_ILIM 1 2 PP5V_S3_LTUSB_A_F
5% MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
1/16W 3 IN_1 OUT2 7 MIN_NECK_WIDTH=0.25 mm 0603 MIN_NECK_WIDTH=0.25 mm
MF-LF VOLTAGE=5V VOLTAGE=5V
402 8 FAULT* C4605 1
2
24 OUT USB_EXTA_OC_L ILIM 5 USB_ILIM 0.01UF 514-0804
20% CRITICAL CRITICAL
4 EN
USB_PWR_EN R46011 16V
X7R-CERM 2
L4600 J4600
THRM 22.1K 0402 90-OHM-50MA
USB3.0-J5
1% TCM0605-1
GND PAD 1/20W SYM_VER-1
F-RT-TH
MF 1 4
USB_EXTA_MUXED_N
9
201 2 91
1
CRITICAL C4695 1
VBUS
C4690 1 1 C4691 USB_ILIM_R 10UF 2
C4692 1
C4696 1
10UF 0.1UF 20%
91 USB_LT1_N D-
0.47UF 6.3V 3
10%
220UF-35MOHM
20%
20%
6.3V
2 2
20%
10V R46001 X5R 2 91 USB_EXTA_MUXED_P 2 3 91 USB_LT1_P
4
D+
10V
X5R 2 6.3V
POLY-TANT
2
X5R
603
CERM
402
22.1K 603
GND
0402 1% 5
CASE-B2-SM1 1/16W 97 USB3_EXTA_RX_RC_N
MF-LF 2 5 3 4 STDA_SSRX-
USB3_EXTA_RX_RC_P 6
NC
IO
NC
IO
402 2 97
STDA_SSRX+
6 VBUS 7
GND_DRAIN
97 USB3_EXTA_TX_C_N 8
1 GND STDA_SSTX-
CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX 97 USB3_EXTA_TX_C_P 9
STDA_SSTX+
C 10
11
SHLD C
D4600 SHLD
USB/SMC Debug Mux RCLAMP0502N
SLP1210N6
12
13
SHLD
SHLD
CRITICAL
14
15
8 =PP3V42_G3H_SMCUSBMUX
16
SMC_DEBUG_YES 17
1 SIGNAL_MODEL=EMPTY
SMC_DEBUG_YES R4650 18
C4650 1 10K SIGNAL_MODEL=EMPTY BEAD-PROBE
BP4604
9
5%
0.1UF
20%
1/16W BEAD-PROBE
10V VCC MF-LF SM
CERM 2 2 402 BP4602
42 41 IN SMC_DEBUGPRT_RX_L 402 5 M+ Y+ 1 12 1 2 R4613 SM
SMC_DEBUGPRT_TX_L 4 M- Y- 2
42 41 OUT U4650 1/20W 1% MF 201
1
PI3USB102ZLE GND_VOID=TRUE
TQFN
91 19 BI USB_EXTA_P 7
D+ NO_TEST=TRUE 15PF 1 2 C4613
1
6
CRITICAL
91 19 BI USB_EXTA_N D- 91 19 OUT USB3_EXTA_RX_N
5% 25V NP0-CERM 0201 NO_TEST=TRUE
SMC_DEBUG_YES GND_VOID=TRUE
8 OE* SEL 10 SMC_DEBUGPRT_EN_L IN 41
91 19 OUT USB3_EXTA_RX_P 12 1 2 R4612 NO_TEST=TRUE
GND SEL=0 Choose SMC
NO_TEST=TRUE
SEL=1 Choose USB 1/20W 1% MF 201
3
GND_VOID=TRUE
CRITICAL CRITICAL
15PF C4612 2 2
1 2 D4610 D4611
5% 25V NP0-CERM 0201 ESD0P2RF-02LS ESD0P2RF-02LS
SMC_DEBUG_NO GND_VOID=TRUE TSSLP-2-1 TSSLP-2-1
R4651 1 1
B 1
0 2 B
5% SMC_DEBUG_NO
1/20W
MF
201 R4652
1
0 2
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
BEAD-PROBE BEAD-PROBE
BP4606 BP4605
SM SM
GND_VOID=TRUE
NO_TEST=TRUE
C4610 0.1UF 1 2 NO_TEST=TRUE
USB3_EXTA_TX_N
1
1
91 19 IN
10% 16V 0201
X5R-CERM
C4611 0.1UF 1 2
91 19 IN USB3_EXTA_TX_P
1
1
10% 16V 0201
NO_TEST=TRUE X5R-CERM NO_TEST=TRUE
GND_VOID=TRUE CRITICAL 2 2
CRITICAL
SM SM
D4612 D4613
ESD0P2RF-02LS ESD0P2RF-02LS
BP4608 BP4607 TSSLP-2-1 TSSLP-2-1
BEAD-PROBE BEAD-PROBE
1 1
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
L4901
78 42 8 =PP3V3_S5_SMC 30-OHM-1.7A
1 2 PP3V3_S5_SMC_VDDA
MIN_LINE_WIDTH=0.25 MM
0402 MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V 1 C4901
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906 0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1
R4902 20%
10V
20%
10V
X5R-CERM 2 2
20%
10V
2
20%
10V
2
20%
10V
2
20%
10V 1M U4900 2 CERM
D
D 0603-1
CERM
402
CERM
402
CERM
402
CERM
402 5%
1/20W
MF
LM4FSXAH5BB
BGA
402
201
2 (2 OF 2)
61 43 42 7 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 7 42 43
IN
OMIT_TABLE A10
SWDIO/TMS SMC_TMS 7 42 43
1 C4907 1 C4908 1 C4909
42 34 7 WIFI_EVENT_L (OD) B11 PK4/RTCCLK SWO/TDO A11 SMC_TDO 7 42 43
0.1UF 0.1UF 0.1UF BI
U4900 2
20%
10V
2
20%
10V
2
20%
10V
SMC_WAKE_L N13 WAKE* TDI B10 SMC_TDI 7 42 43
LM4FSXAH5BB CERM
402
CERM
402
CERM
402 7 NC_SMC_HIB_L M12 HIB*
BGA NC A2
92 82 43 17 7 BI LPC_AD<0> B13 LPC0AD0 (1 OF 2) AIN00 E2 SMC_ADC0 IN 42
NC
42 SMC_CLK32K M10 XOSC0
LPC_AD<1> A13 E1 SMC_ADC1 IN
92 82 43 17 7 BI LPC0AD1 AIN01 IN 42
N10
7 NC_SMC_XOSC1 XOSC1
92 82 43 17 7 BI LPC_AD<2> C12 LPC0AD2 OMIT_TABLE AIN02 F2 SMC_ADC2 IN 42
VDDA D3
92 82 43 17 7 LPC_AD<3> D11 LPC0AD3 AIN03 F1 SMC_ADC3 42
BI IN SMC_EXTAL G12
H12 B3 42 OSC0
92 25 IN LPC_CLK33M_SMC LPC0CLK AIN04 SMC_ADC4 IN 42 G13
42 SMC_XTAL OSC1 VREFA+ D2 PP3V3_S5_AVREF_SMC 7 42
92 82 43 17 7 IN LPC_FRAME_L D12 LPC0FRAME* AIN05 A3 SMC_ADC5 IN 42
VREFA- D1
25 IN SMC_LRESET_L C13 LPC0RESET* AIN06 B4 SMC_ADC6 IN 42
K12 VBAT
XW4900
SM
43 17 7 BI LPC_SERIRQ (OD) H13 LPC0SERIRQ AIN07 A4 SMC_ADC7 IN 42
99 46 45 42 C3 GND_SMC_AVSS 2 1
43 18 7 OUT PM_CLKRUN_L (OD) G11 LPC0CLKRUN* AIN08 B5 SMC_ADC8 IN 42
D7 GNDA E3
43 25 18 7 IN LPC_PWRDWN_L F13 LPC0PD* AIN09 A5 SMC_ADC9 IN 42 PLACE_NEAR=U4900.A1:4MM
E6
20 SMC_RUNTIME_SCI_L F12 LPC0SCI* AIN10 B6 SMC_ADC10 42
OUT IN E8 A1
20 OUT SMC_WAKE_SCI_L B12 PK5 AIN11 A6 SMC_ADC11 IN 42
E9 C7
AIN12 C1 SMC_ADC12 42
IN F10 VDD D9
94 44 SMBUS_SMC_0_S0_SCL (OD) E10 I2C0SCL AIN13 C2 SMC_ADC13 42
BI IN J7 E5
94 44 BI SMBUS_SMC_0_S0_SDA (OD) D13 I2C0SDA AIN14 B1 SMC_ADC14 IN 42
J9 F9
1 C4920 1 C4921
94 44 SMBUS_SMC_1_S0_SCL (OD) M4 I2C1SCL AIN15 B2 SMC_ADC15 42
0.01UF 1UF
BI IN J10 H5 10% 10%
94 44 SMBUS_SMC_1_S0_SDA (OD) N2 I2C1SDA AIN16 G2 SMC_ADC16 42 2 10V 6.3V
2 CERM
BI IN H9 X5R-CERM
SMBUS_SMC_2_S3_SCL N8 G1 SMC_ADC17 GND 0201 402
94 44 7 BI (OD) I2C2SCL AIN17 IN 42
J1 J5
C 94 44 7
94 44
BI SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
(OD)
(OD)
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
SMC_ADC18
SMC_ADC19
IN 42
42 NO STUFF
42 PP1V2_S5_SMC_VDDC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
J6 J8 C
BI IN 1 1 1 1 1 1 1 1 K13 VDDC J11
SMBUS_SMC_3_SDA K8 B7 SMC_ADC20
C4910 C4911 C4912 C4913 C4914 C4915 C4916 C4917
94 44 BI (OD) I2C3SDA AIN20 IN 42
1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
42 SMBUS_SMC_4_ASF_SCL (OD) N7 I2C4SCL AIN21 A7 SMC_ADC21 42
10% 10% 10% 20% 20% 20% 20% 20%
BI IN 25V 25V 25V 10V 10V 10V 10V 10V
M7 B8 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
42 BI SMBUS_SMC_4_ASF_SDA (OD) I2C4SDA AIN22 SMC_ADC22 IN 42
402 402 402 402 402 402 402 402
44 7 SMBUS_SMC_5_G3_SCL (OD) N4 I2C5SCL AIN23 A8 SMC_ADC23 42
BI IN
44 7 SMBUS_SMC_5_G3_SDA (OD) N3 I2C5SDA
BI
C0- K2 CPU_PROCHOT_L 11 42 65 89
IN
48 SMC_FAN_0_CTL H11 PM6/FAN0PWM0 C0+ K1 SMC_VCCIO_CPU_DIV2 42
OUT
48 SMC_FAN_0_TACH L13 PM7/FAN0TACH0 C1- L2 SMC_S5_PWRGD_VIN 42
IN
48 OUT SMC_FAN_1_CTL C11 PK6/FAN0PWM1 PC5/C1+ L1 SPI_DESCRIPTOR_OVERRIDE_L OUT 25 42
42
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
SPI_SMC_CLK
SPI_SMC_CS_L
OUT
OUT
42
42
B
42 SMC_PME_S4_DARK_L J12 PP3/IRQ119 PF4 L9 S5_PWRGD 70
IN IN
70 42 SMC_S4_WAKESRC_EN J13 PP4/IRQ120 PF5 K9 PM_PCH_SYS_PWROK 18 24 70
OUT IN
L5 PP5/IRQ121
NC
D8 PP6/IRQ122 WT0CCP0/PG4 K7 SMC_DEBUGPRT_EN_L
NC OUT 40
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
SMC
DRAWING NUMBER SIZE
3
C5020 1 41 SMC_ADC1 SMC_CPU_ISENSE 46
9
402
0 C5025 1 1
C5026
41 46
2 2 402
5% 0.01UF 1000PF MAKE_BASE=TRUE
SSM6N15FEAPE
1/10W
10% 10uF 0.01UF 5% 41 SMC_ADC8 SMC_CPU_HI_ISENSE 46 SOT563
16V 20% 10% 25V
MF-LF
603
X7R-CERM 2 6.3V
2 2
16V NP0-C0G 2 MAKE_BASE=TRUE
2 0402 X5R X7R-CERM 402 SMC_ADC9 SMC_OTHER_HI_ISENSE
603 0402 41 46
SILK_PART=SMC_RST MAKE_BASE=TRUE
S G 2 R5034
GND_SMC_AVSS
41 SMC_ADC10 SMC_P1V5MEM_ISENSE 45 1
CPU_PECI_R 1
43 2 CPU_PECI
PLACEMENT_NOTE=Place R5001 on BOTTOM side 41 45 46 99 MAKE_BASE=TRUE 41 OUT BI 11 20 89
MIN_LINE_WIDTH=0.4 mm ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD SMC_PROCHOT IN 41
MIN_NECK_WIDTH=0.1 mm 41 SMC_ADC11 SMC_CPUVCCIO_ISENSE 45 5% From/To CPU/PCH
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V MAKE_BASE=TRUE To SMC 1/16W
MF-LF
Used on mobiles to support SMC reset via keyboard. 41 SMC_ADC12 SMC_GFX_VSENSE 45 402
MAKE_BASE=TRUE 20 OUT PM_THRMTRIP_L_R
NOTE: Internal pull-ups are to VIN, not V+. 41 SMC_ADC13 SMC_CPU_SA_ISENSE 45
MAKE_BASE=TRUE
41 PP1V2_S5_SMC_VDDC 41 SMC_ADC14 SMC_GPU_CORE_VSENSE 45
3 D Q5059
MAKE_BASE=TRUE
SSM6N15FEAPE
1SMC_PACKAGE:ENG 41 SMC_ADC15 SMC_GPU_CORE_ISENSE 45 SOT563
R5099 MAKE_BASE=TRUE
SMC_ADC17
SMC_LCDBKLT_VSENSE
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
99
4
S G 5
SMC12 SPI SUPPORT
MF-LF 41 99
MAKE_BASE=TRUE
2 402
SMC_ONOFF_L OUT 41 42 49 41 SMC_ADC18 SMC_CPU_GFX_ISENSE 46 SMC_THRMTRIP IN 41 42
SMC_ADC23
OMIT OMIT
42 41 MAKE_BASE=TRUE R5021
12
C PLACE_SIDE=TOP
R5016
0
1 1
R5015
0 PLACE_SIDE=BOTTOM
41
41
SMC_ADC19
SMC_ADC20
SMC_GPU_P1V35_ISENSE
MAKE_BASE=TRUE
SMC_CPU_SA_VSENSE
99
99
41 OUT SPI_SMC_MISO 1
5%
2 SPI_MLB_MISO IN 43 52 C
3 D Q5057
5%
1/10W
5%
1/10W ENG PACKAGE REQUIRES 1.2V ON SMC_ADC23 PIN MAKE_BASE=TRUE
SSM6N15FEAPE
R5022 1/16W
MF-LF
MF-LF MF-LF 41 SMC_ADC21 SMC_PCH_CORE_ISENSE 99
1
33 2
402
603
2 2
603 MAKE_BASE=TRUE SOT563 41 IN SPI_SMC_MOSI SPI_MLB_MOSI OUT 43 52
SMC_PACKAGE:PROD PLACE_NEAR=U6100.5:1MM
SMC_ADC22 SMC_X29_ISENSE
SILK_PART=PWR_BTN SILK_PART=PWR_BTN 41
MAKE_BASE=TRUE
99
R5013 5%
1/16W R5023
42 8 =PPVCCIO_S0_SMC
SMC_ADC23
0 MF-LF 33
42 41 SMC_TBT_ISENSE_R 1 2 SMC_TBT_ISENSE IN 99 S G 5 41 IN SPI_SMC_CLK 402 1 2 SPI_MLB_CLK OUT 43 52
MAKE_BASE=TRUE 4 PLACE_NEAR=U6100.6:1MM
5% 5%
1 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL
R5097 41
MAKE_BASE=TRUE
7 1/16W
MF-LF SMC_GFX_OVERTEMP IN 41 78
R5024 1/16W
MF-LF
100K 402 33 402
SMC Crystal Circuit 1%
1/20W
41 SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
7 41 IN SPI_SMC_CS_L 1 2
PLACE_NEAR=U6100.1:1MM
SPI_MLB_CS_L OUT 43 52
MF 5%
2 201 41 BDV_BKL_PWM NC_BDV_BKL_PWM 1/16W
MAKE_BASE=TRUE MF-LF
R5010 41 SMC_VCCIO_CPU_DIV2 42 41 SMC_PME_S4_DARK_L SDCONN_STATE_CHANGE_SMC 25
402
1
2.49K2 MAKE_BASE=TRUE
41 SMC_XTAL SMC_XTAL_R 78 42 41 8 =PP3V3_S5_SMC
=TBT_WAKE_L 18 35
1% CRITICAL 1 =PP3V3_S4_SMC
1/20W R5096 42 25 8
MF
201 Y5010
3.2X2.5MM-SM-1
100K
1%
R5068 100K
NO STUFF
1 2
SMC_OOB1_TX_L
12.000MHZ-30PPM-10PF
1/20W
MF
R5012 41 39
5% 1/20W MF 201
2 201 22 42 41 SMC_PME_S4_DARK_L R5069 100K 1 2
41 SMC_EXTAL 1 3 18 PM_CLK32K_SUSCLK_R 1 2 SMC_CLK32K 41 5% 1/20W MF 201
IN
PLACE_NEAR=U1800.N14:5.1mm
OUT
49 42 41 SMC_ONOFF_L R5070 10K 1 2
5% 5% 1/20W MF 201
2 4 1/20W 41 G3_POWERON_L R5072 10K 1 2
MF 5% 1/20W MF 201
201 SMC_LID R5071 100K 1 2
1 C5010 1 C5011 CPU_THRMTRIP_3V3 49 42 41
NC
NC
42 41 5% 1/20W MF 201
12PF 12PF
OUT
43 41 7 SMC_TX_L R5073 10K 1 2
5% 1/20W MF 201
5%
50V
5%
50V CRITICAL 43 41 7 SMC_RX_L R5074 100K 1 2
2 C0G-CERM 2 C0G-CERM 3 5% 1/20W MF 201
R5075
0402 0402 HDMI HPD ESD PROTECTION MMBT3904LP-7
Q5058 1
PM_THRMTRIP_B_L 41 40
41 40
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L R5076
10K
100K
1
1
2
2
5% 1/20W MF 201
Inversion now taking place on RIO DFN1006-3 SMC_TMS R5077 10K 5% 1/20W MF 201
R5058 43 41 7
R5078 10K
1 2
5% 1/20W MF 201
=PP3V3_S4_SMC 8 25 42
2 3.3K 2 43 41 7 SMC_TDO 1 2
B 1
1
5%
PM_THRMTRIP_L IN 11 20 89
43 41 7 SMC_TDI R5079
R5080
10K
10K
1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
B
R5059 1/20W 43 41 7 SMC_TCK 1 2
MF 5% 1/20W MF 201
SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ 100K 201 41 SMC_BIL_BUTTON_L R5081 10K 1 2
5% 5% 1/20W MF 201
1/20W 60 42 41 SMC_BC_ACOK R5087 470K 1 2
MF 5% 1/20W MF 201
2 201 41 SMC_S5_PWRGD_VIN R5092 100K 1 2
5% 1/20W MF 201
R5057 51 41 SMS_INT_L R5093 10K 1 2
5% 1/20W MF 201
1K CPU_THRMTRIP_3V3 R5094 100K 1 2
Hall Effect pads 41 OUT SMC_DP_HPD_L 1 2 HDMI_HPD_L IN 7 38 82
42 41
OMIT_TABLE 1
R5088
J5050 1
R5082 1K
HALL-SENSOR-MLB-PADS-K99 100K 5%
SM 5% 1/20W
1/20W MF
MF
1 8 201
2 201
NC NC 2 SMC_THRMTRIP R5086 10K
2 7 =PP3V42_S3_HALL R5050 42 41 1 2
5% 1/20W MF 201
3 6 0 49 IN =PSOC_WAKE_L SMC_PME_S4_WAKE_L OUT 41
7SMC_LID_R 1 2 SMC_LID 41 42 49 MAKE_BASE=TRUE
NC
4 5
NC 5% 34 IN =BT_WAKE_L 70 41 37 SMC_DELAYED_PWRGD R5091 100K 1 2
1/16W 5% 1/20W MF 201
MF-LF
402
1 C5050 70 41 SMC_PM_G2_EN R5098 100K 1 2
5% 1/20W MF 201
0.001UF R5085
10%
2 50V
X7R-CERM
BATLOW# ISOLATION 70 41 18
70 41
SMC_ADAPTER_EN
SMC_S4_WAKESRC_EN R5090
10K
100K
1
1
2
2
5% 1/20W MF 201
8 =PP3V3_S5_SMCBATLOW =PP3V3_SUS_SMC 8
34 7 PP3V3_WLAN
41 34 7 WIFI_EVENT_L R5089 10K 1 2
5% 1/20W MF 201
D D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
=PP3V3_S5_LPCPLUS 31 32
8
8 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 7 25 92
92 82 41 17 7 BI LPC_AD<0> 3 4 LPC_AD<2> BI 7 17 41 82 92
92 82 41 17 7 BI LPC_AD<1> 5 6 LPC_AD<3> BI 7 17 41 82 92
7 8
43 7 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB BI 7 20 52
LPC_FRAME_L 13 14 SPI_ALT_CS_L
92 82 41 17 7 IN IN 7 43
LPCPLUS_RESET_L 19 20 SMC_TDI
25 7 IN OUT 7 41 42
C 33 34 C
516S0573
SPI_ALT_MOSI 7 43
SPI_ALT_CLK 7 43
SPI_ALT_CS_L 7 43
5% 5% PLACE_NEAR=R5125.2:5mm
1/16W 1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
33
MF-LF
402 B
92 17 IN SPI_CLK_R 1 2 92 SPI_CLK 1 2 SPI_MLB_CLK OUT 42 52
5% 5% PLACE_NEAR=R5126.2:5mm
1/16W 1/16W
PLACE_NEAR=U1800.AY1:5mm R5112 MF-LF
402 R5122 MF-LF
402
SPI_MOSI_R 1
15
2 92 SPI_MOSI 1
33 2 SPI_MLB_MOSI
92 17 IN OUT 42 52
5% 5% PLACE_NEAR=R5127.2:5mm
1/16W 1/16W
MF-LF
402 R5123 MF-LF
402
1
60.4 2
92 17 OUT SPI_MISO SPI_MLB_MISO IN 42 52
1% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
R5200 1
1
R5250 1
1
R5280 1
1
Panther Point R5201 SMC R5251 GPU Temp (Ext) SMC R5281 Battery Charger
1K 1K 4.7K 4.7K 2.0K 2.0K
5% 5% 5% 5% 5% 5%
U1800 1/16W 1/16W U4900 1/16W 1/16W EMC1414-A: U5550 U4900 1/16W 1/16W ISL6258 - U7000
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
(MASTER) 402
2 2
402 (MASTER) 402
2 2
402 (Write: 0x98 Read: 0x99) (MASTER) 402
2 2
402 (Write: 0x12 Read: 0x13)
94
92 17 SMBUS_PCH_CLK SMB_0_S0_CLK 41 SMBUS_SMC_0_S0_SCL =SMBUS_GPUTHMSNS_SCL 47 SMB_5_CLK SMBUS_SMC_5_G3_SCL =SMBUS_CHGR_SCL 61
D 92 17
MAKE_BASE=TRUE
SMBUS_PCH_DATA TBT SMB_0_S0_DATA 94
41
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA =SMBUS_GPUTHMSNS_SDA 47 SMB_5_DATA
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA =SMBUS_CHGR_SDA 61
D
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
U3600
(WRITE: 0xFE READ: 0xFF)
R5270 1
33 =I2C_PCA9557D_SDA 1
SMC R5271 Trackpad
1K 1K 1 1
U4900
5%
1/16W
5%
1/16W J5800 SMC R5290 R5291 DEBUG SENSOR ADC A
MF-LF MF-LF 4.7K 4.7K
(MASTER) 402 2 2 402 (Write: 0x90 Read: 0x91) 5% 5%
U4900 1/16W 1/16W UD100
Audio SMB_2_S3_CLK SMBUS_SMC_2_S3_SCL =I2C_TPAD_SCL
MF-LF MF-LF
49 (MASTER) 402 2 2 402 (Write: 0x10 Read: 0x11)
MAKE_BASE=TRUE
U6751 & U6750 94
SMB_2_S3_DATA SMBUS_SMC_2_S3_SDA =I2C_TPAD_SDA 49 SMB_3_CLK 41 SMBUS_SMC_3_SCL =I2C_SMC_ADCS_SCL 98
24 =SMBUS_XDP_SCL
SMS
24 =SMBUS_XDP_SDA U5920
(WRITE: 0X30/31 READ: 0X32/33)
GYRO
51 =I2C_SMC_SMS_SCL
U5940
(WRITE: 0XD0 READ: 0XD1)
51 =I2C_SMC_SMS_SDA
=I2C_SMC_GYRO_SCL 51
=I2C_SMC_GYRO_SDA 51
92 17 SML_PCH_0_DATA
MAKE_BASE=TRUE
44 8 =PP3V3_S0_DPMUXI2C
A U1800
(Write: 0x88 Read: 0x89)
1/16W
MF-LF
402
2 2
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
402 PAGE TITLE
SML_PCH_1_CLK 1 2
92 17
MAKE_BASE=TRUE SMBus Connections
92 17 SML_PCH_1_DATA 1 2 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
R5222 Apple Inc. 051-9589 D
0 REVISION
5% R
1/16W
MF-LF
4.18.0
SMLink 1 is slave port to 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
access PCH & CPU via PECI. PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 44 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
PLACE_NEAR=U4900.N11:5mm
PBUS Voltage Sense Enable & Filter GPU VCore Load Side Current Sense / Filter R5310
4.53K
80 GFXIMVP6_IMON 1 2
CRITICAL IN
SENSOR_NONPROD:Y 1%
=PP3V3_S0_ISNS 1/20W
Q5300 98 45 8
99 CRITICAL MF
201
NTUD3169CZ
SOT-963
1
C5310
N-CHANNEL 0.1UF
6 PBUSVSENS_EN_L 20%
10V
2 CERM
Enables PBUS VSense D 402
SENSOR_NONPROD:Y
1
divider when in S0. R5302 EDP:50A CRITICAL
100K Vimon=3x50A*(0.2/R8915)*R8912=1V U5310 SENSOR_NONPROD:Y
70 IN =PBUSVSENS_EN 2 G 1%
1/16W OPA2333 PLACE_NEAR=U4900.N11:5mm
SMC Key IG0C
S
D 1
MF-LF
402
2
3
V+
8
DFN R5308
4.53K
SMC_ADC15 D
1 GPUVCORE_IOUT 1 2 SMC_GPU_CORE_ISENSE OUT 42
3 PBUS_S0_VSENSE
SMC Key VP0R
GPUVCORE_INV 2 V- 1%
1/20W
SENSOR_NONPROD:Y
D THRM MF 1
C5308
R5303 1 SMC_ADC5 9
4
201
0.22UF
PLACE_NEAR=U4900.N11:5mm
27.4K 20%
5 G 6.3V
1% 2 X5R
S 1/16W PLACE_NEAR=U4900.L8:5MM 0201
8 =PPBUS_S0_VSENSE MF-LF
4
402
2
RTHEVENIN = 4573 Ohms SENSOR_NONPROD:Y Gain: 3.004x GND_SMC_AVSS
1
P-CHANNEL SMC_PBUS_VSENSE OUT 42
R5309 SENSOR_NONPROD:Y
R5307
499K
R5301 1 PLACE_NEAR=U4900.L8:5MM
1%
1/16W 1
1M
2
100K R5304 1 1
C5304
MF-LF
1%
1%
1/16W 5.49K 2 402 1/16W
MF-LF 1%
0.22UF MF-LF
20% 402
402 1/16W 6.3V
2
MF-LF 2 X5R
402 402 SIGNAL_MODEL=EMPTY
PBUSVSENS_EN_L_DIV 2
PLACE_NEAR=U4900.L8:5MM GND_SMC_AVSS 41 42 45 46 99
NC
=CHGR_ACOK IN 42 61 Vi=Voltage across R7640=0.02139V CRITICAL SMC Key IC1C
NOSTUFF SENSOR_NONPROD:Y U5310
1
Q5310 R5323 PLACE_NEAR=U4900.L12:5mm SMC_ADC11
R5315 NTUD3169CZ 6.49K 8 OPA2333 SENSOR_NONPROD:Y
R5327
0 Enables DC-In VSense SOT-963 96 67 IN CPUVCCIOS0_CS_P 1 2 96 CPUVCCIOISNS_R_P 5 DFN
5%
1/20W divider when AC present.
N-CHANNEL 6 DCINVSENS_EN_L 1%
V+ 7 ISENSE_CPUVCCIO_IOUT 1
4.53K
2 SMC_CPUVCCIO_ISENSE 42
1/16W
OUT
MF
2 201 D
MF-LF
SENSOR_NONPROD:Y 402
6 V- 1%
1/16W SENSOR_NONPROD:Y
R5312 1 R5324 THRM
4 MF-LF
402 1
C5327
C DCINVSENS_EN 2 G
100K
1% 96 67 IN CPUVCCIOS0_CS_N 1
6.49K
2 96 CPUVCCIOISNS_R_N
9
Gain: 154x 0.22UF
PLACE_NEAR=U4900.L12:5mm
C
NC
20%
S 1/16W
NC
1% 6.3V
MF-LF 2 X5R
402 1/16W SENSOR_NONPROD:Y
1 402
R5316 1 2 MF-LF
402
1
R5325 SENSOR_NONPROD:Y
R5326
0 3 DCIN_S5_VSENSE 1M GND_SMC_AVSS 41 42 45 46 99
5% Enables DC-In VSense 1% 1M
1/20W 1/16W 1 2
MF divider when SUS present. D MF-LF
2 201 R53131 SMC KEY VD0R 2
402 1%
1/16W
PM_SUS_EN IN 70
5 G
30.9K
1%
PLACE_NEAR=U4900.N9:5MM SMC_ADC3 MF-LF
402
SIGNAL_MODEL=EMPTY
S 1/16W
8 =PPDCIN_S5_VSENSE MF-LF Divider set for Vin max of 22.32V
4
402 2 RTHEVENIN = 4567 Ohms
P-CHANNEL SMC_DCIN_VSENSE 42
OUT
1
R5311 PLACE_NEAR=U4900.N9:5MM
PLACE_NEAR=U4900.N9:5MM
100K
1%
R5314 1
1
C5314
CPU SA Current Sense / Filter
1/16W 5.36K 0.22UF 99 98 45 8 =PP3V3_S0_ISNS
MF-LF 1% 20%
402
2
1/16W 6.3V
MF-LF 2 X5R
PDCINVSENS_EN_L_DIV
402 2 402
1
C5360
EDP:6A 0.1UF
GND_SMC_AVSS 41 42 45 46 99
20%
Vi=Voltage across R7140=0.006V CRITICAL 2
10V
U5360
X7R-CERM
0402 SMC Key IC2C
R5363 8 OPA2333 PLACE_NEAR=U4900.M10:5mm SMC_ADC13
1.82K R5367
96 62 IN VCCSAS0_CS_P 1 2 96 VCCSAISNS_R_P 3 DFN
1%
1/16W
MF-LF
GAIN:549X X5R
402
PLACE_NEAR=R7510.2:5 MM PLACE_NEAR=U4900.N10:5MM
B 1/16W
MF-LF
402
1
C5320
0.22UF
402 1
R5365
1M R5366 GND_SMC_AVSS 41 42 45 46 99 B
PLACE_NEAR=U4900.N10:5MM 20%
1% 1M
1/16W 1 2
6.3V
2 X5R MF-LF
402 1%
402 2 1/16W
MF-LF
GND_SMC_AVSS 41 42 45 46 99 402
SIGNAL_MODEL=EMPTY
GND_SMC_AVSS 41 42 45 46 99
DDR3 1.5V DRAM ONLY CURRENT SENSE / FILTER
SMC KEY IM0C
SMC_ADC10
NC
GPU Vcore Voltage Sense / Filter EDP CURRENT:8A
CRITICAL
=PPVIN_S3_MEM_ISNS_R U5360 PLACE_NEAR=U4900.N13:5mm
8 IN R5373 OPA2333
SMC KEY VG0C 8
A 8 =PPVCORE_GPU_REG
XW5335
SM
R5335 SMC_ADC14
R5360
0612
2 4
96 ISNS_1V5_MEM_P
1
7.32K
1%
2 96 ISNS_1V5_MEM_R_P 5
V+
DFN
7 ISENSE_P1V5MEM_IOUT 1
R5377
4.53K
2 SMC_P1V5MEM_ISENSE 42
SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
4.53K MF
1/16W
OUT PAGE TITLE
1W
1 2 GPUVSENSE_IN 1 2 SMC_GPU_CORE_VSENSE OUT 42 1%
MF-LF 6 V- 1%
1%
402
THRM
1/16W
MF-LF
Voltage & Load Side Current Sensing
PLACE_NEAR=R8940.1:5 MM PLACE_NEAR=U4900.L10:5MM 0.003 R5374 4
1/16W 96 ISNS_1V5_MEM_N 402 1
C5377 DRAWING NUMBER SIZE
MF-LF 1
C5335 1 3 7.32K 9 PLACE_NEAR=U4900.N13:5mm
402
0.22UF CRITICAL 1 2 96 ISNS_1V5_MEM_R_N 0.22UF
Apple Inc. 051-9589 D
NC
20%
PLACE_NEAR=U4900.L10:5MM
NC
20% 6.3V
6.3V
1% GAIN:136.6X 2 X5R REVISION
2 8 =PPVIN_S3_MEM_ISNS 1/16W R
X5R
402
OUT MF-LF
402 1
402
4.18.0
R5375 R5376 GND_SMC_AVSS 41 42 45 46 99 NOTICE OF PROPRIETARY PROPERTY: BRANCH
GND_SMC_AVSS 41 42 45 46 99 1M 1M
1% 1 2 THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE INC.
MF-LF 1% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 1/16W
2 MF-LF
402
SIGNAL_MODEL=EMPTY I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 132
Gain: 182x III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 45 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
COMPUTING High Side Current Sense / Filter
SIGNAL_MODEL=EMPTY
46 8 =PP3V3_S0_HS_ISNS
SENSOR_NONPROD:Y
SMC Key IC0R
CPU VCore Load Side Current Sense / Filter
C5401 PLACE_NEAR=R7510.3:5MM R5456
1 5.23K
EDP Current:20.1A 0.1UF SMC_ADC8 97 66 65 CPUIMVP_ISNS1_P 1 2
20% IN
10V 0.5%
3
CERM 1/16W
2 402
8 OUT =PPVIN_S5_HS_COMPUTING_ISNS V+ MF
402 46 8 =PP3V3_S0_IMVPISNS SENSOR_NONPROD:Y
PLACE_NEAR=U4900.N8:5MM SENSOR_NONPROD:Y PLACE_NEAR=U5450.5:3MM
U5400 R5403 PLACE_NEAR=R7520.3:5MM
R5457
R5400
2 4 INA213 4.53K 5.23K
SIGNAL_MODEL=EMPTY 1 C5450
96
0612
ISNS_HS_COMPUTING_N 5 IN- SC70 OUT 6 HS_COMPUTING_IOUT 1 2 SMC_CPU_HI_ISENSE 42 97 66 65 CPUIMVP_ISNS2_P 1 2 0.1UF
D
MF
1W
1% CRITICAL 1%
1/16W
PLACE_NEAR=U4900.N8:5MM
OUT IN
0.5%
1/16W SENSOR_NONPROD:Y
20%
10V
2 X7R-CERM
0402
SMC Key IC0C D
Power Drop across R5400 at EDP becomes 1.21W 96 ISNS_HS_COMPUTING_P 4 IN+ REF 1 MF-LF
1 C5403 MF SMC_ADC1
0.003 1 3
402
0.22UF SENSOR_NONPROD:Y 402 SENSOR_NONPROD:Y CRITICAL
20%
CRITICAL GND 6.3V
PLACE_NEAR=R7530.3:5MM
R5458 R5452 U5450 SENSOR_NONPROD:Y
X5R
2 402 5.23K 3.48K OPA333DCKG4 PLACE_NEAR=U4900.M11:5MM
2
5
Gain:50x 97 66 65 IN
CPUIMVP_ISNS3_P 1 2 96 CPUIMVP_ISNS_P 1 2 97 CPUIMVP_ISUM_R_P 1
+ SC70-5 R5451
8 IN =PPVIN_S5_HS_COMPUTING_ISNS_R SIGNAL_MODEL=EMPTY 0.5% 1% V+ 4
4.53K
GND_SMC_AVSS 41 42 45 46 99 1/16W 1/16W CPUIMVP_ISUM_IOUT 1 2 SMC_CPU_ISENSE OUT 42
MF MF-LF
402 402 1% SENSOR_NONPROD:Y
SENSOR_NONPROD:Y 3 V- 1/16W PLACE_NEAR=U4900.M11:5MM
PLACE_NEAR=R7510.4:5MM - MF-LF
R5470 R5453 2
402 1 C5451
5.23K 3.48K
GRAPHICS High Side Current Sense / Filter 97 66 IN
CPUIMVP_ISNS1_N 1 2 CPUIMVP_ISNS_N 1 2 97 CPUIMVP_ISUM_R_N 0.22UF
20%
6.3V
SIGNAL_MODEL=EMPTY 0.5% 1% 2 X5R
1/16W 1/16W
MF MF-LF 402
SENSOR_NONPROD:Y SENSOR_NONPROD:Y
402 402
=PP3V3_S0_HS_ISNS SENSOR_NONPROD:Y GND_SMC_AVSS
46 8
R5455 41 42 45 46 99
PLACE_NEAR=R7520.4:5MM 1 732K
SENSOR_NONPROD:Y R5471 R5454 1 2
1 C5411 5.23K 732K
0.1UF 97 66 IN CPUIMVP_ISNS2_N 1 2 1% 1% Gain:140x
20%
SMC Key IG0R 1/16W 1/16W SIGNAL_MODEL=EMPTY
10V SIGNAL_MODEL=EMPTY 0.5% MF-LF MF-LF Scale: 28.55A / V
EDP Current:4.9A SMC_ADC2 1/16W 402
3
CERM 2 402
2 402
MF
402
Max VOut: 3.3V at 94.2A
=PPVIN_S5_HS_GPU_ISNS V+
PLACE_NEAR=R7530.4:5MM
8 OUT
PLACE_NEAR=U4900.K9:5MM SENSOR_NONPROD:Y R5472
R5410 U5410 R5413 CPUIMVP_ISNS3_N 1
5.23K
2
97 66 IN
0612
2 4 INA210 4.53K SIGNAL_MODEL=EMPTY
MF
96 ISNS_HS_GPU_N 5 IN- SC70OUT 6 HS_GPU_IOUT 1 2 SMC_GPU_HI_ISENSE OUT 42 SIGNAL_MODEL=EMPTY 0.5%
1/16W
1W
1% CRITICAL 1% PLACE_NEAR=U4900.K9:5MM MF
1/16W 402
0.003 96 ISNS_HS_GPU_P 4 IN+ REF 1 MF-LF C5413
402 1 Sense R is R7510, R7520 & R7530
1 3 0.22UF
20%
CRITICAL GND 6.3V Individual Sense R is 0.75mOhm
2 X5R EDP: 94A TDP :45A
2
=PPVIN_S5_HS_GPU_ISNS_R 402
8 IN
Gain:200x
C GND_SMC_AVSS 41 42 45 46 99
(Effective Sense R is 0.25mOhm due to summing of the 3 phases)
C
SIGNAL_MODEL=EMPTY
CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
116S0114 2 RES,MTL FILM,100K,5,1/16W,0402,SMD,LF C5451,C5461 SENSOR_NONPROD:N
IPBR
R5423 R5420 SMC_ADC7
45.3K 0
61 IN CHGR_BMON 1 2 SMC_CHGR_BMON_INSENSE_R 1 2 SMC_CHGR_BMON_ISENSE OUT 42
1% 5%
From charger 1/16W
MF-LF 1 C5421 1/16W
MF-LF
402 0.022UF 402
10%
16V
2 X5R-X7R-CERM
0402
A GND_SMC_AVSS 41 42 45 46 99
SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
DC-IN (AMON) Current Sense Filter High Side and CPU/AXG Current Sensing
PLACE_NEAR=U4900.K10:5MM SMC Key ID0R DRAWING NUMBER SIZE
EDP Current:4.6A
R5441 SMC_ADC4
Apple Inc. 051-9589 D
1
45.3K2 REVISION
61 CHGR_AMON SMC_DCIN_ISENSE 42 R
IN
1% PLACE_NEAR=U4900.K10:5MM
OUT
4.18.0
1/16W NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF
402
1 C5441 THE INFORMATION CONTAINED HEREIN IS THE
0.0022UF PROPRIETARY PROPERTY OF APPLE INC.
10% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
50V
2 CERM
402
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
GND_SMC_AVSS 41 42 45 46 99
IV ALL RIGHTS RESERVED 46 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TG0D 0.0022uF
10%
EMC1414-A-AIA
50V DFN
CERM 2 2 DP1 7 GPUTHMSNS_THM_L
402 THERM*/ADDR
BC846BMXXH 2
SOT732-3 CRITICAL 3
SIGNAL_MODEL=EMPTY
5 DN2/DP3 SMCLK 10 =SMBUS_GPUTHMSNS_SCL 44
BI
1
C5552 1 GND THRM_PAD
Placement note: Q5503 1
0.0022uF 6 11
PLACE Q5501 ON TOP SIDE BC846BMXXH 10%
TG0P GPU PROXIMITY TEMPERATURE
SOT732-3 50V
CERM 2
3
CLOSE TO THE LEFT FIN STACK 2 402
96 GPUTHMSNS_D_N
Placement note:
PLACE U5550 ON TOP SIDE UNDER GPU
Th2H Th1H PLACE_NEAR=U5550.4:5mm
LEFT FIN STACK TEMPERATURE RIGHT FIN STACK TEMPERATURE
PLACE_NEAR=U5550.5:5mm THSP TBT DIE
Placement note: TP_TBT_THERM_DP 97 TBT_THERMD_P
35 BI
PLACE Q5503 ON BOTTOM SIDE NEAR RIGHT FIN STACK Write Address: 0x98 MAKE_BASE=TRUE
NOSTUFF
Read Address: 0x99
1
R5520
10K
PLACE_SIDE=BOTTOM 5%
1/16W
MF-LF
1 2 97 TBT_THERMD_N
R5570 XW5520
C 8 =PP3V3_S0_CPUTHMSNS 1
47
2 PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
SM
C
5% MIN_NECK_WIDTH=0.2 mm Use GND pin B1 on U3600 for N leg
1/16W
MF-LF
VOLTAGE=3.3V
1
C5570
0.1UF
402
1 20% R5571 1 1
R5572
10V
VDD 2 X7R-CERM
10K 10K
TM0P DDR3 PROXIMITY TEMPERATURE 0402 5% 5%
U5570 1/16W
MF-LF
1/16W
MF-LF
96 DDR3THMSNS_D1_P EMC1414-A-AIA 402
2 2
402
PLACE_NEAR=U5570.2:5mm
DFN
2 DP1 THERM*/ADDR 7 CPUTHMSNS_THM_L
CRITICAL 3 PLACE_NEAR=U5570.3:5mm
1
Q5504 1 0.0022uF
10%
BC846BMXXH 50V
2
SOT732-3 CERM
402
2
3
96 CPUTHMSNS_D2_N Write Address: 0x98
TP0P PCH PROXIMITY TEMPERATURE Read Address: 0x99
PLACE_NEAR=U5570.4:5mm
Placement note: PLACE_NEAR=U5570.5:5mm
1 C5523 1
PLACE_NEAR=J3501
R5522
PLACE_SIDE=BOTTOM 0.1uF 10K
C1 20%
5%
10V
V+ 2 CERM
1/16W
402 MF-LF
U5523 2 402
TMP105
WCSP-6
44 BI =I2C_X29THMSNS_SDA A1 SDA A0 C2 X29THMSNS_A0
CRITICAL
44 BI =I2C_X29THMSNS_SCL B1 SCL ALERT B2 NC
A SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE
D D
CRITICAL CRITICAL
R5650 1 J5650 R5660 1 J5660
47K FF14A-5C-R11DL-B-3H 47K FF14A-5C-R11DL-B-3H
5% F-RT-SM 5% F-RT-SM
1/16W 1/16W
MF-LF 6 MF-LF 6
NC NC
R5655 402 2
R5665 402 2
47K 1 47K 1
41 OUT SMC_FAN_0_TACH 1 2 7 FAN_LT_TACH 41 OUT SMC_FAN_1_TACH 1 2 7 FAN_RT_TACH
5% 2 5% 2
1/16W 1/16W
MF-LF 3 MF-LF 3
402 402
4 4
1 1
R5651 5 R5661 5
100K NC 100K NC
5% 5 5% 2
1/16W Q5660 7 1/16W Q5660 7
MF-LF MF-LF
402 2
G 2N7002DW-X-G NC 402 2
G 2N7002DW-X-G NC
SOT-363 SOT-363
4 S D 3 518S0769 1 S D 6 518S0769
41 IN SMC_FAN_0_CTL 7 FAN_LT_PWM 41 IN SMC_FAN_1_CTL 7 FAN_RT_PWM
B B
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE
3V3 LDO
V+
VDD
10UA
80UA
60MA (MAX)
2.55 KOHM
10 OHM
0.0255
0.204
0.6
V
V
V
0.255E-6
16.32E-6
36E-3
W
W
W Keyboard Connector
VOUT 60MA (MAX) 0.2 OHM 0.012 V 0.72E-3 W
- SPI HOST TO Z2
- TRACKPAD PICK BUTTONS PSOC VDD 8MA (TYP)
14MA (MAX)
1.5 OHM 0.012
0.021
V
V
96E-6
294E-6
W
W
IPD Flex Connector
- KEYBOARD SCANNER 18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W CRITICAL
49 8 =PP3V3_S4_TPAD 32
PLACE_SIDE=BOTTOM 49 8 =PP3V42_G3H_TPAD
D
5%
1/16W
MF-LF
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V 1 C5704 1 C5705 1 C5706
5%
1/20W
MF 1
NOSTUFF
C5708
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM 2 1 49 7 WS_KBD2 27 D
402 100PF 0.1UF 4.7UF 201
0.1UF 49 7 Z2_CS_L 4 3 Z2_KEY_ACT_L 7 49 49 7 WS_KBD3 26
1 5% 10% 20% 10% 6 5 25
R5703 2 25V
NP0-CERM 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
NC NC 49 7 WS_KBD4
220K 0201 201 402 201 49 7 Z2_MOSI 8 7 PSOC_F_CS_L 7 49 49 7 WS_KBD5 24
5%
1/20W 49 7 Z2_MISO 10 9 PICKB_L 7 49 49 7 WS_KBD6 23
MF TPAD_5V_SW_S4
201 2 PLACE_NEAR=J5800.18:3MM 49 7 Z2_SCLK 12 11 PSOC_MISO 7 49 49 7 WS_KBD7 22
56
55
54
53
52
51
50
49
48
47
46
45
44
43
0201 201 2 MF-LF
TPAD_5V_LDO 402 7 WS_KBD16_NUM 13
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
PLACE_NEAR=J5800.18:3MM WS_KBD17 12
L5707 R5715 49 7
10K WS_KBD18 11
49 WS_CONTROL_KEY 1 P2_3 P2_2 42 WS_KBD17 7 49
FERR-120-OHM-1.5A 49 WS_KBD16N 1 2
49 7
49 7 WS_KBD19 10
49 7 Z2_KEY_ACT_L 2 P2_1 CRITICAL P2_0 41 WS_KBD16N 49 49 PP5V_S5RS4_CUMULUS 1 2 1%
1/16W 49 7 WS_KBD20 9
3 40
TPAD_VBUS_EN
NC
4
P4_7
P4_5
OMIT
U5701
P4_6
P4_4 39
WS_KBD15_C
WS_KBD14
49 0402-LF
TPAD_5V_LDO SMC Manual Reset & Isolation MF-LF
402 49 7 WS_KBD21 8
70 IN
5 P4_3 P4_2 38 WS_KBD13
7 49
1 C5707 Left shift, option & control keys combined with power button cause SMC RESET# assertion. 49 7 WS_KBD22 7
NC CY8C24794 7 49
0.1UF Keys ANDed with PSoC power to isolate when PSoC is not powered. R5710 49 7 WS_KBD23 6
6 P4_1 MLF P4_0 37 WS_KBD12 7 49
10%
PLACE_NEAR=J5800.18:3MM 1K
NC 10V
2 X5R-CERM No IPD on OE input pin PP3V3_S4 (symbol error). 42 41 OUT SMC_ONOFF_L 1 2 7 WS_KBD_ONOFF_L 5
49 7 PSOC_MISO 7 P3_7 (SYM-VER2) P3_6 36 WS_KBD11 7 49 0201 49 8 =PP3V42_G3H_TPAD 5% 4
PSOC_F_CS_L 8 35 WS_KBD10
49 7
49 7 PSOC_MOSI 9
P3_5
P3_3
337S2983 P3_4
P3_2 34 WS_KBD9
7 49
7 49
C5710
0.1UF
1
1/16W
MF-LF
402
49 7 WS_LEFT_SHIFT_KBD 3
2
10 33 49 7 WS_LEFT_OPTION_KBD
49 7 PSOC_SCLK P3_1 P3_0 WS_KBD8 7 49
1 C5750 20%
1
C 49 7 Z2_MISO 11 P5_7 P5_6 32 WS_KBD7 7 49
0.1UF
10%
10V
CERM
402
2 49 7 WS_CONTROL_KBD
C
10
49 7 Z2_CS_L 12 P5_5 P5_4 31 WS_KBD1 7 49 2 16V
PLACEMENT_NOTE=NEAR J5713
X7R-CERM 31
49 7 Z2_MOSI 13 P5_3 P5_2 30 WS_KBD2 7 49 VDD
0402
F-RT-SM
19 VSS
22 VDD
THRML SLG4AP021
20 D+
21 D-
PAD 57 FF14A-30C-R11DL-B-3H
TQFN
49 8 =PP3V3_S4_TPAD 4 OE J5713
(IPD) CRITICAL
TP_PSOC_SCL WS_KBD4 7 49
1 IN_1
OUT_1 9 WS_LEFT_SHIFT_KEY 49 518S0752
49 7 WS_LEFT_SHIFT_KBD
TP_PSOC_SDA WS_KBD5 7 49 (IPD)
OUT_2 8 WS_LEFT_OPTION_KEY 49
7 TP_PSOC_P1_3 WS_KBD6 7 49 49 7 WS_LEFT_OPTION_KBD 2 IN_2
(IPD)
TP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_0 3 IN_3
OUT_3 7 WS_CONTROL_KEY 49
WS_CONTROL_KBD
ISSP SCLK/I2C SCL ISSP SDATA/I2C SDA 49 7
(IPD)
Pull-up in U5010.
R5701 Z2_CLKIN 7 49 OUT_ALL# 6 SMC_TPAD_RST_L OUT 42
USB_TPAD_P 24 96
91 9 1 2 26 USB_TPAD_R_P TP_P7_7
5% THRM
1/20W
MF
(PP3V3_S3_PSOC) GND PAD
WS_KBD15_C CAP_COMP_H CAP_COMP_L Q5736 Q5738 LED Current
11
201
R5702 1 C5702 1 C5703 1 C5701 Z 1 1 off off none
24 96
100PF 0.1UF 4.7UF
91 9 USB_TPAD_N 1 2 26 USB_TPAD_R_N 5% 10% 20% 1 0 1 on off source
2 25V
NP0-CERM 2 6.3V
X5R 2 6.3V
X5R
5%
1/20W 0201 201 402 0 1 0 off on sink
MF
201
BYPASS=U5701.22:19:5 mm CAPS:EXT CAPS:EXT CAPS:EXT
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11 mm R57401 R57381 R57361
10K 10K 10K 1 CAPS:EXT
B
Caps Lock LED Drive 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF S Q5736
B
TPAD_5V_NO_FET
201 2 201 2 201 2 NTZD3152P
2 SOT-563-HF
R5720 5V TPAD FET G
0 49 8 =PP3V3_S4_TPAD
1 2
5% MOSFET SiA413 CAPS:EXT CAPS:EXT CAPS:EXT D
All RC values are TBD 1/16W
MF-LF
402 CHANNEL P-TYPE 12V
1
R5730 1
R5732 1
R5734 CAPS:EXT 8
6
10K 10K 20K CAP_SOURCE
5% 5% 5% V+ CAPS:EXT MIN_LINE_WIDTH=0.2MM
5V TRACKPAD S4 FET TPAD_5V_FET RDS(ON) 29 mOhm @4.5V 1/20W 1/20W 1/20W MIN_NECK_WIDTH=0.1MM
CRITICAL
Q5720
MF
2 201
MF
2 201
MF
2 201
U5730 R57371
LOADING 16 mA (EDP) LM393ADGKR 113
SIA413DJ MSOP 1%
CAP_VREF_L 6
7 1/20W
SC70-6L MF
8 =PP5V_S5_TPAD 49 WS_KBD15_C 5 201 2
7
WS_KBD15_CAP
S
7 49
D
PP5V_S5RS4_CUMULUS
4
49
2 CAPS:EXT MIN_LINE_WIDTH=0.2MM
TPAD_5V_FET TPAD_5V_FET VOLTAGE=5V MIN_NECK_WIDTH=0.1MM
Q5721 TPAD_5V_FET MIN_NECK_WIDTH=0.20MM 1 CAP_COMP_H R57391
C5722 1
MIN_LINE_WIDTH=0.50MM CAP_VREF_H 3
SSM3K15FV D 3 R57211 0.033UF
113
G
MF TPAD_5V_FET 402
10K 20K 10K 4
201 2 C5723 5% 5% 5% CAP_SINK
R5722 0.01UF
1/20W
MF
1/20W
MF
1/20W
MF
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
1 G S 2 P5VCUMULUS_EN_L 1
3.3K 2 P5VCUMULUS_SS 1 2 2 201 2 201 2 201 3
70 IN =P5VS4_TPAD_EN 5%
10%
D CAPS:EXT
1/20W
10V
MF
201 X5R CAPS:EXT Q5738
201 CAP_COMP_L_INV 1 G DMN3730UFB4
CRITICAL S DFN1006H4-3
Q5734
TPAD Buttons Disable BOM Options available to CSA 5 SSM3K15AMFVAPE D 3
A 49 BUTTON_DISABLE
PLACE THESE COMPONENTS CLOSE TO J5800
TPAD_5V:SW_S4
TPAD_5V:LDO_S4
Original implementation off PP5V_S4
PP5V_S5 LDO power in S4 only
VESM 2
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB TPAD_5V:LDO_S5 PP5V_S5 LDO power
Q5701 D 6
KEYBOARD/TRACKPAD (1 OF 2)
SSM6N15FEAPE 1 G S 2 DRAWING NUMBER SIZE
SOT563 CAP_COMP_L
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S0_TPAD
1
R5853
470K
5% J5815 PIN 4 IS GROUNDED
1/16W
MF-LF ON KEYBOARD BACKLIGHT FLEX
2 402 CRITICAL
D MF-LF
2 402 2 1 KBDLED_ANODE2 7 50
D
7 SMC_KBDLED_PRESENT_L 4 3
6 5
NC
8 7 KBDLED_ANODE1 7 50
10 9
13
14
516S0899
Keyboard Backlight Connector
C C
1 OMIT_TABLE
R5857 CRITICAL CTRL
10K L5850 U5850 10
5%
1/16W
15UH-20%-740MA-0.42OHM 1 VIN LED 7 KBDLED_ANODE1 1 2 R5855
MF-LF MIN_LINE_WIDTH=0.25 MM
2 402
1 2 KBDLED_SW1
MIN_LINE_WIDTH=0.3 MM
LT3591 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V
1%
1/16W KBD_BL:SANDWICH KBD_BL:SANDWICH KBD_BL:TBONE KBD_BL:TBONE
SMC_SYS_KBDLED_FILTER VLF403212MT-SM MIN_NECK_WIDTH=0.25 MM 3 SW DFN CAP 5 MF-LF
SWITCH_NODE=TRUE 402 CRITICAL CRITICAL CRITICAL CRITICAL
NOSTUFF NOSTUFF 1 C5850 4 SW CAP 6 KBDLED_CAP1 1 C5855 1 C5856 1 C5857 1 C5858
1 C5859 1 1UF MIN_LINE_WIDTH=0.25 MM 1.0UF 1.0UF 1.0UF 1.0UF
10UF
R5858 10% GND PAD MIN_NECK_WIDTH=0.2 MM 10% 10% 10% 10% PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
120K 2 10V 2 50V 2 50V 2 50V 2 50V
2
8 =PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
D SMS SMS D
14
C5926 1 1
C5922 SMS SMS NOSTUFF
1
10UF 0.1UF 1 1
20% 10% VDD VDD_IO R5920 R5925
6.3V 6.3V
X5R 2 2 X5R NC 2 10K 10K
603 201 SMS NC U5920 5% 5%
3 1/20W 1/20W SMS
BYPASS=U5920.14:13:8 mm 1 NC
R5924 LIS331DLH MF MF
10K LGA
201
2
201
2 R5923
5% 10 CS 8 SMS_I2C_SEL 0
1/20W RESERVED 1 2 =I2C_SMC_SMS_SDA BI 44
MF 15
201 CRITICAL 5%
2
SDO 7 SMS_ADDR_SELECT 1/20W
MF
42 41 OUT SMS_INT_L 11 INT1 SDA/SDI/SDO 6 I2C_SMC_SMS_SDA_R 201
12
13
16
1 2 =I2C_SMC_SMS_SCL IN 44
10K
338S0687 5% 5%
1/20W
1/20W
MF MF
PLACEMENT_NOTE=See schematic for orientation. 201
2
201
Front of system
+X
+Z (dn)
C C
Circle indicates pin 1 location when placed
in correct orientation
8 =PP3V3_S3_GYRO
GYRO
0.1UF
10%
6.3V
2 X5R
201
10%
6.3V
2 X5R
201
0.1UF 10UF
20%
6.3V
2 CERM-X5R
0402-1
GYRO
1 (WRITE: 0XD0 READ: 0XD1)
R5944
10K
GYRO
15
VDD 16
5%
1
1/20W
MF GYRO
2 201 RES/VDD VDD_IO
R5946
CS PU = I2C U5940 338S0927 = 8KHZ 1
0
2 =I2C_SMC_GYRO_SCL IN 44
RES3 12
GND
13
PLLFILT_GYRO
GYRO
1 C5942
0.47UF
10%
2 6.3V
CERM-X5R
402 GYRO
PLLFILT_GYRO1 GYRO 1 C5945
1 0.01UF
R5945 10%
10V
10K 2 X5R-CERM
5% 0201
1/20W
MF
2 201
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
D D
C C
8 =PP3V3_SUS_ROM
1
R6101 CRITICAL
8
3.3K
C6100 1
5% 0.1UF VDD
1/16W 20%
MF-LF 10V
CERM 2 U6100
2 402 402
64MBIT
SPI_MLB_CLK SOIC SPI_MLB_MOSI
43 42 IN 6 SCK SI 5 IN 42 43
SST25VF064C
SPI_MLB_CS_L OMIT
43 42 IN 1 CE* SPI_MLB_MISO
SPI_WP_L SO 2 OUT 42 43
3 WP*
43 20 7 IN SPIROM_USE_MLB 7 HOLD*
NOTE: If HOLD* is asserted VSS
4
ROM will ignore SPI cycles.
B B
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE
AUDIO CODEC
APPLE P/N 353S2355
L6201 U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL
FERR-22-OHM-1A-0.065-OHM PP5V_AUDIO_HPAMP 53
=PP1V5_S0_AUDIO 1 2 PP1V5_S0_AUDIO_DIG
8 IN
MIN_LINE_WIDTH=0.6 MM
0201 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
C6210 1 1
C6211
D 4.7UF
20%
4V
0.1UF
10%
6.3V
PP4V5_AUDIO_ANALOG IN 53 58 59
D
X5R-1 2 2 X5R
402 201 CRITICAL CRITICAL
1
C6214 1 1 C6213
C6219 0.1UF 10UF
10UF C6218 1 1 10% 20%
20%
C6217 16V 10V
GND_AUDIO_CODEC 16V 0.1UF 10UF X5R-CERM 2 2 X5R-CERM
59 58 54 53 2 0201 0402-1
TANT-POLY 10% 20%
24
46
25
16V
CRITICAL CRITICAL 2012-LLP 2 2 16V
9
PP4V5_AUDIO_ANALOG X7R-CERM TANT-POLY GND_AUDIO_CODEC
59 58 53 IN
C6221 1 1 C6220 MIN_LINE_WIDTH=0.20MM VD VA_REF VA_HP VA
0402 2012-LLP
GND_AUDIO_CODEC
53 54 58 59
2
201 MIN_NECK_WIDTH=0.15MM CS4206B HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_REF IN 58
QFN
59 IN AUD_DMIC_SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 57 96
59 IN AUD_DMIC_SDA2 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 AUD_LO1_L_N OUT 57 96 LFT SUBWOOFER AMP. SIG. SOURCE
/SPDIF_OUT2
TP_XCVR_ADC_RSTN 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 57 96
RT. SUBWOOFER AMP. SIG. SOURCE
GPIO3 = SPKR AMP SHDN CONTROL 57 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 57 96
C MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
1 VL_IF
VCOM 28 CS4206_VCOM
C
LINEIN_L+ 21 NO_TEST=TRUE NC_AUD_LI_P_L NC
92 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 NO_TEST=TRUE NC_AUD_LI_REF NC
92 17 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE NC_AUD_LI_P_R NC
R6211 10 SYNC
22
92 17 HDA_SDIN0 1 2 92 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INL_P 58 96
IN IN
EXT MIC CODEC INPUT
5% 5 SDO MICIN_L- 17 AUD_MIC_INL_N IN 58 96
1/20W
MF MICIN_R+ 19
201 11 RESET*
92 17 OUT HDA_SDOUT MICIN_R- 20
92 17 IN HDA_RST_L TP_AUD_MIC_INP_R
TP_AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC NC
AUD_SPDIF_OUT 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM TP_AUD_MIC_INN_R
MIN_NECK_WIDTH=0.15MM
5%
DGND THRM_PAD AGND 1/16W
MF-LF
402
49
26
1 1
C6224 C6225
1UF 10UF
20% 20%
16V 2 2 16V
TANT TANT-POLY
0603-SM 2012-LLP
R6220
B 58 7 OUT AUD_SPDIF_OUT_JACK 1
33 2
B
MIN_LINE_WIDTH=0.5MM
5% 59 58 54 53 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.15MM
1/16W VOLTAGE=0V
MF-LF
402
A 5%
1/20W
MF 1
C6200
GND
2
NC 5
CRITICAL
C6202 1 1
CRITICAL
C6203 SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
201 PAGE TITLE
1UF XW6200 0.1UF 1.0UF
2
10%
10V
X5R
1
C6201
1UF
10%
SM
10%
16V
X5R-CERM 2
20%
10V
2 X5R-CERM
AUDIO: CODEC/REGULATOR
1 2 DRAWING NUMBER SIZE
402
2
10V 0201 0201-1
X5R
402
Apple Inc. 051-9589 D
GND_AUDIO_CODEC 53 54 58 59 REVISION
R
4.18.0
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
62 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 53 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
58 53 7 IN AUD_HP_PORT_L OUT
CRITICAL
C6300 1
B 0.1UF
10%
6.3V 1
B
X5R 2
201
R6302
10K
NC AUD_HP_ZOBEL_L 1%
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
1/20W
MF
R63001 2 201
39
5%
1/20W
MF
201 2
59 58 53 IN GND_AUDIO_CODEC
R63101
39
5%
1/20W 1
MF
201 2 R6312
10K
1%
NC AUD_HP_ZOBEL_R 1/20W
MIN_LINE_WIDTH=0.30MM MF
MIN_NECK_WIDTH=0.20MM
CRITICAL 2 201
C6310 1
0.1UF
10%
6.3V 2
X5R
201
58 53 7 IN AUD_HP_PORT_R OUT
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
D D
C C
B B
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
AUDIO: IV SENSE
DRAWING NUMBER SIZE
D D
C C
B B
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
CRITICAL
1
CRITICAL CRITICAL
C6612
47UF
L6610 C6613 20%
6.3V 2 PLACE_NEAR=U6610.A1
FERR-1000-OHM 0.01UF TANT-POLY 1 C6611
CASE-A4
AUD_LO2_L_P 1 2
AUD_SPKRAMP_LIN_P 1 2 0.1UF
A1
96 53 IN 96
10%
0402
NO_TEST=TRUE CRITICAL 16V
CRITICAL 10%
2 X7R-CERM
L6611 50V PVDD 0402
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375) C6614 X7R-CERM
D GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
IN
CRITICAL
0402
NO_TEST=TRUE
10%
96 SPKRAMP_LIN_P A3 IN+
B3 IN-
WLP
OUT+ B1
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
OUT
D
50V
X7R-CERM
96 SPKRAMP_LIN_N OUT- C1
1ST ORDER FC (SUB) = NOM 9 HZ NO_TEST=TRUE
0402
A2
CRITICAL MF-LF MF-LF
402 402
2 2
57 9 PP5V_S0_AUDIO_AMP_R PLACE_NEAR=U6620.A1
CRITICAL 1
1
C6621
CRITICAL C6622 0.1UF
L6620 C6623 47UF 10%
A1
FERR-1000-OHM CRITICAL 16V
0.01UF 20% 2 X5R-CERM
6.3V 2
1 2 1 2 POLY-TANT 0201
96 53 IN AUD_LO2_R_P 96 AUD_SPKRAMP_RIN_P 2012-LLP
PVDD
NO_TEST=TRUE
0402 CRITICAL SPKRCONN_R_OUT_P
L6621
CRITICAL 10% U6620 MIN_LINE_WIDTH=0.40 MM
OUT 7 59 96
C FERR-1000-OHM
C6624
0.01UF
50V
X7R-CERM
0402
96
NO_TEST=TRUE
SPKRAMP_RIN_P A3 IN+
MAX98300
WLP
OUT+ B1
MIN_NECK_WIDTH=0.10 MM
SPKRCONN_R_OUT_N OUT
MIN_LINE_WIDTH=0.40 MM
7 59 96
C
96 53 AUD_LO2_R_N 1 2 AUD_SPKRAMP_RIN_N 1 2
MIN_NECK_WIDTH=0.10 MM
IN 96 B3 IN-
0402
NO_TEST=TRUE 96 SPKRAMP_RIN_N OUT- C1
10% NO_TEST=TRUE
CRITICAL 50V
X7R-CERM
57 AUD_SPKRAMP_SHUTDOWN_L C2 SHDN* GAIN C3 SPKR_R_GAIN
0402
B2 NC
NOSTUFF R66201
R6601 1 100K
100K PGND 5%
57 9 PP5V_S0_AUDIO_AMP_R 5% 1/16W
A2
1/20W MF-LF
MF 402 2
201 2
PLACE_NEAR=U6630.C2
1 CRITICAL 1 CRITICAL 1
C6631
CRITICAL C6635 C6632
CRITICAL 47UF 47UF 0.1UF
L6630 C6633 20% 20% 10%
16V
C2
FERR-1000-OHM 2 6.3V 2 6.3V 2 X5R-CERM
0.22UF POLY-TANT POLY-TANT CRITICAL
2012-LLP 2012-LLP 0201 SPKRCONN_SR_OUT_P
1 2 1 2
VDD OUT 7 59 96
96 53 IN AUD_LO1_R_P 96 AUD_SPKRAMP_RSUBIN_P RSUBIN_P MIN_LINE_WIDTH=0.40 MM
0402
NO_TEST=TRUE NO_TEST=TRUE U6630 MIN_NECK_WIDTH=0.10 MM
10% SSM2375
16V WLCSP
CERM B1 C3
402
IN+ OUT+
A1 B3
CRITICAL IN- OUT-
CRITICAL NO_TEST=TRUE
L6631 C6634 A2 A3
FERR-1000-OHM 57 AUD_SPKRAMP_SHUTDOWN_L SD* GAIN TP_SWR_GAIN SPKRCONN_SR_OUT_N OUT 7 59 96
0.22UF MIN_LINE_WIDTH=0.40 MM
B2 MIN_NECK_WIDTH=0.10 MM
1 2 1 2
96 53 IN AUD_LO1_R_N 96 AUD_SPKRAMP_RSUBIN_N RSUBIN_N EDGE
NO_TEST=TRUE
0402
10%
GND
C1
16V
CERM
402
B B
57 9 PP5V_S0_AUDIO_AMP_L
C2
96 53 AUD_LO1_L_P 96 AUD_SPKRAMP_LSUBIN_P LSUBIN_P POLY-TANT 2 6.3V 2 7 59 96
IN 2012-LLP POLY-TANT X7R-CERM OUT
0402
NO_TEST=TRUE NO_TEST=TRUE 2012-LLP
CRITICAL 0402
10%
VDD MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
16V
CERM
U6640
402 SSM2375
WLCSP
CRITICAL B1 C3
CRITICAL IN+ OUT+
L6641 C6644 A1 B3
FERR-1000-OHM IN- OUT-
0.22UF
OUT 7 59 96
1 2 1 2 A2 A3
96 53 IN AUD_LO1_L_N 96 AUD_SPKRAMP_LSUBIN_N LSUBIN_N 57 AUD_SPKRAMP_SHUTDOWN_L SD* GAIN TP_SWL_GAIN MIN_LINE_WIDTH=0.40 MM
NO_TEST=TRUE NO_TEST=TRUE SPKRCONN_SL_OUT_N MIN_NECK_WIDTH=0.10 MM
0402
10% B2
16V
EDGE
CERM
402
GND
C1
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
58 53 8 =PP3V3_S0_AUDIO_DIG PORT B LEFT(HEADSET MIC) AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS
HP=80HZ, LP=10.63KHZ
1
1C6795 1 C6794 1 C6755
R6762 1.0UF
20% 20%
1.0UF 1.0UF
20%
10K 10V 10V 10V
I2C PULLUPS ON SOUTHBRIDGE PAGE 5% 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
1/20W 0201-1 0201-1 0201-1 MIKEY 1A
MF
R6757 201 2 APN:353S2640
=I2C_MIKEY_SCL 1
33 2
MIKEY ADDRESS: WRITE=72H, READ=73H
44 IN
5%
L6754 MIN_LINE_WIDTH=0.20MM
A2
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM
R6758 1/20W
MF
VOLTAGE=3.42V
D 44 BI =I2C_MIKEY_SDA 1
33 2
201 AVDD
U6751
8 =PP3V42_G3H_AUDIO 1
0201
2 PP3V42_GH3_AUDIO_LC
D
5%
1/20W CD3282A1
MF WCSP CRITICAL
201 1 C6793 1 C6792 1 C6790
58 AUDIO_SCL C3 SCL MICBIAS C1 HS_MIC_BIAS NO_TEST=TRUE
1.0UF 1.0UF 1.0UF L6701
20% 20% 20% PLACE_NEAR=U6750.A1 FERR-33-OHM-0.8A-0.09-OHM
58 AUDIO_SDA B3 SDA DETECT B1 HS_SW_DET 2
10V
2
10V
2
10V 1 C6754 AUD_CONN_MIC
X5R-CERM X5R-CERM X5R-CERM 7 US_HS_MIC 1 2
0201-1 0201-1 0201-1 0.1UF
19 AUD_I2C_INT_L D3 INT* BYPASS D1 HS_RX_BP 10% 0201
OUT 16V
2 X5R-CERM
CRITICAL
AUD_IPHS_SWITCH_EN A3 ENABLE MIKEY 0201
25 IN
R67541 L6700
HS_HDET A1 HDET 1K 59 58 54 53 GND_AUDIO_CODEC 120-OHM-25%-1.3A
NOSTUFF NO_TEST=TRUE 5% 1 2
US_HS_GND AUD_CONN_SLEEVE_XW
C2 DGND
D2 AGND
1/20W 58 7 OUT
B2
R6761 CS MF MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
A1
201 2 MIN_NECK_WIDTH=0.06MM 0402 MIN_NECK_WIDTH=0.2MM
47K 1
1 C6756
59 IN AUD_PORTA_DET_L 1 2
R6755 0.01UF
10% VDD CRITICAL
5% 100K
1/20W
MF
5% 2 10V
X5R-CERM
U6750 L6702
201
1/20W
MF
0201 120-OHM-25%-1.3A
201 2 TS3A8235YFP CH_HS_GND 1 2 AUD_CONN_MIC_XW
WCSP 58 7 OUT
MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
CRITICAL MIN_NECK_WIDTH=0.06MM 0402 MIN_NECK_WIDTH=0.2MM
D4 RAMPI
GND_AUDIO_CODEC NO_TEST=TRUE CHS_CLAMPI
59 58 54 53
D3
R6751 R6752 R6753 C4
RAMPO
2
1K 1 1
2.2K 2 1
2.2K 2 CHS_CLAMPO
CLAMPI
MIKEY
CRITICAL 5% 1% 1%
B4 APN:510S0009
C6752 MIKEY
R6750
1/20W
MF
1/20W
MF
1/20W
MF NO_TEST=TRUE
CLAMPO
0.1UF 2.2K 2
201 201 201 CRITICAL CRITICAL
96 53 OUT AUD_MIC_INL_P
1 2 NO_TEST=TRUE HS_MIC_HI_RC 1 NO_TEST=TRUE HS_MIC_HI D2 MIC MIC1 B1 L6703 J6701
MIKEY MIKEY 5% MIKEY HS_MIC_LO D1 REF MIC2 C1 FERR-33-OHM-0.8A-0.09-OHM 51138-0274
10% CRITICAL 1/20W CRITICAL NO_TEST=TRUE AUD_CONN_SLEEVE F-ST-SM
6.3V
R67561 MF 1 C6751 1 C6791 CH_HS_MIC 1 2 22
C
C X5R
201
MIKEY
100K
5%
1 C6750
6800PF
201 1 C6758
27PF
10UF
20% 20%
10UF 58 IN AUDIO_SCL A3 SCL
7
0201 CRITICAL 21
CRITICAL 1/20W 10%
10V
MIKEY
5%
25V
10V
2 X5R-CERM 2 10V
X5R-CERM 58 BI AUDIO_SDA A4 SDA L6704
C6753 MF
201 2
2 X5R-X7R-CERM
0201 R6759
2 NP0-C0G
0201 58 54
0402-1 0402-1 A2 ADDR 120-OHM-25%-1.3A 1 2
0.1UF 0 53
59
GND_AUDIO_CODEC
AUD_HP_PORT_L 1 2 AUD_CONN_HP_LEFT 3 4
54 53 7 IN
GND1
GND2
1 2 1 2 MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
96 53 OUT AUD_MIC_INL_N 0402 5 6
GND MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
HS_MIC_LO_RC 5%
10%
6.3V
1/20W
MF
XW6751
SM
7 8
X5R 201 9 10
C2
B2
B3
C3
201 53 AUD_HP_PORT_REF 1 2 59
AUD_CONN_TIPDET_INV
OUT 11 12
R/C6750 FILTER TO ADDRESS OUT-OF-BAND PLACE_NEAR=U6750.D1
NOISE ISSUE SEEN ON EARLY HEADSETS 13 14
(SEE RADAR # 6210118)
IN US_HS_GND
1
R6760 IN CH_HS_GND
15 16
47K 17 18
5% 19 20
1/20W 59 58 54 53 GND_AUDIO_CODEC
MF 58 53 8 =PP3V3_S0_AUDIO_DIG
201 2
NOSTUFF 23
53 7 OUT AUD_SPDIF_OUT_JACK
24
59 58 54 53 GND_AUDIO_CODEC
CRITICAL
L6705
120-OHM-25%-1.3A
B 54 53 7 IN AUD_HP_PORT_R
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
1
0402
2
B
AUD_CONN_HP_RIGHT
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
CRITICAL
I2C ADDRESSES L6706
MIKEY U6751 READ 0111 0011 0X73 FERR-470-OHM
MIKEY U6751 WRITE 0111 0010 0X72 59 7 AUD_TYPEDET 1 2 AUD_CONN_TYPEDET
OUT
CHS U6750 READ 0111 0111 0X77 0201
CHS U6750 WRITE 0111 0110 0X76
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER SIZE
1
59 53 OUT AUD_SENSE_A 96 57 7 IN SPKRCONN_R_OUT_P
96 57 7 IN SPKRCONN_R_OUT_N 2
1 1 SPKRCONN_R_ID 3
R6896 R6895 59 7 IN
20.0K 39.2K 4
1% 1%
1/16W 1/16W 96 57 7 IN SPKRCONN_SR_OUT_P 5
MF-LF MF-LF 59 53 8 =PP5V_S4_AUDIO
402 402 96 57 7 SPKRCONN_SR_OUT_N 6
2 2 IN
AUD_PORTA_DET_L 58 AUD_PORTB_DET_L NC
SPEAKERID SPEAKERID
8
Q6897 D 6
Q6896 D 3 R68101 1
R6811
SSM6N15FEAPE SSM6N15FEAPE
100K 100K
C SOT563 SOT563
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
C
2 402
2 G S 5 G S 59 7 IN SPKRCONN_L_ID SPKRCONN_R_ID IN 7 59
1 4
AUD_OUTJACK_INSERT_L 1 1
59 IN R6812 R6813
100K 100K
1% 1%
AUD_TYPEDET_OD OUT 59 1/16W 1/16W
R6802 MF-LF
402 2
MF-LF
2 402 PORT C DETECT(SPEAKER MISMATCH)
100K 1 PP4V5_AUDIO_ANALOG
59 58 54 53 GND_AUDIO_CODEC 2 SPEAKERID SPEAKERID
1
5%
1/20W R6801 59 53 OUT AUD_SENSE_A
MF
201
3 150K
1% SPEAKERID
Q6800 1/20W
MF R6816
D
2 201 SPEAKERID
DMC2400UV 100K 2
P-CHN
SOT563 1
R68941
G
5 AUD_TYPEDET IN 7 58 1% 10K
1/16W 1%
S
MF-LF 1/16W
402 MF-LF
402 2
R6803 4
59 53 8 =PP5V_S4_AUDIO
100K 1 PP4V5_AUDIO_ANALOG 53 58 59
59 58 53 PP4V5_AUDIO_ANALOG 2 AUD_TYPEDET_OD_INV SPEAKERID
NC AUD_PORTC_DET_L
5%
1/20W 6
1 C6810
MF 0.1UF
201 C6800 1 PLACE_NEAR=Q6800.4 10%
6.3V
2 X5R
0.1UF
D 10% 201 SPEAKERID
6.3V
Q6800
N-CHN
X5R 2 Q6896 D 6
DMC2400UV 201
SOT563 G 2 AUD_TYPEDET_OD 59 SSM6N15FEAPE
B S
IN
SPEAKERID
CRITICAL
SPEAKERID
SOT563
B
U6800 L6802 SPEAKERID
MCP6514_POS 3 5 MCP6541T FERR-1000-OHM R6820 2 G S 1
1 SC70-5
GND_AUDIO_CODEC 53 54 58 59
1 1 2 33
59 8 =PP3V3_S0_AUDIO MCP6514_OUT SPKR_MATCH_DRV_R 1 2 SPKR_MATCH_DRV
R6867 4
0402 5%
0 MCP6514_NEG 1/16W
1 2 AUD_IP_PERIPHERAL_DET OUT 19 2 MF-LF
402
1
5%
R6865 1/16W
MF-LF 59 53 8 =PP5V_S4_AUDIO
47K 402 EXTRACTION NOTIFICATION
5% SPEAKERID
1/20W
MF
2 201
R68141
1 274K 59 58 54 53 GND_AUDIO_CODEC
R6866 1%
1/16W
475K AUD_OUTJACK_INSERT_L MF-LF
1% OUT 59 402 2 SPEAKERID
AUD_TIPDET_FET1
1/20W
MF R6817
2 201 45.3K2
1
APN:376S0613
1%
Q6803 SPEAKERID CRITICAL
SPEAKERID
1/16W
MF-LF
SSM6N15FEAPE
SOT563
D 6 Q6897 D 3
R68151 1 C6811
402 AUDIO CONNECTOR DETECT STATES
SSM6N15FEAPE 90.9K
SOT563 1% 4.7UF
1/16W 20% NOTHING SPDIF HEADPHONE
10V
MF-LF 2 X5R-CERM
402 2 0402 AUD_J1_TYPEDET_R 1 1 0
R6892 2 G S 1 5 G S 4 AUD_J1_TIPDET_R 0 1 1
CRITICAL
AUD_CONN_TIPDET_INV 1.5K AUD_OUTJACK_INSERT_L 1 0 0
58 IN
1 2 7 AUD_TIPDET_INV L6801 AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV
1% FERR-33-OHM-0.8A-0.09-OHM
1/16W
MF-LF 1 2 AUD_TIPDET_FET2
A 402
1
C6860
0201
1 SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
1UF C6891 PAGE TITLE
10% 25V
2 X5R 402 1UF
2 10%
X5R
25V
402
Alternate Parts AUDIO: JACK TRANSLATORS
TABLE_ALT_HEAD
REVISION
353S3452 353S1286 U6800 R
NOM R6892-C6860 FC = 106Hz 59 58 54 53 GND_AUDIO_CODEC
MAXIM ALT TO MICROCHIP
4.18.0
SSM6N15FE Vth = 0.8V to 1.5V NOTICE OF PROPRIETARY PROPERTY: BRANCH
SSM6N15FE IGSS = +/-1uA THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3) THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
68 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 59 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
MagSafe DC Power Jack F6905
6AMP-32V-0.0095OHM
1 2 =PP18V5_DCIN_CONN 8
0603
TDM LEVEL SHIFT
7 PP18V5_DCIN_FUSE
CRITICAL MIN_LINE_WIDTH=1MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
J6900
D WTB-PWR-M82
M-RT-SM
1
C6905
0.01UF
20%
D
1 2
50V
CERM =PP3V42_G3H_ONEWIREPROT 8
LAYOUT NOTE:
2 0603
TDM:MLB
3 7 TDM_ONEWIRE_MPM 1
C6908 8 =PP3V42_G3H_TDM
CRITICAL Q0220 NEEDS 10 SQ CM
4 0.1UF
K
D6970 OF 1 OZ CU FOR THERMAL
20%
5 CRITICAL 10V PLACEMENT_NOTE=PLACE NEAR U6900 and U6901 DDZ9694T
2 CERM
6 U6901 402 A SOD523 2 TDM:MLB
SMC_BC_ACOK_VCC TC7SZ08FEAPE 5 CRITICAL
SOT665
A
2 SMC_BC_ACOK IN 41 42
TDM:MPM TDM:MLB
TDM_RX_D
TDM:MLB
TDM_PD_BASE 1 Q6970
4 ZXTN619MA
1
518S0508 1 Y
C6900
0.1UF R69291 B
1 R69771 R69751 TDM:MLB
1
R6973 3
DFN
22 2.21K 24.9K
2.0K
1
20% 5% 1% 1%
10V 3 VDD
CERM 2 VCC 5% 1/20W 1/20W 1/20W
1/16W MF MF MF
402
U6900
MF-LF
402 2
201 2
TDM:MLB
201 2 U6970 2 201
MAX9940 SLG4AP030 TDM_RX
TDM:MLB
SC70-5 R6976 TDFN CRITICAL 3
7 ADAPTER_SENSE 5 EXT INT 4 SYS_ONEWIRE BI 41
SYS_TDM_ONEWIRE 1
22 2 TDM_ONEWIRE_MLB 2 IN_A OUT_C 6
TDM:MLB Q6971 1
41 BI 1 MMBT2222AM3T5G
CRITICAL
5%
4 IN_B1
R6974 TDM:MLB SOT723
1/20W OUT_D1 3 6.34K 1
R6972 2
MF 1%
NC GND 201
7 IN_B2 1/20W 54.9
OUT_D2 8 MF 1% TDM_PD_DS
2
3
1
R6912 2 201 1/20W
MF
22.1K Input impedance of 22.1K meets CRITICAL 2 201
1%
NC 1/20W sparkitecture requirements TDM:MLB TDM:MLB
MF 1 1
2 201 for 15" MBP design only GND
THRM
PAD R6971 R6970
12.1 12.1
9
1% 1%
Q6910 1/8W
MF-LF
1/8W
MF-LF
SI5419DU 2 805 2 805
1-Wire OverVoltage Protection
C The chassis ground will otherwise float and can
POWERPAK
TDM_PD_BASE_R C
5A 1
send transients onto ADAPTER_SENSE when AC is R6910
connected. 100K
D
1 5%
S
5 1/20W
MF
C6912
G
1
2 201 When input voltage is 2V the FET will be off
4 0.047UF
10% blocking the leakage path and 22.1K can be
25V
2 X5R
0402
R6911 properly detected.
1
10K 2
5%
DCIN_ISOL_GATE_R 1/20W When input voltage is at 16V+, FET will
MF
201 conduct and power charger and 3.42V reg
DCIN_ISOL_GATE
8 =PP18V5_DCIN_ISOL
K
D6910
GDZT2R6.8
6.8V Zener GDZ-0201
A
R6920 CRITICAL
47 D6905
1 2 PP18V5_DCIN_CONN_R
MIN_LINE_WIDTH=0.6 mm BAT30CWFILM
1% MIN_NECK_WIDTH=0.25 mm SOT-323
1/3W VOLTAGE=18.5V
MF 1
805
BATTERY CONNECTOR 3.425V "G3Hot" Supply
B R6905
10
3 PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm Supply needs to guarantee 3.31V delivered to SMC VRef generator
B
61 8 =PPBUS_G3H 1 2 PPBUS_G3H_R 2 VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 mm
518-0376 5% MIN_NECK_WIDTH=0.25 mm P3V42G3H_BOOST
1/8W VOLTAGE=18.5V DIDT=TRUE
CRITICAL MF-LF
805
J6950
3
C6994 1
9
NEG 22PF 348K
19 8 1%
5%
CRITICAL 1/20W
20 NEG 9 2
50V
MF
1 NP0-C0G-CERM
21 NEG 10 D6950 R6950 0201 201
2 1 C6999
1
200K
1%
1/20W
MF
201
2
3
C7090 1 C7094 1
CHGR_5V:LDO
NO STUFF 4.7UF VIN BOOST R7091
10
0.22UF CRITICAL
7
For EMC Reverse-Current Protection 10% 10% 0
35V
X5R-CERM 2
U7090 10V
2 L7095 1 2 PP5V1_CHGR_VDDP 61
FROM ADAPTER Inrush Limiter 1 C7080 0805 LT3470A
CERM
402 33UH-20%-0.39A-0.435OHM
MIN_NECK_WIDTH=0.25 mm MF-LF 5% 402
DFN 1/16W
4.7UF MIN_LINE_WIDTH=0.5 mm
D
8 =PPDCIN_S5_CHGR PPDCIN_G3H_INRUSH 8 SHDN* SW 4 P5V1_SW 1 2
10% MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.5 mm
25V 2 DP418C-SM
2 X5R-CERM MIN_NECK_WIDTH=0.25 mm BIAS MIN_NECK_WIDTH=0.25 mm CRITICAL CRITICAL
VOLTAGE=18.5V CRITICAL SWITCH_NODE=TRUE
D 1
C7085
1
R7085
0603 1
R7080 NC
7 NC DIDT=TRUE
P5V1_BIAS <Ra>
1 C7098 1 C7099 D
G
10UF 10UF
0.1UF 470K
1% 5%
100K FB 1
R7095 1 20% 20%
10% THRM 10V 10V
8 =PPDCIN_S5_CHGR_ISOL 25V 1/16W 1/16W
GND
1
C7095 681K 2 X5R 2 X5R
PAD Vout = 5.50V
3
2 X5R MF-LF MF-LF 22PF 1% 0603 0603
402 402 1/20W
9
402 2 2 5%
50V MF 100MA MAX OUTPUT
2 201
CHGR_AGATE_DIV CHGR_SGATE_DIV NP0-C0G-CERM
0201
2
(Switcher limit)
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
1
P5V1_FB
R7081 <Rb>
R7086 1 62K
332K
1%
5%
1/16W
R7096 1
1/16W MF-LF 200K
CRITICAL MF-LF
2
402 1%
402 2 1/20W
D7005 (CHGR_AGATE) (CHGR_SGATE) Vout = 1.25V * (1 + Ra / Rb)
MF
201
BAT30CWFILM 2
SOT-323
1
R7005
20 R7021
3 61 CHGR_DCIN_D_R 1 2 (CHGR_DCIN)
10
5% 1 2
2 1/16W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF-LF 5%
4 2
402 1/16W 96 CHGR_CSI_R_P R7020
1
C7020 MF-LF
0.020
Divider sets ACIN threshold at 13.55V 0.047UF
402
0.5%
10%
Sparkitecture impedance is set by R6912 in 15" MBP 10V
1W
2 X5R-CERM R7022 96 CHGR_CSI_R_N MF-LF
30mA max load 0402 3 1
0612
10
1 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
70 8 =PP3V42_G3H_CHGR MIN_NECK_WIDTH=0.1 mm 1 2 61 PP5V1_CHGR_VDDP 1/16W MIN_NECK_WIDTH=0.25 mm CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm MF-LF VOLTAGE=18.5V
5%
1/16W
MIN_NECK_WIDTH=0.2 mm 402 1
C7030 1
C7031 1
C7032 1
C7033 1
C7034 1 C7035 1 C7036 1
C7037
MF-LF
VOLTAGE=5.1V
10UF 10UF 10UF 10UF 10UF 1UF 1UF 0.001UF
402 C7001 1 C7022 1 1 C7021 20% 20% 20% 20% 20% 10% 10% 10%
35V 35V 50V
1UF 0.1UF 0.1UF 2 35V 2 35V 2 35V 2 35V 2 35V 2 X5R 2 X5R 2 X7R-CERM
NO STUFF TANT-POLY TANT-POLY TANT-POLY TANT-POLY TANT-POLY
C7002 603 603 0402
C R7012 1
1UF
10%
1
1
R7002
100K
10%
10V
X5R
402
2
10%
25V
X5R
402
2 2
10%
25V
X5R
402
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM
C
1K 10V
2 5%
19
20
X5R
1% 402 1/16W
1/16W 61 MF-LF
MF-LF 402 5
402 2 GND_CHGR_AGND 2 VDD VDDP
R7000 12 VHST CRITICAL DCIN 2 61 CHGR_DCIN CRITICAL
0 D Max Current = 8A
1
R7010 IN SMC_RESET_L 1 2 CHGR_RST_L 13 SMB_RST_N
SGATE 26 CHGR_SGATE Q7030
130K 5% 44 IN =SMBUS_CHGR_SCL 11 SCL U7000 4 G RJK0332DPB-01 (L7030 limit)
1% 1/16W
=SMBUS_CHGR_SDA 10
AGATE 1 CHGR_AGATE 1
C7025 LFPAK-SM
1/16W MF-LF 44 BI SDA TQFN
0.22UF
CSIP 28 94 CHGR_CSI_P f = 400 kHz
ISL6259
MF-LF 402
2 402 70 IN CHGR_VFRQ 4 VFRQ 10%
10V
CSIN 27 94 CHGR_CSI_N 2 CERM S
CHGR_CELL 6 CELL CRITICAL CRITICAL
402
L7030 TO SYSTEM
CHGR_ACIN 3 ACIN
BOOT 25 CHGR_BOOT DIDT=TRUE
PLACE_NEAR=U7000.25:2mm
1 2 3 4.7UH-20%-14.5A-9MOHM
F7040
UGATE 24 CHGR_UGATE GATE_NODE=TRUE DIDT=TRUE 8AMP-32V-0.006OHM
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CHGR_ICOMP 5 ICOMP PHASE 23 CHGR_PHASE 1 2 1 2 =PPBUS_G3H 8 60
1
R7011 CHGR_VCOMP 7 VCOMP
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm PIME173T-SM
40.2K CHGR_VNEG 8
LGATE 21 CHGR_LGATE GATE_NODE=TRUE DIDT=TRUE SWITCH_NODE=TRUE 0603
1% VNEG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
1/16W 1 CHGR_CSO_P 18 16 CHGR_BGATE
152S1466 CRITICAL
MF-LF R7015 94 CSOP BGATE
2 402 330K 94 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON OUT 46
F7041
5% 8AMP-32V-0.006OHM
THRM_PAD
1
(OD) ACOK 14 =CHGR_ACOK OMIT_TABLE
2 402 OUT 42 45 MIN_LINE_WIDTH=0.6 mm
PGND
MIN_NECK_WIDTH=0.25 mm
1UF VOLTAGE=12.6V CRITICAL 0603
CHGR_VCOMP_R 10%
16V 5
1
C7040 1
C7045
2 X5R 68UF 0.001UF
29
22
402 10%
1
353S2392 CRITICAL 20%
50V
C7015 2 16V
POLY-TANT
2 X7R-CERM
220PF Q7035 CASE-D2E-SM 0402
10% 4
50V RJK0305DPB CRITICAL CRITICAL
X7R-CERM 2
LFPAK-HF
0402 R7050 Q7055
0.005
SI7137DP
B 1
R7042
0
1%
1W
MF
SO-8
TO/FROM BATTERY B
5% R7016 1 0612
S
1/16W XW7000 1 2 3 2 1 PPVBAT_G3H_CHGR_R
3.01K
3
MF-LF SM MIN_LINE_WIDTH=0.6 mm
D
4 3 PPVBAT_G3H_CONN
2 402 1% MIN_NECK_WIDTH=0.2 MM 7 60
2
1 2 (GND)
5
1/16W VOLTAGE=12.6V 1 1 MIN_LINE_WIDTH=0.6 mm
MF-LF C7055 1
C7056 C7057 MIN_NECK_WIDTH=0.25 mm
1
402
2 PLACE_NEAR=U7000.29:1mm 1UF 0.1UF 0.01UF VOLTAGE=12.6V
PLACE_NEAR=U7000.22:1mm
G
10% 10% 10%
CHGR_VNEG_R 25V 16V 16V
X5R 2 X7R-CERM 2 X7R-CERM 2
4
603-1 0402 0402
1
C7016 (CHGR_CSO_P) R7051 2.2 1 2 96 CHGR_CSO_R_P
5% 1/16W MF-LF 402
470PF
10% (CHGR_CSO_N) R7052 0 1 2 96 CHGR_CSO_R_N
50V 5% 1/16W MF-LF 402
2 CERM
0402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
1
C7042 C7011 1 1
C7000 C7005 1 C7026 1
NO STUFF
0.068UF 0.01UF 1UF 0.22UF 0.001UF CRITICAL
10% 10% 10% 10% 10%
2
10V
X5R-CERM
16V
X7R-CERM 2 2
10V
X5R
50V
X5R-CERM 2
50V
X7R-CERM 2 R7055
0402 0402 402-1 0603-1 0402 0.001
61 GND_CHGR_AGND 1%
MIN_LINE_WIDTH=0.2 mm 1W
MIN_NECK_WIDTH=0.2 mm MF
VOLTAGE=0V 0612
2 1
4 3
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
D D
8 =PPVIN_S0_VCCSAS0
8 =PP5V_S0_VCCSAS0
PLACE_NEAR=Q7100.2:1.5mm
VCCSAS0_BOOT_RC
MIN_LINE_WIDTH=0.3 mm CRITICAL CRITICAL
MIN_NECK_WIDTH=0.2 mm
R7101 1
1
C7101 DIDT=TRUE C7119 1
C7120 1
C7121 1 1
C7122
2.2 10UF 10UF 10UF 0.1UF 1000PF
20% 20% 20% 10% 5%
5% 25V 25V 25V
1/16W 2
10V
X5R 1
1
C7130 X5R-CERM 2 X5R-CERM 2
16V
X7R-CERM 2 2 NP0-C0G
MF-LF
402
603 R7130 0.22UF 0603 0603 0402 402
2 0 10%
10V
5% 2 CERM
PP5V_S0_VCCSAS0_VCC 1/10W 402
MIN_LINE_WIDTH=0.6 mm MF-LF
MIN_NECK_WIDTH=0.2 mm 603
2
VOLTAGE=5V
19
20
VCC PVCC VCCSAS0_VBST
MIN_LINE_WIDTH=0.3 mm 376S0944
U7100 MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
2
CRITICAL
C =PVCCSA_EN 15
EN
ISL95870AH
UTQFN
BOOT 18
VCCSAS0_DRVH
Q7100
RJK0222DNS CRITICAL
CRITICAL
R7140
C
R7151 70 IN MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 0.001
CPU_VCCSASENSE 1
1.62K
2 CPU_VCCSASENSE_DIV 10 CRITICAL 17 GATE_NODE=TRUE 1 HWSON L7100 1%
1W =PPVCCSA_S0_REG
89 13 IN FB UGATE DIDT=TRUE 1.0UH-7A MF-1
8 99
1% 0612
1/16W VCCSAS0_SREF 7
SREF PHASE 16 VCCSAS0_LL 7 1 2 PPVCCSA_S0_REG_R 2 1
MF-LF MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
402
VCCSAS0_VO 12 1 MIN_NECK_WIDTH=0.2 mm PIMB053T-SM MIN_NECK_WIDTH=0.2 mm 4 3 6A Max Output
1 VO LGATE SWITCH_NODE=TRUE VOLTAGE=1.05V
R7147 DIDT=TRUE
152S1302 f = 300 kHz
41.2K VCCSAS0_OCSET 11
OCSET 6
1%
1/16W 14
R7153 MF-LF 70 OUT PVCCSA_PGOOD PGOOD
1.62K 2 402
VCCSAS0_RTN 1 2 VCCSAS0_RTN_DIV 4 VCCSAS0_DRVL
RTN 3 4 5
MIN_LINE_WIDTH=0.6 mm
1% 13 MIN_NECK_WIDTH=0.2 mm
1/16W VCCSAS0_FSEL FSEL GATE_NODE=TRUE
MF-LF DIDT=TRUE
402 8
VCCSAS0_SET0 SET0
2 C7103 1
0.022UF VCCSAS0_SET1 9
SET1
XW7101 10%
SM 16V
2 6
X5R-X7R-CERM 1
1
0402 R7148 VID0
52.3K 5 (ENDIAN SWAP)
1%
1/16W
R7103 1 VID1
96 45 VCCSAS0_CS_P
MF-LF 0
2 402
1
C7102 5%
96 45 VCCSAS0_CS_N
1/16W
2.2UF GND PGND 1
10%
MF-LF
402
R7141
16V 2 1.5K
2
2 X5R
R7150 603 1%
1/16W
82.5K MF-LF C7140
1 2 402 2
1000PF
1%
1/16W 89 13 IN CPU_VCCSA_VID<1> 2 1
MF-LF
402 89 13 CPU_VCCSA_VID<0>
B 1 C7106
10PF
1
R7154
4.64K
1
R7152
4.64K
1 C7105
10PF VCCSAS0_SET_R
IN 5%
25V
NP0-C0G
1
R7142 B
5% 1% 1% 5%
402 1.5K
50V 1/16W 1/16W 50V 1 1% OCP = R7141 x 8.5uA / R7140
2 C0G-CERM MF-LF MF-LF 2 C0G-CERM R7149 1/16W
0402 2 402 2 402 0402 499K (VCCSAS0_OCSET)
MF-LF
OCP = 8.5A
1% 2 402
1/16W
MF-LF (VCCSAS0_VO)
2 402
XW7100
SM
VCCSAS0_AGND 1 2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PLACE_NEAR=U7100.3:1mm
INTEL TABLE:
VID1 VID0 Voltage fb = (R7151+R7152)/R7152 = 1.349 and Vref = 0.5;
VID1=1, VIC0=1:
0 0 0.9V
Vout<1,1> = Vref x fb;
1 0 0.8V VID1=0, VID0=1:
Vout<0,1> = Vref x (1+R7147 / (R7148 + R7149 )) x fb
0 1 0.725V
VID1=1, VID0=0
Vout<1,0> = Vref x (1+ (R7147 + R7148) / R7149 )) x fb
1 1 0.675V
VID1=0, VID0=0
Vout<0,0> = Vref x (1+ (R7147 / (R7148 + R7149 // R7150 )) x fb
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
D D
63 8 =PP5V_S4_REG
8 =PPVIN_S5_P5VP3V3
R72011
23
29
22
13
VOUT = 5.0V C7201 C7203 VOUT = 3.3V
2
1 1
SKIP_5V3V3:AUDIBLE
0
1
0.22UF 2.2UF
R72001
V5SW
VIN
VREG5
VREG3
VREF2
1 5%
11A MAX OUTPUT 152S0688 MIN_LINE_WIDTH=0.6 MM
0
1/20W 10%
10V
20%
10V MIN_LINE_WIDTH=0.6 MM CRITICAL 152S0754 10A MAX OUTPUT
MIN_NECK_WIDTH=0.2 MM MF CERM 2 2 X5R-CERM MIN_NECK_WIDTH=0.2 MM
CRITICAL 5% 201 2 C7264 1
Q7260 CRITICAL
F = 400 KHZ 1
C7224 1/20W 402 402
F = 400 KHZ
CRITICAL
L7220 CRITICAL 0.1UF MF
201 2 6 SKIPSEL1
0.1UF
10%
RJK0214DPA
2 WPAK2
L7260
NOSTUFF 1.0UH-21A-0.006OHM 10%
CRITICAL 50V 1.0UH-22A CRITICAL
PCMB103T-1R0MS Q7220 2
50V
R7244 1 P5VP3V3_SKIPSEL 19 SKIPSEL2 X7R 2
PCMC063T-SM
1
C7253 1
C7271 CSD58872Q5D
X7R
U7201 R7263
603-1
C7272 1
C7293 1
C 20%
150UF 0.001UF
10%
2
1 VIN SON5X6
TG 3
603-1
P5VS4_TG
1
5%
1/16W
14 OCSEL
QFN
EN 12 =P5VS5_EN IN 70
1
0
2 P3V3S5_TG
0.001UF
10%
150UF
20%
C
TPS51980
50V 50V
2 6.3V 2 X7R-CERM MIN_LINE_WIDTH=0.6 MM MF-LF MIN_LINE_WIDTH=0.6 MM
1 X7R-CERM 2 6.3V 2
POLY-TANT P5VS4_VBST 31 VBST1 VBST2 P3V3S5_VBST POLY-TANT
2
MIN_NECK_WIDTH=0.2 MM 402 26 5% MIN_NECK_WIDTH=0.2 MM
CASE-B2-SM 0402 P5VS4_VSW 6 VSW DIDT=TRUE 2
DIDT=TRUE DIDT=TRUE 1/16W DIDT=TRUE
0402 CASE-B2-SM
CRITICAL CRITICAL CRITICAL MIN_LINE_WIDTH=0.6 MM
7 TGR 4 MF-LF GATE_NODE=TRUE
7
CRITICAL
MIN_NECK_WIDTH=0.2 MM P5VS4_DRVH 1 DRVH1 DRVH2 24 P3V3S5_DRVH 402
C7254 1 C7252 1
C7250 1
DIDT=TRUE
8 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1
C7290 1
C7292
150UF 330UF 10UF P5VS4_LL 32 SW1 SW2 25 P3V3S5_LL 10UF 330UF
PLACE_NEAR=L7220.1:3MM
PLACE_NEAR=L7260.2:3MM
20% 20% 20%
20%
10V NO STUFF MIN_LINE_WIDTH=0.6 MM SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 MM NO STUFF 6.3V
20%
6.3V 2 6.3V 2 2 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 2 2 6.3V
X5R 1 BG 5 P5VS4_DRVL P3V3S5_DRVL 6 X5R
POLY-TANT
CASE-B2-SM
POLY-TANT
CASE-D3L-SM 805 R7299 MIN_LINE_WIDTH=0.6 MM GATE_NODE=TRUE DIDT=TRUE
30 DRVL1 DRVL2 27
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM
R7298 1 603
POLY-TANT
CASE-D3L-SM
1 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 10
5% PGND P5VS4_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2 5%
1/10W 1/10W
P5VS4_CSN1 P3V3S5_CSN2
9
8 CSN1 CSN2 17
MF-LF
603
C7218 C7288 3 4 5
MF-LF
603
2 2
0.1UF 0.1UF
PLACE_NEAR=L7260.1:3MM
PLACE_NEAR=L7220.1:3MM
PLACE_NEAR=L7220.2:3MM
PLACE_NEAR=L7260.2:3MM
11 MODE RF 3 P3V3S5_RF
P5VS4_SNUBR 1 2 1 2 P3V3S5_SNUBR
MIN_LINE_WIDTH=0.6 MM P5VS4_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
10%
16V
P5VS4_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 10%
16V
DIDT=TRUE
X7R-CERM
R7206 1
X7R-CERM
2 NO STUFF NO STUFF 2
0402
70 IN =P5VS4_EN 4 EN1 EN2 21 =P3V3S5_EN IN 70
0402
XW7222 C7299 1
P5VS4_PGOOD 5 P3V3S5_PGOOD
249K 1
C7298 XW7262
SM 0.0033UF R7247 70 OUT PGOOD1 PGOOD2 20
OUT 70 1%
R7246 0.001UF SM
1/16W
10% 3.24K 1.43K 10%
50V GND THRM_PAD MF-LF 50V
1 2 1 2 402 1 2 2 1
X7R-CERM 2 X7R-CERM
28
0402 0402
33
1% 1%
P5VS4_VFB1_R 1/16W 1/16W P3V3S5_VFB2_R
2 2 R7256 1 MF-LF
402 1 R7236 1 1
R7238 R7239 1 MF-LF
402
1
R7216 2 2
GND_5V3V3_AGND
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PPVIN_S3_DDRREG
OMIT_TABLE OMIT_TABLE
CRITICAL CRITICAL
C7330 1
C7331 1 1 C7332 1 C7333 1
C7334
68UF 68UF 1UF 0.001UF 1UF
20% 20% 10% 10% 10%
16V 2 16V 2 25V 50V 25V
2 X5R 2 X7R-CERM 2 X5R
POLY-TANT POLY-TANT
=PPVIN_S0_DDRREG_LDO CASE-D2E-SM CASE-D2E-SM 603-1 0402 603-1
8
8 =PP5V_S3_DDRREG
C7301 1
10UF
20%
10V
C7300 1 X5R 2
R7330
10UF
603
1
1 2
(DDRREG_DRVH) DDRREG_DRVH_R
20%
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
10V 5%
X5R 2 MIN_NECK_WIDTH=0.17 mm MIN_NECK_WIDTH=0.17 mm
1/16W
603 MF-LF
402
2
C VLDOIN
MIN_NECK_WIDTH=0.17 mm
C7325
0.1UF
CRITICAL
Q7330
C
V5IN 1 2
12 VBST 15 DDRREG_VBST MIN_LINE_WIDTH=0.6 mm CSD58872Q5D
DRVH 14 DDRREG_DRVH SON5X6 VIN 1 CRITICAL
U7300 GATE_NODE=TRUE DIDT=TRUE
10% 3 TG
27 9 IN =DDRVTT_EN (VTT Enable) 17 S3 SW 13 DDRREG_LL 50V
X7R
L7330
TPS51916 SWITCH_NODE=TRUE DIDT=TRUE
603-1 VSW 6 0.68UH-18A-3.3MOHM
70 IN =DDRREG_EN (VDDQ/VTTREF Enable) 16 S5 QFN
DRVL 11 DDRREG_DRVL (DDRREG_LL)
4 TGR 7 1 2 =PPDDR_S3_REG 8
DDRREG_1V8_VREF 6 VREF GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
8 PCMB103T
CRITICAL PGOOD 20 DDRREG_PGOOD
OUT 88 MIN_NECK_WIDTH=0.17 mm CRITICAL Vout = 1.5V
1
1
OMIT_TABLE VDDQSNS 9 DDRREG_VDDQSNS DDRREG_VSW 152S0905 C7340 18A max output
R7315 33 DDRREG_FB 8 REFIN 5 BG SWITCH_NODE=TRUE
C7315 1
VTT 3 8 =PPVTT_S0_DDR_LDO XW7360 (DDRREG_DRVL) DIDT=TRUE 270UF (Q7335 limit)
0.1UF 20.0K SM MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm 20%
1
10%
1% DDRREG_MODE 19 MODE VTTSNS 1
DDRREG_VTTSNS 1 2
MIN_NECK_WIDTH=0.17 mm
PGND
MIN_NECK_WIDTH=0.17 mm 2 2V
TANT
C7346 f = 400 kHz
1/16W
16V
2 MF-LF DDRREG_TRIP 18 TRIP PLACE_NEAR=C7361.1:3mm CASE-B4-SM 0.001UF
X7R-CERM 10%
9
402 =PPVTT_S3_DDR_BUF 8 33
0402 2 50V
VTTREF 5 CRITICAL 2 X7R-CERM
10mA max load
0402
C7341 1 1
C7345 2
21
TANT
150K 100K 0.01UF 1
6.3V
X5R 2 2
6.3V
X5R
CASE-B4-SM 603
1 PLACE_NEAR=C7340.1:1MM
1%
1/16W
1%
1/16W
10%
1
R7317 R7318 603 603
MF-LF MF-LF 2
16V
X7R-CERM 200K 61.9K PLACE_NEAR=C3101.1:1mm PLACE_NEAR=C3101.1:3mm
402 2 2
402 0402 1% 1%
1/16W 1/16W
DDRREG_P1V35_L MF-LF MF-LF C7360, C7361 close to memory
2
402
2 402 C7350 1
Q7319 2
0.22UF
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
SSM3K15FV D 3 XW7300 10%
MIN_NECK_WIDTH=0.17 mm
SOD-VESM-HF SM 10V
CERM 2
402
NOSTUFF 1
PLACE_NEAR=U7300.7:1mm
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
1 G S 2 MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
B B
MEM_VDD_SEL_1V5_L IN 18
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
D =PP5V_S0_CPUIMVP 8 66 D
R7401
1
10 2
PP5V_S0_CPUIMVP_VCC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM 5%
VOLTAGE=5V 1/16W
MF-LF =PPVIN_S0_CPUIMVP 8 66
402
8 =PPVCCIO_S0_CPUIMVP 1
C7402 1
C7403
C7401 1 2.2UF 2.2UF
20% 20%
2.2UF 2
10V
2
10V
20% X6S-CERM X6S-CERM
10V 0402 0402
2
R74791 1
R7480 X6S-CERM
0402
54.9 130
1% 1%
1/20W 1/20W PLACE_NEAR=U7400.24:2mm
MF MF
201 2 2 201 PLACE_NEAR=U7400.15:2mm
VCC 46
29
19
PLACE_NEAR=U7400.18:2mm PLACE_NEAR=U7400.16:2mm
SIGNAL_MODEL=EMPTY
VDDA
VDDB
R7406
R7403 300
182K 2 1 2 CPUIMVP_ISNS1_P IN 46 66 97
U7400 1
1%
MAX15119GTM 1% 1/20W
QFN 1/20W MF
66 OUT CPUIMVP_AXG_PWM2 13 DRVPWMB TONB 1 CPUIMVP_TONB MF
R7402 201
201
182K 2 R7407
66 OUT CPUIMVP_PWM3 37 DRVPWMA TONA 48 CPUIMVP_TONA 1
300
1% 1 2 CPUIMVP_ISNS2_P 46 66 97
CPUIMVP_ISUM3P 45 BSTA1 25 CPUIMVP_BOOT1 1/20W IN
66 65 IN CSPA3 CRITICAL OUT 66
MF
SIGNAL_MODEL=EMPTY
1%
89 42 41 11 OUT CPU_PROCHOT_L 4 VRHOT* DHA1 27 CPUIMVP_UGATE1 OUT 66 201 1/20W
CSNB 10
FBB 6 CPUIMVP_FBB 65
GNDSA
GNDSB
PGNDA
PGNDB
THRM
PAD
1 1 AGND CPUIMVP_ISUM3P 65 66
CRITICAL CRITICAL
1 1 1
5
20
49
30
17
NO STUFF NO STUFF NO STUFF
R7469 R7467 R7465 R7463 R7461 NO STUFF NO STUFF NO STUFF NO STUFF
CPUIMVP_ISUMGN 66
1 IN
200K 137K 137K 1
C7418 1
C7419 1
C7414 1
C7415 1
C7416 1
C7417 C7410
100KOHM 100KOHM 1% 1% 1% XW7400 100PF 100PF 100PF 100PF 100PF 100PF 100PF
1/20W 1/20W 1/20W SM
0402 0402 5% 5% 5% 5% 5% 5% 5%
MF MF MF
B 2 2 2
201
2
201
2
201 2 1 2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
B
GND_CPUIMVP_SGND
MIN_LINE_WIDTH=0.6 mm
PLACE_NEAR=Q7510.1:7mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C7473
PLACE_NEAR=Q7550.1:6mm 1
C7440 100PF SIGNAL_MODEL=EMPTY
1000PF 1 2
10%
16V
1
C7412
2 X7R-CERM R7440 5% 1000PF
SIGNAL_MODEL=EMPTY
0201
10 25V 10%
CPU_AXG_SENSE_R 1 2 CPU_AXG_SENSE_N 13 89
NP0-CERM 2
16V
IN 0201 X7R-CERM
1% R7412 0201 R7413
66 IN CPUIMVP_ISUMG_AVEP 1
C7441 1/20W
MF CPUIMVP_FBA 1
12.1K
2 CPUIMVP_FBA_R 1
10
2 CPU_VCCSENSE_P
65 IN 13 89
1000PF 201
10% 1% 1%
16V 1/20W 1/20W
2 X7R-CERM MF MF
0201 R7441 201 SIGNAL_MODEL=EMPTY 201
SIGNAL_MODEL=EMPTY 10
CPU_VCCSENSE_R 1 2 CPU_VCCSENSE_N IN 13 89
1%
C7422 1
1/20W 1000PF
NO STUFF NO STUFF 10%
MF
16V
1
C7442 1
C7443 201
X7R-CERM 2
1000PF 1000PF R7422 0201 R7423
10% 10% 16.2K 10
16V 16V CPUIMVP_FBB 1 2 CPUIMVP_FBB_R 1 2 CPU_AXG_SENSE_P
2 X7R-CERM 2 X7R-CERM 65 IN 13 89
0201 0201 1% 1%
1/20W 1/20W
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY MF MF
201 201
A SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
5
6
7
8
CRITICAL 68UF 68UF CRITICAL 68UF 68UF
376S1010 20% 20% 10% 10% 10% 20% 20% 10% 10% 10%
PHASE 1 D Q7510
IRF6802SDTRPBF
2
20%
16V
POLY-TANT
CASE-D2E-SM
2
20%
16V
POLY-TANT
CASE-D2E-SM
2
16V
X6S-CERM
0603
2
16V
X6S-CERM
0603
2
16V
X6S-CERM
0402
2
50V
X7R-CERM
0402
2
50V
X7R-CERM
0402
PHASE 2 376S1010
D Q7510
IRF6802SDTRPBF
2
20%
16V
POLY-TANT
CASE-D2E-SM
2
20%
16V
POLY-TANT
CASE-D2E-SM
2
16V
X6S-CERM
0603
2
16V
X6S-CERM
0603
2
16V
X6S-CERM
0402
2
50V
X7R-CERM
0402
2
50V
X7R-CERM
0402
3
1% 1%
1W 1W
0.36UH-20%-36A-0.00108OHM 0.36UH-20%-36A-0.00108OHM
D R7511
1
1
1 2 PPVCORE_S0_CPU_PH1 1
MF
0612
2 =PPVCORE_S0_CPU_REG 8
R7521
1
1
1 2 PPVCORE_S0_CPU_PH2 1
MF
0612
2 =PPVCORE_S0_CPU_REG 8 66
D
C7511 PIMS103T-SM
MIN_LINE_WIDTH=0.6 MM 3 4
66 C7521 PIMS103T-SM
MIN_LINE_WIDTH=0.6 MM 3 4
0 0.22UF NOSTUFF
MIN_NECK_WIDTH=0.25 MM 0 0.22UF NOSTUFF
MIN_NECK_WIDTH=0.25 MM
5% 10% 1 152S1538 VOLTAGE=1.25V 5% 10% 1 152S1538 VOLTAGE=1.25V
1/16W 16V R7512 97 46 CPUIMVP_ISNS1_N 1/16W 16V R7522 97 46 CPUIMVP_ISNS2_N
MF-LF 2 CERM 97 65 46 CPUIMVP_ISNS1_P MF-LF 2 CERM 97 65 46 CPUIMVP_ISNS2_P
NC
NC
402 2 402
2.2 1 1
402 2 402
2.2 1 1
NC
NC
5% R7513 R7514 5% R7523 R7524
1/10W 1/10W
MF-LF 46.4 10 65 IN CPUIMVP_BOOT2 MF-LF 46.4 10
603 2 1% 1% MIN_LINE_WIDTH=0.25 MM DIDT=TRUE 603 2 1% 1%
65 IN CPUIMVP_BOOT1 1/20W 1/20W MIN_NECK_WIDTH=0.2 MM 1/20W 1/20W
1
2
8
7
MIN_LINE_WIDTH=0.25 MM MF MF MF MF
1
2
8
7
DIDT=TRUE CPUIMVP_UGATE2
MIN_NECK_WIDTH=0.2 MM 201 2 201 65 IN 201 2 201
CPUIMVP_PH1_SNUB 2
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE CRITICAL CPUIMVP_PH2_SNUB 2
CPUIMVP_UGATE1 D CPUIMVP_ISUMN
65 IN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
GATE_NODE=TRUE
D CRITICAL
Q7515
DIDT=TRUE
NOSTUFF
CPUIMVP_ISUMN 65 66 65 IN
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_PHASE2
GATE_NODE=TRUE
Q7525 DIDT=TRUE
NOSTUFF
65 66
3
5
6
0201
5
6
3
CPUIMVP_ISUM2P 65
CPUIMVP_ISUM1P 65
Additonal Input Bulk Caps (D SIZE)
CRITICAL OMIT_TABLE OMIT_TABLE THESE TWO CAPS ARE FOR EMC
CRITICAL CRITICAL CRITICAL CRITICAL OMIT_TABLE
Q7530 1
C7533 1
C7534 1
C7535 1
C7536 1
C7537 1
C7538 1
C7539
CRITICAL OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL CRITICAL
OMIT_TABLE
CRITICAL CRITICAL
649136PBF 1
S1 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF C7570 1 1 1 1 1
PHASE 3 D
1
2 2
20%
16V
POLY-TANT
2
20%
16V
POLY-TANT
2
20%
16V
X6S-CERM
0603
2
20%
16V
X6S-CERM
0603
2
10%
16V
X6S-CERM 2
0402
10%
50V
X7R-CERM
0402
2
10%
50V
X7R-CERM
0402 2
68UF
20%
16V
C7571
68UF
20%
C7572
68UF
20%
C7574
15UF
20%
C7575
68UF
20%
C7578
15UF
20%
376S1014 5
CASE-D2E-SM CASE-D2E-SM POLY-TANT 2 16V 2 16V 2 16V 2 16V 2 16V
CASE-D2E-SM POLY-TANT POLY-TANT TANT POLY-TANT TANT
CRITICAL CASE-D2E-SM CASE-D2E-SM SM CASE-D2E-SM SM
4 G 6
66 65 8 =PP5V_S0_CPUIMVP CPUIMVP_BOOT3_RC R7530
MIN_LINE_WIDTH=0.25 MM 3 S CRITICAL 0.00075
C 1
C7541
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUE
L7530
0.36UH-20%-36A-0.00108OHM
1%
1W
MF
C
1UF CPUIMVP_PHASE3_L PPVCORE_S0_CPU_PH3 0612
1
R7547
10%
16V
1 2 1 2 =PPVCORE_S0_CPU_REG 8 66
1 MIN_LINE_WIDTH=0.6 MM
5
1
2
8
7
66
SKIP* DH 8 CPUIMVP_UGATE3 603 2 201 2 MF MF
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE 201 2 201 15UF 15UF
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE CRITICAL CPUIMVP_PH3_SNUB 2 20% 20%
LX 7 D CPUIMVP_ISUMN 2 16V 2 16V
CPUIMVP_PHASE3
DIDT=TRUE
Q7535 DIDT=TRUE
NOSTUFF 65 66 TANT
SM
TANT
SM
DL 4
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE 649135PBF 1
C7532
THRM CPUIMVP_LGATE3 4 G DIRECTFET_S3C 0.001UF
GND PAD 10% 1
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE
376S1011 50V C7583
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE S 2 330PF
3
X7R-CERM
0402 10%
16V
2 X7R-CERM
0201
3
5
6
CPUIMVP_ISUM3P
AXG PHASE 1 65
R7556
AXG PHASE 2 1
CRITICAL
C7560 1
CRITICAL
C7561 1
CRITICAL
C7562
10UF
1
CRITICAL
C7563
10UF
1
C7564
1UF
1
C7565
0.001UF
1
C7566
0.001UF
0 68UF 68UF
1 2 CPUIMVP_BOOT1G_R 20% 20% 20%