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The shift register we discussed earlier can be converted into a simple counter
by connecting the output of its last stage to the input of its first stage. Initially,
we set the first stage to 1 and clear the rest of the stages (set to 0). Each clock
pulse then shifts the 1 along to the next stage until it reaches the last stage. At
this point the next clock pulse loads the 1 back into the first stage. Such a
counter that contains n-stages is called a modulo-n ring counter.
Notice that this counter is not a binary counter. It does not count in a binary
count sequence.
Although less efficient than other counters the output of the ring counter can
be decoded without the use of decoding gates such as the previous slide
Ring Counters
Q0 Q1 Q2 Q3
D Q D Q D Q D Q
CLK C C C C
Count Q3 Q2 Q1 Q0
T1 T2 T3 T4 T5 T6 0 0 0 0 1
1
CLK 1 0 0 1 0
0
1
Q0 2 0 1 0 0
0
1 3 1 0 0 0
Q1
0 4 0 0 0 1
1
Q2
0
1
Q3
0
Figure 3.20 shows an example of a modulo-4 ring counter, the timing waveforms and a count table.
Introduction to HCPLDs
All our working in digital electronics up until now
has dealt with digital logic gates and devices
themselves, that is, how they operate and perform
https://www.altera.com/download/software/quartus-
ii-we
Topic
Description
Example
AHDL Example – Truth Tables
Alternatively we can use the Index of Digital Systems,
Ronald J. Tocci and Search for Truth Tables, using
AHDL 181-182
AHDL Example – Truth Tables
The AHDL solution:
Figure 4-11. c) Ronald J. Tocci Digital Systems, Principles and Applications, pg 134
AHDL Example – Truth Tables
Define 4 Inputs
Define 1 Output
Truth table