Area Optimization of CMOS Full Adder Design Using

3T XOR
Somashekhar Malipatil Vikas Maheshwari Marepally Bhanu Chandra
Research Scholar, Department of ECE Department of ECE Department of ECE
Sri Satya Sai University of Technology & Bharat Institute of Engineering & Koneru Lakshmaiah Education Foundation,
Medical Sciences(SSSUTMS),Sehore(MP), India Technology, Hyderabad, India Hyderabad, India
somashekhar49@gmail.com maheshwarivikas1982@gmail.com mbhanu.iiit@gmail.com

Abstract –GDI (Gate Diffusion Input) is a new technique

of low power digital circuit design is proposed. This technique Pd= αcv2f …………………….1
allows minimization of area and power consumption of digital Where α=switching activities
circuits. In this design XOR gate is designed using 3 C=capacitance
transistors and CMOS full adder is designed based on two 3T V=supply voltage
XOR and one 2T Mux. Using 8 transistors the full adder is f=frequency
designed in this paper and voltage scaling also done by In this design, dynamic power is minimized by reducing
reducing supply voltage. In this proposed full adder, the power switching activity and supply voltage 1.2V.
consumption 4.604µW is achieved and the total area is
144µm2.
III. CMOS 8T FULL ADDER DESIGN
Keywords–Low Power, Area, Full adder GDI, 3T XOR,
2T MUX, CMOS, 120nm Technology, Logic Gates,
Microwind 2, DSCH 2.

I. INTRODUCTION
With Increasing demand for reliable battery life of
digital devices is also demanding for low power
consumption digital devices. It has become the major
focussed work for designers to design such digital
devices in order to meet the requirements of the latest
advancements of the technology as these devices mostly
include phones, laptops, sensor nodes[1]. Fig.1 Simplified Full adder using Mux
Significant parameters for designing any integrated
circuit are area and power dissipation. Whenever
technology scales from µm to nm, the Vth of transistors is
also minimized this leads to sub threshold leakage current
to increase exponentially.

II. PROPOSED METHODOLOGY-GDI

GDI approach allows implementation of a wide range of
complex logic functions using only two transistors. This
method is suitable for design of fast, low power circuits,
using reduced number of transistors. The dynamic power
is expressed as shown in equation 1.
Fig.2 3T XOR using GDI

978-1-7281-5284-4/20/$31.00 ©2020 IEEE

The logic diagram of full adder is shown in fig.1 and it
consists 2 XOR gates and one 2:1 Mux. In this paper the
CMOS XOR gate is designed using 3 transistors based
on GDI technique is shown in fig.2. When any one of
the input is high, the output will become high. For
example in the fig.2 the inputs a=1, b=0 and output will
become 1.

Fig.5 3T XOR 3D process

The fig 5 shows the 3T XOR 3D process. To create IC

3D process, it takes many process steps including initial
substrate, diffusion formation, and oxide growth.

Fig.3 2T based 2:1 Mux using GDI

The 2T based 2:1 Multiplexer is shown in figure 3.
When select line sel=0, the output will select ‘a’ and
when select line sel=1, the output will sect ‘b’. The 2:1
Multiplexer is designed using 2 transistors based on GDI
technique is shown in fig.3.

Fig.6 8T Full adder 3D process

IV. RESULTS

Fig.4 8T Full Adder using GDI

The proposed 8 transistor full adder using GDI technique

is shown in fig.4. In this full adder 2 XOR gates and one
Fig.7 Simulation of Full adder in DSCH 2
2:1 Mux is used to design full adder. The fig.4 shows
full adder when all the 3 inputs are high, the outputs
sum=1 and carry=1.
 Fig. 11 Cgs and Cgd characteristics with respect to Vds
Fig.8 Simulation result of 3T XOR in DSCH 2

S.No. Supply Power

Voltage Consumption
1 1.8V 10.062µW
2 1.2V 6.488µW
3 1.0V 4.604µW

Table 1: Power Analysis of proposed full adder with

voltage scaling
Area Analysis: the proposed full adder layout width is
20µm and length is 7µm. The total area is 144µm2.

Fig. 9 Ids Vds Characteristics Proposed Mayur C.H.

Parameter
work Agarwal[3] Chang[5]
In the figure 9, the BSIM4 model is used to analyze the Power
Consumption 4.604 µW 20.25 µW 24.18 µW
Ids versus Vds characteristics. The width of the
transistor is 10µm and length is 0.120µm. Area 144µm2 - -
Table 2: Performance Comparison with existing work

Fig.10 Ids Versus Vgs characteristics Fig.12 Power consumption comparison with existed
work
 V. CONCLUSION
In this design XOR gate is designed using 3 transistors
and CMOS full adder is designed based on two 3T XOR
and one 2T Mux. Using 8 transistors the full adder is
designed in this paper and voltage scaling also done by
reducing supply voltage. In this proposed full adder, the
power consumption 4.604µW is achieved and the total
area is 144µm2.

REFERENCES

[1] Senthil Kumaran Varadharajan and Viswanathan

Nallasamy, “Low Power VLSI Circuits Design Strategies
and Methodologies: A Literature Review”, 2017 IEEE,
978-1-5090-5555-5/17/$31.00 ©2017 IEEE.
[2] Dr.B.T.Geetha et al., “Design Methodologies and Circuit
Optimization Techniques for Low Power CMOS design”,
2017 IEEE, 978-1-5386-0814-2/17/$31.00 ©2017 IEEE.
[3] Mayur Agarwal, Neha Agarwal , Md. Anis Alam, “A New
Design of Low Power High Speed Hybrid CMOS Full
Adder”, 2014 International Conference on Signal
Processing and Integrated Networks (SPIN), March 2014,
Page(s): 448-452.
[4] Akshay Bhaskar et al., “A low power & high speed 10
transistor full adder using multi threshold technique”,
2016 IEEE, Doi:10.1109/ICIINFS.2016.8262968.
[5] C.H. Chang, J. Gu, M. Zhang, “A Review of 0.18μ Full
Adder Performances for Tree Structured Arithmetic
Circuits”, IEEE Transactions on Very Large Scale
Intergration Systems, Vol. 14, No. 12, December 2006.
[6] A. Parveen and T. T. Selvi, "Power Efficient Design of
Adiabatic Approach for Low Power VLSI Circuits," 2019
IEEE pp. 1-4.
doi: 10.1109/ICEES.2019.8719300.
[7] Somashekhar, Design of a Low Power D-Flip Flop using
AVL Technique, International Journal of Advanced
Research in Computer and Communication Engineering
Vol. 4, Issue 9, September 2015 DOI
10.17148/IJARCCE.2015.4962 291 .
[8] M Mittal and A P S Rathod, “Digital circuit optimization
using pass transistor logic architectures”, 2016 IEEE, pp-
1-5. Doi:10.1109/ETCT.2016.7882922.
[9] Malipatil, Somashekhar.(2017). Review and Analysis of
Glitch Reduction for Low Power VLSI Circuits.
International Journal for Research in Applied Science &
Engineering Technology (IJRASET) ISSN: 2321-9653.