****library: "samples"

version: 6.03ak
aids: 14
aidname: user
aidname: io
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
aidname: network
variables: 5
<[01,00]: 1
#[01,00]: 1
D[01,00]: 1
NET_compare_hierarchy[01,00]: 1
NET_use_port_names[01,00]: 1
aidname: drc
aidname: erc
aidname: simulation
variables: 1
SIM_fasthenry_defthickness[01,00]: 800
aidname: project
userbits: 6
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 400
variables: 1
TECH_last_state[01,00]: 8
techname: mocmosold lambda: 2000
techname: mocmossub lambda: 400
variables: 1
TECH_last_state[01,00]: 8
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 2000
variables: 1
TECH_last_state[01,00]: 0
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-2{p2}
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 29
maincell: 6
***cell: 0
name: tech-nMOSPullup{lay}
version: 1
creationdate: 0
revisiondate: 612141470
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aadirty: 6638
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name: out
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name: in
descript: 832
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celldone: tech-nMOSPullup
***cell: 1
name: tech-nMOS{lay}
version: 1
creationdate: 0
revisiondate: 976904012
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arc: 22
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arc: 32
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**node: 25
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type: nmos:Diffusion-Pin
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**node: 32
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***cell: 3
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arc: 43
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SCHEM_resistance[0104,0100001201]: "15K"
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*port: s
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SCHEM_resistance[0104,0100001201]: "14.0625K"
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SCHEM_flipflop_type[04,00]: "rsms"
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SCHEM_flipflop_type[04,00]: "rsms"
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exported: 0
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arc: 1
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**node: 5
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arc: 3
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*port: metal-1
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arc: 5
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userbits: 1032
*port: metal-1
arc: 6
**node: 15
type: mocmos:Metal-1-Pin
lowx: -37600 highx: -36400 lowy: 24000 highy: 25200
rotation: 0 transpose: 0
userbits: 1032
*port: metal-1
arc: 7
**porttype: 0
subnode: 0
subport: metal-1
name: b1
descript: 832
userbits: 92160
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subport: metal-1
name: b2
descript: 832
userbits: 92160
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subport: metal-1
name: b3
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subport: metal-1
name: b4
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subnode: 4
subport: metal-1
name: b5
descript: 832
userbits: 92160
**porttype: 5
subnode: 5
subport: metal-1
name: b6
descript: 832
userbits: 92160
**porttype: 6
subnode: 6
subport: metal-1
name: b7
descript: 832
userbits: 92160
**porttype: 7
subnode: 7
subport: metal-1
name: b8
descript: 832
userbits: 92160
**arc: 0
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width: 1200 length: 7600
userbits: 805315010
*end: 0
node: 0
nodeport: metal-1
xpos: -79000 ypos: 32200
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xpos: -79000 ypos: 24600
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width: 1200 length: 7600
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*end: 0
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nodeport: metal-1
xpos: -73000 ypos: 32200
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width: 1200 length: 7600
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*end: 0
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nodeport: metal-1
xpos: -67000 ypos: 32200
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nodeport: metal-1
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width: 1200 length: 7600
userbits: 805315010
*end: 0
node: 4
nodeport: metal-1
xpos: -55000 ypos: 32200
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nodeport: metal-1
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*end: 0
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nodeport: metal-1
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width: 1200 length: 7600
userbits: 805315010
*end: 0
node: 7
nodeport: metal-1
xpos: -37000 ypos: 32200
*end: 1
node: 15
nodeport: metal-1
xpos: -37000 ypos: 24600
celldone: tool-RoutingRiverBottom
***cell: 20
name: tool-RoutingRiverTop
version: 1
creationdate: 902349268
revisiondate: 902349348
lowx: -82400 highx: -53200 lowy: 26800 highy: 34400
aadirty: 4606
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arc: 0
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arc: 2
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arc: 3
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rotation: 0 transpose: 0
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*port: metal-1
arc: 7
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
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arc: 0
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arc: 1
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arc: 2
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type: mocmos:Metal-1-Pin
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userbits: 1032
*port: metal-1
arc: 3
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type: mocmos:Metal-1-Pin
lowx: -66400 highx: -65200 lowy: 33200 highy: 34400
rotation: 0 transpose: 0
userbits: 1032
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arc: 4
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
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arc: 5
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
userbits: 1032
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arc: 6
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
userbits: 1032
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arc: 7
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subport: metal-1
name: a1
descript: 832
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subport: metal-1
name: a2
descript: 832
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subport: metal-1
name: a3
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subport: metal-1
name: a4
descript: 832
userbits: 92160
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subport: metal-1
name: a5
descript: 832
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subport: metal-1
name: a8
descript: 832
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nodeport: metal-1
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type: mocmos:Metal-1
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userbits: 805309250
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node: 1
nodeport: metal-1
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nodeport: metal-1
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userbits: 805309250
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nodeport: metal-1
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nodeport: metal-1
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nodeport: metal-1
xpos: -65800 ypos: 33800
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width: 1200 length: 6400
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nodeport: metal-1
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nodeport: metal-1
xpos: -61800 ypos: 33800
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nodeport: metal-1
xpos: -57800 ypos: 27400
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nodeport: metal-1
xpos: -57800 ypos: 33800
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nodeport: metal-1
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celldone: tool-RoutingRiverTop
***cell: 21
name: tool-RoutingRiver
version: 1
creationdate: 902349456
revisiondate: 902349531
lowx: -86000 highx: -42800 lowy: 5200 highy: 32400
aadirty: 6638
userbits: 262144
nodes: 2 arcs: 8 porttypes: 0
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type: [19]
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descript: 969
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arc: 1
*port: b3
arc: 2
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*port: b5
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celldone: tool-RoutingRiver
***cell: 22
name: tool-SiliconCompiler{vhdl}
version: 1
creationdate: 676840842
revisiondate: 902688574
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 4606
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FACET_message[0257204,00]: ["-- VHDL design of Automobile Cruise Control","-- for
1988 CMC Workshop","--","-- Written by: D. Luke, A. Jost, & R. Hobson","-- Revised
to IEEE syntax by A. Jost","-- Latest revision date: Jan 3, 1989","--
*********************************************","","--BUS STRUCTURE
DEFINITION","","package buses is"," type BUS8 is array (0 to 7) of
BIT;","end buses;","","--**********************","","--TOP LEVEL ENTITY
ACC","","use buses.all;","","entity ACC is port(DR_SPEED, CONTROL : in BIT; FASTER,
SLOWER : out BIT;"," REF_SPEED: in BUS8) ;","end ACC;","","-- how
it is constructed:","","architecture ACC_BODY of ACC is",""," component
SENSOR_BOX port(pulses,reset : in BIT; refer: in BUS8;","
equal : out BIT);"," end component;",""," component TRANSMITTER_BOX1
port( eq, ck: in BIT;"," su, sd: out BIT);"," end
component;",""," signal EQUAL: BIT;","","begin","","SENSOR:
SENSOR_BOX port map( DR_SPEED, CONTROL, REF_SPEED, EQUAL);","TRANSMITTER:
TRANSMITTER_BOX1 port map( EQUAL, CONTROL, FASTER, SLOWER);","","end
ACC_BODY;","","--*******************************************************","","--
ENTITY SENSOR_BOX","","use buses.all;","","entity SENSOR_BOX is port(pulses, reset:
in BIT; refer: in BUS8;"," equal: out BIT) ;","end
SENSOR_BOX;","","architecture SENSOR_BODY of SENSOR_BOX is"," ","
component COUNTER_8 port(pulses,reset: in BIT; c: out BUS8);"," end
component;",""," component COMPARATOR_8 port(ina,inb: in BUS8;eql: out
BIT);"," end component;",""," signal C: BUS8;","","begin","","COUNTER:
COUNTER_8 port map(pulses,reset,C);","COMPARATOR: COMPARATOR_8 port
map(C,refer,equal);","","end SENSOR_BODY;","","--
***********************************************","","-- ENTITY
TRANSMITTER_BOX","","entity TRANSMITTER_BOX1 is port( eq, ck: in BIT; su, sd: out
BIT) ;","end TRANSMITTER_BOX1;","","architecture TRANSMITTER_BODY1 of
TRANSMITTER_BOX1 is",""," component rdff port(d,ck,cb,reset: in BIT; q,qb:
out BIT);"," end component;",""," component inverter port(a: in BIT; y:
out BIT);"," end component;",""," component nor2 port(a1,a2: in BIT; y:
out BIT);"," end component;",""," component nor3 port(a1,a2,a3: in BIT;
y: out BIT);"," end component;",""," signal ckbar,q1b,power,q2,q2b:
BIT;","","begin","","FF1: rdff port map(power,ck,ckbar,eq,open,q1b);","FF21:
nor2 port map(eq,q2b,q2);","FF22: nor2 port map(q2,ck,q2b);","NOR3X: nor3 port
map(q2b,ck,su,sd);","INV: inverter port map(ck,ckbar);","NORX: nor2 port
map(ck,q1b,su);","","end TRANSMITTER_BODY1;","","--
********************************************","","--ENTITY COUNTER_8","","use
buses.all;","","entity COUNTER_8 is port(pulses, reset: in BIT; c:out BUS8);","end
COUNTER_8;","","architecture COUNTER_BODY of COUNTER_8 is",""," component
rdff port(d, ck, cb, reset : in BIT; q, qb: out BIT);"," end component;","","
component inverter port(a: in BIT; y: out BIT);"," end component;","","
signal CBAR: BUS8;"," signal DSBAR: BIT;"," signal HOLD:
BIT;","","begin","","RIPPLEADD: for i in 1 to 7 generate"," RIPPLE: rdff port
map(CBAR(i), CBAR(i-1), C(i-1), HOLD, C(i), CBAR(i));"," end generate
RIPPLEADD;","","RIPPLEIN: rdff port map(CBAR(0), pulses, DSBAR, HOLD, C(0),
CBAR(0));","DS_INVERT: inverter port map(pulses, DSBAR);","R_INVERT: inverter
port map(RESET, HOLD);","","end COUNTER_BODY;","","--
*************************************************","","-- ENTITY
COMPARATOR_8","","use buses.all;","","entity COMPARATOR_8 is port(ina, inb:in BUS8;
eql: out BIT);","end COMPARATOR_8;","","architecture COMPARATOR_BODY of
COMPARATOR_8 is",""," component xor2 port(a1,a2: in BIT; y,yb: out BIT);","
end component;",""," component nor2 port(a1,a2: in BIT; y: out
BIT);"," end component;",""," component nand4 port(a1,a2,a3,a4: in BIT; y
: out BIT);"," end component;",""," signal comp: BUS8;"," signal
p,q: BIT;","","begin","","XORG: for i in 0 to 7 generate"," XORX: xor2
port map(ina(i),inb(i),open,comp(i));"," end generate XORG;","NANDX1: nand4
port map(comp(0),comp(1),comp(2),comp(3),p);","NANDX2: nand4 port
map(comp(4),comp(5),comp(6),comp(7),q);","NORX: nor2 port map(p,q,eql);","","end
COMPARATOR_BODY;","","--
***************************************************************",""]
celldone: tool-SiliconCompiler
***cell: 23
name: tool-SimulateALS{sch}
version: 1
creationdate: 676677107
revisiondate: 901155969
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aadirty: 6638
userbits: 262144
nodes: 24 arcs: 24 porttypes: 8
**node: 0
type: schematic:Or
lowx: -124000 highx: -84000 lowy: 32000 highy: 56000
rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 0
arc: 1
*port: y
arc: 23
**node: 1
type: schematic:Buffer
lowx: -120000 highx: -96000 lowy: 4000 highy: 28000
rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 2
*port: y
arc: 3
**node: 2
type: schematic:And
lowx: -32000 highx: 0 lowy: 12000 highy: 36000
rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 3
arc: 21
*port: y
arc: 4
**node: 3
type: schematic:Wire_Pin
lowx: -162000 highx: -158000 lowy: 50000 highy: 54000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 0
exported: 0
**node: 4
type: schematic:Wire_Pin
lowx: -162000 highx: -158000 lowy: 34000 highy: 38000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 1
exported: 1
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celldone: tool-SimulateALS
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celldone: tool-SimulateSPICE
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celldone: tool-SimulateVERILOG
***cell: 26
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