EEN 222 Computer Architecture

LAB No. 1
Introduction to Verilog (Gate Level)

Objectives
In this lab you will learn
1. Verilog coding and syntax
2. Creating and simulation a project in modelsim
3. Implementing and synthesizing a project in Xilinx

You will need the following software

1. Modelsim
2. Xilinx ISE 10.1

PROCEDURE
MODELSIM Quick Guide

For simulating Verilog designs and respective test benches in Modelsim you need to do the
following steps:

a) Creating a Modelsim Project and adding design files to it (Steps 1 to 7 below)

b) Compile the project (Steps 8 to 10)
c) Load the compiled design (Steps 11 to 12)
d) Add signals to be viewed in Timing Diagram (Steps 13 to 19 ,skip step 16)
e) Run the simulation (Step 16)

Step-by-Step Guide

1. Make a folder for your work anywhere in your computer

2. Create a Project: Select File -> New -> Project

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3. A dialog box will appear. Browse to the folder you created in step 1, give a project name and
Select OK.

4. Another dialog box will appear. If you want to use an already existing file then select “Add
Existing File” otherwise select “Create New File”

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5. On selecting Create new file, another dialog will appear. If file type is not Verilog, select
Verilog from drop down menu. Give a name to the Verilog file you want to create and press
ok. If you want to create multiple files you can either repeat step 4 & 5 at this stage or add
new file to project later on as mentioned in step 6.

6. After step 5 you should be able to see your created file name in the Workspace window as
shown below. If you want to add another file later on you can always right click in the
Workspace window and select Add to Project -> New File

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7. Double clicking the file in work space window will open it for editing. Write your Verilog
code.

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8. After writing the code, Compile the files. Right click in the Workspace window and select
Compile -> Compile All

9. You can see the compilation results in the Transcript window as shown below. You will get
messages in green like following if compile is successful.

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10. In case of errors you will get error messages in red in the Transcript window as shown below.
You can double click the messages to open the details of the errors. This will open a dialog
box showing details of errors as shown below.

Note that in the above example, the error message tells us the line number i.e. 55 and further
elaborates that it was expecting a semicolon and encountered an “endmodule” instead. In the
figure, you can see that a semicolon is missing on line number 53 in fifo.v. Remove all such
errors and compile again (as mentioned in step 8) until compilation of all files is successful.

11. After successful compilation, the next step is to run the simulation. In the bottom of
Workspace window, select Library. Here select work (i.e. press the “+” mark on left side of
work), you will see the names of your project files.

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12. Right click on the test bench file and select Simulate as shown below. This will load your test
bench and the files included in the test bench i.e. your complete design. The simulation is
ready to be run. You can notice that after this step a few more tabs are added in the
Workspace window and the active tab is sim.

13. We are generally interested in viewing the results in form of timing diagram. For that we can
start the wave form viewer by typing view wave in the Transcript window. This will open the
wave form viewer.

14. You can see the hierarchy of your design in the Workspace window (You can see tb_fifo,
FIFO and counter in the following figure). To select all signals of an instance of a module to
be viewed in waveform viewer, you can right click it and select Add -> To Wave -> All
items in region as shown

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15. When you click an instance its variables are displayed in the Objects window. If you prefer
viewing some specific signals instead of all signals, you can select Add -> To Wave ->
Selected items on selected signals from Objects window.

16. Once done with adding required signal, we can run the simulation. To run the simulation, in
the Transcript window write run –all

This will run the simulation unless $stop is reached in the Verilog code. You can also manually
stop the simulation by pressing the break key from the tool bar.

17. You can visually see the timing diagrams in wave form viewer

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You can use right click on the wave form window to zoom in or zoom out in different regions.
Or, you can use menu buttons to zoom in and zoom out, or use zoom mode to
zoom select the zoom region on the screen using mouse.

18. To save the set of signals that you have added in the wave form for future simulations, you
can select File -> Save Format and give a name to the file. In subsequent simulations you
can load this file before running the simulation instead of adding these signals again.

19. To use a saved wave file before running the simulation, instead of doing step 14 & 15 you
can write do wave. do(If you saved the file with this name, otherwise use the name you used
while saving) in the transcript window.

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By this time, you should be able to compile and simulate your design to view the results. In next
section we shall see how we can automate these steps to save our time in the debug process,
where we need to simulate the design multiple times.

Using scripts

It is often desirable to do a small change in Verilog code and run the simulation again. To avoid
doing the above-mentioned steps again we can automate a few things using scripts. For most of
the steps mentioned above, we can use the transcript window commands instead of GUI (When
we do something from GUI, it initiates a related command that you can see in the Transcript
window).

For compiling all files we can use

>project compileall

For loading the project we can use

>vsimwork.tb_fifo

To save a wave file we can use

> write format wave wave.do

To quit a simulation we can use

> quit –sim

To run a set of commands in sequence, we can write all the commands in a file and use that file
to run all the commands. For example, the steps the to run a simulation as discussed above can
be executed from Transcript window by following commands

project compileall
vsimwork.tb_fifo
view wave
do wave.do
run -all

We can create a file say run.do with the above-mentioned commands on each line. Then, instead
of running all the commands we can use the do command in transcript window to run all the
commands in that file as below.

> do run.do

Similarly if we can write another script file that saves the wave file, quits the current simulation
and then compiles and re-runs the simulation, then we can write the following lines on top of
above mentioned lines
write format wave wave.do
quit -sim

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And then we can save it with a different name say rerun.do, this way we can use run.do for
running the simulation for the first time and use rerun.do to rerun the simulation keeping all the
waveform signals intact.

For new projects, you can copy the same do files just changing the name of the test bench file.
Known Issues

Some students missed step no.5 above to select the file type as Verilog instead of VHDL.

Another problem encountered by most students is that when they do “Compile All” nothing
happens and the file is not added to Work folder. To solve this problem we can do the following.

For each Verilog file in your project, Edit properties of the file

Right click file name in the project tab and select properties

This will open the following window. We have to make two changes here.

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First, Click on “Change Type” button will open a change type dialog. Select Verilog and press
OK as shown.

Now, In “Compile to library” drop down in General Settings, select “work” and press OK.

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After these changes, try “Compile All” (i.e. Step no. 8 above) again.

After we have verified our modules in modelsim now its time to synthesize in Xilinx

XILINX PROJECT NAVIGATOR STEP BY STEP GUIDE

1.Clik on File .Select New Project

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2.A New Project wizard will appear which will ask you to name the project and the location to
want to save it.

3.Click Next and you will see a window like that.

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4.In the Device Properties window Enter the following parameters

Family Spartan3E
Device XC3S1200E
Package FG320
Speed -4
Synthesis Tool XST (Verilog/VHDL)
Simulator MODELSIM or ISE Simulator
Preferred language verilog

5.Once you have entered the parameters.Click Next

6.The new window will ask you to add a new source file.Click New Source.You will see a
window like that

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7.Select Verilog Module and Enter the file name.Then Click Next.You will see a new window
that will ask you to enter the inputs and outputs

8.Enter the Port name and direction i.ewether a port is input or output.If is a vector then check
the bus box and specify the MSB and LSB.

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9.Click Next and you will see a following a window.Then Click Finish

10.You will see a screen like that

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11.In the project window write your Verilog code.

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12.Once you have written your code,save it and then right Click on Synthesize XST and select
Run

13.Once the Synthsise process has run successfully you will see the it has turned a greenish
arrow.This indicates that there are no errors in the design.Click on the + box and then click on
the view RTL Schematic.

13.You will see the design generated in the window as shown

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14.RunImplement Design

15.Once the implementation is done then run Generate programming File

Lab No.1 Introduction to Verilog

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16.You will see a window like that

Now once the Programming File is generated it is the then ready to be loaded on the fpga.

Lab Tasks
1. Write Verilog Description of a Full Adder at Gate Level
2. Write Verilog Description of a 3x8 decoder at Gate Level
3. Verify the task 1 and Task 2 using Test Fixture

Checked By: Date:

Lab No.1 Introduction to Verilog