VLSI Design Lab Manual

Lab # 6 : Introduction to modelsim:

Objectives:
 Getting used to Modelsim software
 Creating a Verilog file in Modelsim
 Compiling and simulating a Verilog module
 Analyzing the timing diagram of a Verilog Module

Software Used:
 Modelsim

In Lab
Open modelsim in your PC and goto file->new->project as shown in fig:1

Fig1: create new project

Type your project name and clik Ok

A new window will pop up as shown in fig:2

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Fig:2 create new file

Click create new file and a new window will open up as shown in figure:3

Fig:3 new file name and file type

Fill in the file name and choose file type as verilog

Now press Ok

After this the file you created will appear in the workspace window as shown in figure:4

Here file name was example1

Try to keep the module name and file name same to avoid any error

Fig:04 new file created in files panel on workspace window

Now left click on the created file and select edit

A new window will appear as shown in figure:5 here you have to type your verilog code

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For example I type here a code for inverter as shown in figure:6

Now press save and goto the work space window and select created file and than left and goto

compile-> compile selected

if there is no error a check mark indication will be placed in front of the file as shown in figure:7

Now our design is ready and now we have to test it for this we have to create a test bench

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CREATING A TEST BENCH

Left click anywhere in workspace window and goto add to project->new file

Add name of the file and select type as verilog and press ok

A new file will be created in the work space as shown in figure:8

Now edit this file and create a test bench for the module eample1 in this case

The verilog code for the test bench is shown below in figure:9

Now save this code and goto workspace window and select tb_example1.v file and left click on it and
compile it

Now select the tb_example1 file and goto simulate and goto work->tb_example and press ok as shown in
figure:10

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Now in work space window a new simulation panel will appear as shown in figure:11

Fig 10: simulation window

Fig 11: Sim panel

Now in sim panel right click on tb_example1 goto add to wave and a new window will appear here click
run to view simulation as shown in figure 12

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Fig 12: waveform window

In this task , you will run your first programme in Verilog which is a high-level language for ASIC design
and FPGA programming. Essentially it converts all logic into gates.

Install ModelSim from \\support\Softwares\Engg Softwares\Model Sim 5.7G.

Create a file main .v (in a folder ‘hello') using notepad containing following code:

module main;
integer i;
initial
begin

$display("Hello, World");
$display("The system is up !");

for (i=0;i<5;i=i+1)
begin
$display(i);
end

end
endmodule

Goto File >> Change Directory and point to your ‘hello’ folder
Goto Work >> main. Double click to load simulation

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Type run to execute code. Type quit –sim to end simulation

Task 1:
Write Verilog code for following design

Task 2
Generate Fibonacci series using a verilog program

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