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    Nalamala Venkatesh is seeking a position as an RTL design and verification trainee where they can apply their knowledge and contribute to an organization. They have completed an advanced VLSI design and verification course from January 2020 to present. Their technical skills include Verilog, SystemVerilog, UVM methodology, protocols like AXI and SPI, and tools like Questasim and Vivado. Their projects include designing and verifying a 1x3 router using Verilog and UVM and working on a doubly fed induction generator with active filter capabilities.

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    Nalamala Venkatesh is seeking a position as an RTL design and verification trainee where they can apply their knowledge and contribute to an organization. They have completed an advanced VLSI design and verification course from January 2020 to present. Their technical skills include Verilog, SystemVerilog, UVM methodology, protocols like AXI and SPI, and tools like Questasim and Vivado. Their projects include designing and verifying a 1x3 router using Verilog and UVM and working on a doubly fed induction generator with active filter capabilities.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    28 views2 pages

    Nalamala Venkatesh PDF

    Uploaded by

    Pranav Dixit
    Nalamala Venkatesh is seeking a position as an RTL design and verification trainee where they can apply their knowledge and contribute to an organization. They have completed an advanced VLSI design and verification course from January 2020 to present. Their technical skills include Verilog, SystemVerilog, UVM methodology, protocols like AXI and SPI, and tools like Questasim and Vivado. Their projects include designing and verifying a 1x3 router using Verilog and UVM and working on a doubly fed induction generator with active filter capabilities.

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    of 2

    NALAMALA VENKATESH

    RTL DESIGN AND


    VERIFICATION TRAINEE

    Mobile :- +918897673667.
    Email :- nalamalav@gmail.com
    Linked In:-https://www.linkedin.com
    /in/nalamala-venkatesh-36b994155.

    OBJECTIVE
    To obtain a position where I can apply my knowledge and skills in real time environment
    and work hard there by continuously growing and contributing to the main objective of the
    organization.

    EDUCATION
    Advanced VLSI Design and Verification course
    Maven Silicon VLSI Design and Training Center, Bangalore January 2020 till date.

    COURSE BOARD INSTITUTION PERCENTAGE YEAR

    B.E(EEE) Jntu Kakinada Narasaraopeta institute 2017


    of technology 68
    Narasaraopeta,
    Guntur(dt).

    Diploma SBTET Govt polytechnic , 67 2014


    Kandukur

    SSC STATE Zph School, 75 2011


    BOARD Brahmanapalli

    Technical Skills
    HDL: Verilog
    HVL: SystemVerilog
    Verification Methodologies: Constraint Random Coverage Driven Verification
    Assertion Based Verification - SVA
    TB Methodology: UVM
    Protocols: AXI, AHB, UART, I2C, SPI
    EDA Tool: Mentor Graphics - Questasim and Xlinix - ISE, Xilinx - Vivado
    Domain: ASIC/FPGA front-end Design and Verification
    Operating System Linux
    Scripting Languages: Perl Scripting
    Core Skills: RTL Coding using Synthesizable constructs of Verilog, FSM based
    design, Simulation, CMOS Fundamentals, Code Coverage, Functional
    Coverage, Synthesis,
    Static Timing Analysis, Assertion Based Verification using
    SystemVerilog Assertions.
    EXPERIENCES
     I am worked at Udaan Express as a process executive from April 2019 to December
    2019
     I am works at GSH Facilities and Management services as a Electrical Assistant from
    September 2018 to April 2019

    PROJECTS

    1. Router 1x3 – RTL design and Verification

    HDL: Verilog
    HVL: SystemVerilog TB Methodology: UVM
    EDA Tools: Questasim and ISE

    Description: The router accepts data packets on a single 8-bit port and routes them to one of the
    three output channels, channel0, channel1 and channel2.

    Responsibilities:
     Architected the block level structure for the design.
     Implemented RTL using Verilog HDL.
     Architected the class based verification environment using SystemVerilog.
     Verified the RTL model using SystemVerilog.
     Generated functional and code coverage for the RTL verification sign-off
    Synthesized the design.

    2. Doubly fed induction generator with an integrated active filter capabilities

    Description: A Doubly Fed Induction generator as its name suggests is a 3 phase induction
    generator where both the rotor and stator windings are fed with 3 phase AC signal ...... It also
    consists of a multiphase slip ring assembly to transfer power to the rotor. It is typically used
    to generate electricity in wind turbine generators.

    HOBBIES
     Listening music
     Swimming

    DECLARATION:
    I hereby declare that the above said information are true to the best of my knowledge and
    belief.
    Date:-
    Place:- (Nalamala venkatesh)

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