IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Design of Delay Efficient Modified 16 bit Wallace

Multiplier
G.Challa Ram, D.Sudha Rani, R.Balasaikesava, K.Bala Sindhuri

Abstract—The structure of modified tree multipliers with Further results are compared in terms of speed, area and
different adders is presented. Multiplication is an important power. In this Paper proposed 16bit Wallace Multiplier
fundamental arithmetic operation in all microprocessor circuits using different adders i.e., carry select adder (CSLA) and
and algorithms. Currently the speed of multipliers is limited by Binary to Excess Code Converter-1 (BEC) are designed
the speed of adders used for partial products addition. In this
using Verilog HDL.
paper Conventional Array Multiplier and Dadda Multiplier are
compared with the Wallace multiplier in terms of delay. Further
a proposed sixteen bit Wallace multiplier is implemented by II. ARRAY MULTIPLIER
using Carry Select Adder (CSLA) and Binary to Excess -1
Converter (BEC) adder. The delay for Wallace multiplier using Array multiplier is similar to normal multiplier. Array
CSLA is less when compared to Wallace multiplier with BEC. multiplier algorithm consists of same steps as done in normal
These multipliers are coded in Verilog HDL, simulated and multiplication of numbers. The design of Array multiplier is
synthesized by using XILINX software 12.2 on Spartan 3E FPGA easy to implement. In this multiplication the number of
device xc3s500-5fg320. partial products is obtained in large number. As a multiplier
Keywords— Array Multiplier, Wallace Multiplier, Dadda
working performance is based on the number of partial
Multiplier, Proposed Multiplier, Ripple Carry Adder (RCA), products obtained [2]. Array multiplier is poor when
Carry Select Adder (CSLA), Binary to Excess Code Converter-1 compared to tree multipliers in terms of delay and memory.
(BEC-1),Half Adder (HA),Full Adder(FA).
In this algorithm each multiplier bit is multiplied with each
I.INTRODUCTION bit of multiplicand to get a partial product. There will be a
shift in partial product after completion of multiplication of
Multiplication is one of the basic arithmetic operations. At each bit of multiplicand. The partial products are added to
present, multiplication of bits is a common process in any of obtain the final result [8].
the algorithms used for processing of systems. The
functionality of any algorithm is greatly dependent on
functional parameters of multipliers [1, 2]. The parameters
include delay, memory and power. For efficient working of
any algorithm which includes multiplication the selection of
multiplier plays a key role [3]. The selection of multiplier is
concerned by observing the delay and area of the multiplier.
The delay and memory of any multiplier can be varied by
using different adders. By using adders like CSLA and BEC
in place of normal full adders a reduction in delay and area
can be achieved. Different tree multipliers are fastest among
the available multiplier [6]. These tree multipliers can be
further modified to obtain efficient delay and memory.
In this paper the multiplication algorithm of Array, Dadda
and Wallace multipliers and their architectures are
explained [9]. Fig.1: Four bit Array Multiplier

III. WALLACE MULTIPLIER

G.Challa Ram, B.E Student, Department of ECE, SRKR Engineering

College,Bhimavaram, India.(gchallaram@yahoo.com)
D.Sudha Rani, B.E Student,Department of ECE,SRKR Engineering College,
Bhimavaram, India. (sudha9540@gmail.com)
R.Balasaikesava, M.E student,Department of ECE,SRKR Engineering
College, Bhimavaram, India. (balasaikesava@gmail.com)
K.Bala Sindhuri, Assistant Professor, Department of ECE, SRKR Engineering
College, Bhimavaram, India. (k.b.sindhuri@gmail.com)
Wallace multiplier is one among the efficient tree
multipliers which are frequently used in microprocessor
circuits [1]. Wallace multipliers operate on a different
algorithm unlike conventional Array multiplier. Wallace
Multiplier is commonly used where an efficient delay is
major requirement [4, 6].
Wallace Multiplier algorithm for 4 bit is mentioned below.
 For a 4 bit multiplication firstly, the partial
products are obtained.
 Group the first three rows of partial products and

978-1-5090-0774-5/16/$31.00 © 2016 IEEE

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India
add them together by using adders. The carry
generated by the adders in each column is rippled
to preceding column as shown in fig.3
 The outputs of these adders in the first stage are
added with the remaining rows of partial products.
Fig.2: Four bit Wallace Multiplier
The dot representation of Wallace multiplier is shown in
fig.3 where ‘.’ indicates partial products and ‘o’ indicates
carry generated by the addition of partial products. Further
this multiplier is implemented by using different adder in
order to minimize the memory and delay.
Fig.3: Dot representation of 4 bit Wallace Multiplier
IV. DADDA MULTIPLIER
Dadda multiplier algorithm is similar to Wallace algorithm
with few modifications. This algorithm depends upon the
weights of the partial products [2]. Firstly, the partial
products are obtained as in normal multiplication. These
partial products are arranged in rows and columns such that
all the partial products in each column are equal [5]. After
the arrangement of partial products the column having
maximum height i.e., consisting more number of partial
products is chosen for reduction. When there are ‘i’ partial
products in the column these are reduced by using the
following formula.
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For example, if there are four elements in maximum height
of the column. These elements should be reduced to three so
that the maximum height of the columns will be three. This
reduction process is continued for three elements. The
reduction of these partial products is done by using full
adders and the carry should be considered as an element in
the net column. This reduction should be continued till the
maximum height of the column reaches to two. The final
result is obtained by adding these last two rows.
V. PROPOSED WALLACE MULTIPLIER
Normal Wallace Multiplier occupies more memory when
compared with Array and Dadda Multipliers but consumes
less delay. The delay consumption is based on the type of
adders used in the multipliers. In order to achieve very low
delays the conventional half and full adders can be replaced
with new techniques. In this paper Carry Select Adder
(CSLA) and Binary to Excess Code Converter (BEC) are
used in the implementation of Wallace multiplier. These
adders are explained in detail below.
A. Carry Select Adder (CSLA)
Carry Select Adder is similar to Ripple Carry Adder. In
CSLA the total numbers of bits are partitioned into equal
sizes and the carry in for second group is taken as both zero
and one [7]. The outputs are generated for both the cases
i.e. for carry o and 1 at once so that the delay can be greatly
reduced. The desired outputs are selected by using a
multiplexer having carry as a selection line. Multipliers
using CSLA adder can have better delays but it consumes
more area as no of gates are increased.
Fig.4: Four bit Dadda Multiplier algorithm
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

The partial products obtained at the last stage are added

by BEC or CSLA to get the result. Here CSLA is
preferred when there is a need for less delay multipliers
and BEC is chosen as a multi tradeoff between memory
and delay.

In fig.7 the dots indicate the partial products of the Wallace

Multiplier which are added by using CSLA or BEC to
obtain the result. It is implemented up to 16 bit
multiplication.

Fig.5: Eight bit CSLA structure

B. Binary to Excess Code Converter: Fig.7: Implementation of Wallace using CSLA and BEC

Binary to Excess code converter is used in CSLA when VII.RESULTS

the carry input is one. BEC increments the input bits by The simulation windows for 16- bit Array, Dadda,
one so it is chosen in the case where carry input is Wallace and Proposed Wallace Multiplier are shown.
given as 1in CSLA [8]. By using BEC structure in place
of full adders memory can be minimized as BEC structure
consist of NOT,AND,XOR gates.

BEC adders are implemented easily along with CSLA by

replacing the structure with BEC gates [2]. In order to
obtain efficient memory and delays multipliers are
implemented with these BEC adders.

Fig.8: Simulation results for 16x16 Array multiplier

Fig.6: Eight bit BEC structure

C. Implementation of Wallace Multiplier using CSLA

and BEC

In Wallace Multiplier generally the partial products at

the last stage are added by using half and full adder to
obtain the result. The use of large number of half and full Fig.9: Simulation results for 16x16 Wallace multiplier
adders leads to a great increase in the memory which
makes the multiplier inefficient. In order to attain a good
level of memory utilization these adders are replaced
by modern algorithm such as BEC and CSLA.

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

From table2, the delay consumed for the Wallace

multiplier with CSLA is less when compared to normal
Wallace multiplier and Wallace Multiplier with BEC.
Proposed Wallace multiplier with CSLA is preferred when less
delay is required.

TABLE II: COMPARISON BETWEEN 16X16 WALLACE

MULTIPLIER USING BEC- 1 AND CSLA

Fig.10: Simulation results for 16x16 Dadda Multiplier

Wallace Wallace Wallace
Utilization Summary: Utilization 16x16 16x16 16x16
using using Multiplier
The below table1 shows the comparison of 16 bit BEC-1 CSLA
Array, Dadda and Wallace Multipliers and table2 Delay in ns 24.948 25.596 36.350
shows the comparison of Wallace multiplier with Power in mw 86.48 86.52 86.25
CSLA and BEC adders.
Memory in KB 205452 205644 204172

No. of 493 493 493

Slice
registers
Bonded IOBs 66 66 66
Flip flops 492 492 492
Frequency 75.609 86.081 80.205
in MHZ
No.of 4 1019 1021 1000
input
Fig.11: Simulation results for 16x16 Wallace multiplier using CSLA
LUTs
VIII.CONCLUSION
REFERENCES
From the above results it is clear that for 16bit, delay for
Wallace multiplier (36.350 ns) is less when compared to
Array (61.39 ns) and Dadda (55.651ns) multipliers. Wallace [1] Himanshu Bansal, K. G. Sharma, Tripti Sharma,” Wallace Tree
Multitier is high speed multiplier when compared with Array Multiplier Designs: A Performance Comparison Review“, Innovative
Systems Design and Engineering, Vol.5, No.5, 2014.
and Dadda Multipliers.
[2] Addanki Purna Ramesh,” Implementation of Dadda and Array
TABLE I:COMPARISON BETWEEN 16X16 ARRAY MULTIPLIER, Multiplier Architectures Using Tanner Tool “, International Journal of
DADDA MULTIPLIER AND WALLACE MULTIPLIER. Computer Science & Engineering Technology (IJCSET), volume: 2,

Array Dadda Wallace [3] E. Prakash, R. Raju, Dr.R. Varatharajan, “Effective Method For
Utilization 16x16 16x16 16x16 Implementation of Wallace Tree using Fast Adders”, Journal of
Multiplier Multiplier Multiplier Innovative Research and Solutions (JIRAS) ,Volume.1,Issue No.1,July –
Dec 2013.
Delay in ns 61.39 55.651 36.350
Power in 86.22 86.18 86.25 [4] Chepuri satish, Panem charan Arur, G.Kishore Kumar , G.Mamatha,
mw ”An Efficient High Speed Wallace Tree Multiplier”, International
Memory in 200524 200524 204172 Journal of Emerging Trends in Electrical and Electronics (IJETEE)
,Vol. 10, Issue.4,May2014.
KB
No.of Slice 493 493 493 [5] Witney J.Townsend, Earl E.Swartzlander, Jr., and Jacob A.Abraham,
registers “A Comparision of dadda and Wallace multiplier delays” Computer
Bonded 66 66 66 Engineering Research centre, the University of Texas at Austin.
IOBs [6] Shahzad Asif and Yinan Kong,” Low-Area Wallace Multiplier”,
No.of 4 844 889 1000 Department of Engineering, Macquarie University, Sydney, NSW 2109,
input LUTs Australia, Received 18 March 2014; Accepted 23 April 2014; Published
12 May 2014.
Flip Flops 492 492 492
Frequency in 79.108 70.033 80.205 [7] B. Ramkumar and Harish M Kittur, “Low–Power and Area-Efficient
MHZ Carry Select Adder”, IEEE transactions on very large scale integration
(VLSI) systems, VOL.20, NO.2, february 2012.

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[8]G.Challa ram, D.Sudha Rani, Y. Rama lakshmanna, k. Bala

sindhuri,”Area efficient modified vedic multiplier”, International
conference on circuit ,power and computing
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[9] E. Prakash, R. Raju, Dr.R. Varatharajan, “Effective Method For

Implementation of Wallace Tree using Fast Adders”, Journal of
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