6T-SRAM cell layout

Large unfilled shapes are the

Diffusions.
Lighter and darker shaded
Poly crosses diffusion a shapes makes cross-coupled
transistor is formed latch

B and B bar

There are number of ways SRAM cell can be laid out

Alternative layout incorporates two ground contacts and two VDD contacts. The area of the
Cell is the primary factor in the overall area of an embedded memory

Vdd and gnd contacts can be shared with adjacent cells. Saves significant area.
• There are no contacts in between the cross-coupled
FETs , the spacing b/w these goes small.

• Often, bit line contacts are shared by a pair of cells

vertically adjacent to another column

• If a single bit line contact becomes resistive, two cells

will fail
– Reading a cell involves the cell pulling down either B or B bar
line low.
– Resistive bitline contact causes one of the two data types to
fail on these two cells
– Vertically paired cells with defective bit line contact may
store either “0” or “1” but not both
• Resistive bit line contact degrades the writing of
the cells more than the read operation.

• SRAM cells fig. 1 and 2 are laid out differently .

They fail differently as well.

• One cell layout style is sensitive to different

manufacturing defects and fails differently from
other cell layout styles

• Different fault models and testing patterns

should be used for these different designs.
• Separate resistive ground contact can easily
disturb since there is an imbalance between B and
B bar

• Open VDD contact is shared by adjacent cells. –

group of four cells fail
• Two Layout looks identical and Failure modes are
different
A 500MHZ 288kb CMOS SRAM Macro for On-Chip Cache ,
K. Furumochi ; H. Shimizu ; M. Fujita ; T. Akita ; T. Izawa ; M. Katsube ; K. Aoyama ; S. Kawamura
• For any layout cell stability is defined by the
ratio of the strength of pull-down divided
strength of the transfer device. This is “beta
ratio”.

• Beta ratio of 1.5 to 2 is typical in industry

– Below 1.0 indicates cell read disturbance error. For
SRAM, a defect free must have non-destructive
read operation
• Determining the beta ratio, which, defines cell
stability

Beta ratio calculation for an “n” read port memory

• In the case of a multiport memory cell it is the
relative strength of the pull-down device to all of
the transfer devices combined.

• The beta ratio, which is so critical to single-port

cell stability, is now the strength of the pull-down
device divided by the strength of both transfer
devices for a two-port memory
 Butterfly curve for an SRAM cell.
A.J. Bhavnagarwala, X. Tang, J.D. Meindl, “The impact of intrinsic device fluctuations on
CMOS SRAM cell stability,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, 4/2001,
pp. 658-65.

The SNM of a CMOS SRAM cell

is defined as the minimum dc
noise voltage necessary to flip
the state of a cell

A larger box, which is contained

inside the butterfly “wing”
indicates a more stable the cell
• The butterfly curve illustrates the stability of the 4
latch transistors inside the cell

• To generate a butterfly curve, one node is forced to a

potential and the complement node value is
determined

• The curve flattens during a read operation, reducing

the box size and so illustrating a reduced stability.

• A smaller box size during a read also correlates to a

smaller beta ratio.