School of Engineering and Applied Science, Ahmedabad University

M.Tech./B.Tech: __________________________

Name: ____________________________________________ Roll no.: ____________________________

Student’s Signature: ________________________ Supervisor’s Signature: _______________________

M. Tech. (CSE): Semester I // B. Tech. (ICT): Semester VII

Subject: High Performance Computing (EVD511); Mid-Term Exam (Maximum Marks: 100)
16/09/2018, Exam Duration: 1 Hour and 30 minutes

Instructions: (1) Attempt All Questions. (2) Answer all the question with reference to HPC Course taught
in the class. (3) Figures to the right indicate full marks. (4) Assume any necessary data and mention them.

Q.1 Consider following set of instructions written in simplified assembly language. Assume that all the
instructions mentioned below can be symmetrically executed in three clock cycles. First clock cycle
will be used for fetching the instruction, second clock cycle will be used for decoding the instruction
and third clock cycle will be used for executing the instruction. If three stage instructions level
pipelining is applied to execute this code, identify which “conflicts” will be present when you execute
following program. Answer questions with reference to this program. [18]

Program:

Line 1: R0 = 2
Line 2: R1 = 3
Line 3: R1 = R1 + R0
Line 4: R5 = R1 + 5
Line 5: Jump to Line 3 if R1 < 6
Line 6: R6 = R5
Line 7: R8 = R4 + R7

Now, answer following Questions:

Identify Conflict 1 and mention in which lines of the code it will be encountered:

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Identify Conflict 2 and mention in which lines of the code it will be encountered:

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Rewriting above program to remove conflicts, assuming three stage pipeline execution scenario. Note
that the rewriting the program should have identical outcome at the end of the execution compared to

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original program. Use NOP (No Operation) instruction as Stall if and when required. Write shortest
possible program without any conflict.

Briefly Mention Any one technique you used to resolve Conflicts:

(1) ______________________________________________________________________________

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Q.2 Draw and explain the diagram to represent “Memory Hierarchy for Servers” and describe the
essentials of Memory Hierarchy. Explain need of memory hierarchy, its advantages and its
disadvantages/limitations. [10]

Diagram:

Description:
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Q.3 Briefly answer following questions. [16]

(a) Very briefly explain three steps involved in Tomasulo’s Algorithm.

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(b) Briefly describe VLIW Processors with reference to Instruction Level Parallelism.

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(c) Compare Software and Firmware

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(d) Briefly explain compiler optimization to reduce miss rate, with example of “Loop Interchange”.

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Q.4 Write a short note on Flynn’s Taxonomy. Draw appropriate diagrams and mention one example with
brief description. [16]

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Q.5 Consider following set of instructions written by an amateur programmer in simplified assembly
language. Assume that all the instructions mentioned below can be symmetrically executed in three
clock cycles. First clock cycle will be used for fetching the instruction, second clock cycle will be used
for decoding the instruction and third clock cycle will be used for executing the instruction. If three
stage instructions level pipelining is applied to execute this code, identify which “conflicts” will be
present when you execute following program. Answer questions with reference to this program. [16]

Program:

Line 1: R2 = R1 + R0
Line 2: R5 = R2 + R3
Line 3: R3 = R1 + R4
Line 4: R9 = 5
Line 5: Jump to Line 8
Line 6: R6 = R1 + R3
Line 7: R8 = R4 + R7
Line 8: R10 = 2
Line 9: R11 = R9 + R10

Now, answer following Questions:

Identify Conflict 1 and mention in which lines of the code it will be encountered:

_____________________________________________________________________________________

_____________________________________________________________________________________

Identify Conflict 2 and mention in which lines of the code it will be encountered:

_____________________________________________________________________________________

_____________________________________________________________________________________

Rewriting above program to remove conflicts, assuming three stage pipeline execution scenario. Note
that all mathematical operations mentioned in the program should be executed. You can not exclude
any instruction. You may rearrange instructions. Use NOP (No Operation) instruction as Stall if and
when required. Write shortest possible program without any conflict.

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Briefly Mention Any one technique you used to resolve Conflicts:

(1) ______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

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Q.6 Describe the principle of operation of FeRAM. Draw two diagrams with proper labels – first in ON
state of device and second in OFF state of device, to explain details. Explain how this structure stores
the binary information. [12]

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Q.7 Assume we have a computer where the cycles per instruction (CPI) is 1.0 when all memory accesses
hit in the cache. The only data accesses are loads and stores, and these total 60% of the instructions.
If the miss penalty is 20 clock cycles and the miss rate is 5%, calculate how much faster the computer
would be if all instructions were cache hit. [8]

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Suppose that we want to enhance the processor used for a specific application. The new processor is
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20 times faster on computation in that specific application than the original processor. Assuming that
the original processor is busy with computation 50% of time and is waiting for I/O for the remaining
time, what is the overall speedup gained by incorporating the enhancement? You may use concepts of
Amdahl’s Law for this calculation. [4]

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