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Digital Design: Register-Transfer Level (RTL) Design
Digital Design: Register-Transfer Level (RTL) Design
Chapter 5:
Register-Transfer Level
(RTL) Design
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com
5.1
Introduction outputs
inputs
FSM
FSM
bi bo
• Chapter 3: Controllers Combinational
– Control input/output: single bit (or just a logic n1
few) representing event or state n0
s1 s0
– Finite-state machine describes
State register
behavior; implemented as state register clk
and combinational logic
• Chapter 4: Datapath components
– Data input/output: Multiple bits Register Comparator
collectively representing single entity i
s
sa
i
n
bi bo
• This chapter: custom processors
z
1
RTL Design: Capture Behavior, Convert to Circuit
• Recall
– Chapter 2: Combinational Logic Design
• First step: Capture behavior (using equation
or truth table)
• Remaining steps: Convert to circuit
Capture behavior
– Chapter 3: Sequential Logic Design
• First step: Capture behavior (using FSM)
• Remaining steps: Convert to circuit
• RTL Design (the method for creating
Convert to circuit
custom processors)
– First step: Capture behavior (using high-
level state machine, to be introduced)
– Remaining steps: Convert to circuit
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5.2
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2
RTL Design Method: “Preview” Example
• Soda dispenser s a
– c: bit input, 1 when coin
deposited
– a: 8-bit input having value of c Soda
deposited coin d dispenser
– s: 8-bit input having cost of a processor
soda
– d: bit output, processor sets to s a 25
1 when total value of
deposited coins equals or 50 25
0 1 0 1 0
exceeds cost of a soda c Soda tot:
tot:
d dispenser a
0 1 0 processor50
25
3
Preview Example:
Step 2 -- Create Datapath
Inputs : c (bit), a(8 bits), s (8 bits)
Outputs : d (bit)
Local reg isters: t ot (8 bits)
Datapath 8
Digital Design
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s a
which we named
tot_lt_s 8 8
• Controller’s outputs
– External output d c
(dispense soda)
– Outputs to datapath d tot_ld
to load and clear the
tot register tot_clr
Controller Datapath
Digital Design
tot_lt_s
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4
Preview Example: Step 4 – Derive the Controller’s
FSM s a
• Same states 8 8
and arcs as
c
high-level
d
state machine tot_ld
Controller
Datapath
tot_clr
• But set/read
tot_lt_s
datapath s a
control Inputs::c, tot_lt_s(bit)
Outputs:d, tot_ld, tot_clr (bit)
signals for all tot_ld
tot_ld
tot_clr
ld
clr
tpt
datapath c c
Add
8
8 8
tot_clr
operations d Init Wait
tot_ld=1 tot_lt_s 8-bit
tot_lt_s 8-bit
and d=0 c’*
tot
c’*tot_lt_s < adder
tot_clr=1 8
conditions _lt
_s
’ Disp
Datapath
d=1
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tot_clr
logic
tot_ld
s1 s0 c n1 n0 d
– As in Ch3 0 0 0 0 0 1 0 0 1
– Table shown on right 0 0 0 1 0 1 0 0 1
Init
0 0 1 0 0 1 0 0 1
0 0 1 1 0 1 0 0 1
Inputs::c, tot_lt_s (bit)
0 1 0 0 1 1 0 0 0
Outputs:d, tot_ld, tot_clr (bit)
0 1 0 1 0 1 0 0 0
Wait
tot_ld
c c 0 1 1 0 1 0 0 0 0
Add tot_clr 0 1 1 1 1 0 0 0 0
d Init Wait 1 0 0 0 0 1 0 1 0
Add
tot_ld=1
tot_lt_s
d=0 c’* c’*tot_lt_s
tot 1 1 0 0 0 0 1 0 0
Disp
tot_clr=1 _lt
_s
’ Disp
d=1
Controller
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5
Step 1: Create a High-Level State Machine
• Let’s consider each step of the
RTL design process in more
detail Inputs: c (bit), a (8 bits), s (8 bits)
• Step 1 Outputs: d (bit)
Local registers: tot (8 bits)
– Soda dispenser example
c
– Not an FSM because:
• Multi-bit (data) inputs a and s Init Wait
• Local register tot tot= tot+a
• Data operations tot=0, tot<s, d=0 c’ (tot<s)
c’(tot<s)’
tot=tot+a. tot=0
– Useful high-level state machine: Disp
• Data types beyond just bits d=1
• Local registers
• Arithmetic equations/expressions
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6
Step 1 Example: Laser-Based Distance Measurer
T (in seconds)
B L
laser from button to laser
Laser-based
distance
sensor D 16 measurer S
to display from sensor
• Inputs/outputs
– B: bit input, from button to begin measurement
– L: bit output, activates laser
– S: bit input, senses laser reflection
– D: 16-bit output, displays computed distance
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S0 ?
a
L = 0 (laser off)
D = 0 (distance = 0)
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7
Step 1 Example: Laser-Based Distance Measurer
from button B
Inputs: B, S (1 bit each) L
Laser- to laser
Outputs: L (bit), D (16 bits) based
distance
B’ (button not pressed) to display
D 16 measurer S
from sensor
S0 S1 ?
B
L=0 (button
D=0 pressed)
• Add another state, call S1, that waits for a button press
– B’ – stay in S1, keep waiting
– B – go to a new state S2
S0 S1 S2 S3
B
L=0 L=1 L=0 a
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8
Step 1 Example: Laser-Based Distance Measurer
B L
Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) from button to laser
Lase
r-based
Local Registers: Dctr (16 bits) D 16
distance
measu rer S
to display from sensor
B’ S’ (no reflection)
S (reflection)
S0 S1 S2 S3 ?
B
L=0 Dctr = 0 L=1 L=0 a
D=0 (reset cycle Dctr = Dctr + 1
count) (count cycles)
B’ S’
S0 S1 S2 S3 S4
B S
L=0 Dctr = 0 L=1 L=0 D = Dctr / 2
D=0 Dctr = Dctr + 1 (calculate D)
9
Step 2: Create a Datapath
• Datapath must
– Implement data storage
– Implement data computations
• Look at high-level state machine, do
three substeps
– (a) Make data inputs/outputs be datapath
inputs/outputs
– (b) Instantiate declared registers into the
datapath (also instantiate a register for each Instantiate: to
data output) introduce a new
– (c) Examine every state and transition, and
instantiate datapath components and component into a
connections to implement any data design.
computations
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10
Step 2 Example: Laser-Based Distance Measurer
Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)
(c) (continued) Local Registers: Dctr (16 bits)
Examine every
state and B‘ S‘
transition, and
instantiate
S0 S1 S2 S3 S4
datapath B S
components and L=0 Dctr = 0 L=1 L=0 D = Dctr / 2
D=0 Dctr = Dctr + 1 (calculate D)
connections to
implement any Datapath
a
data computations
Dreg_clr >>1
16
Dreg_ld
16
D
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T0 R = E + F
A B A B add_A_s0 ⋅1
2× ⋅1
2×
+ + add_B_s0
T1 R = R + G A B
a
+
R R
R
(a) (b) (c)
(d)
• Introduce mux when one component input can come from
more than one source
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11
Step 3: Connecting the Datapath to a Controller
L
B to laser
from button
Controller from sensor
Dreg_clr S
Dreg_ld
• Laser-based distance
measurer example
Dctr_clr Datapath
• Easy – just connect all
Dctr_cnt
D
control signals
to display between controller and
16 300 MHz Clock
datapath
Datapath
Dreg_clr >>1
Dreg_ld 16
Dreg_ld
B’ S’
Dctr_clr Datapath
Dctr_cnt
D S0 S1 S2 S3 S4
to display B S
16 300 MHz Clock
L=0 Dctr = 0 L=1 L=0 D = Dctr / 2
D=0 Dctr = Dctr + 1 (calculate D)
Inputs: B, S
• FSM has same Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
structure as high-
level state machine B’ S’
a
– Inputs/outputs all
bits now S0 S1
B
S2 S3
S
S4
– Replace data
operations by bit L=0 L=0 L=1 L=0 L=0
Dreg_clr = 1 Dreg_clr = 0 Dreg_clr = 0 Dreg_clr = 0 Dreg_clr = 0
operations using Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 1
datapath Dctr_clr = 0 Dctr_clr = 1 Dctr_clr = 0 Dctr_clr = 0 Dctr_clr = 0
Dctr_cnt = 0 Dctr_cnt = 0 Dctr_cnt = 0 Dctr_cnt = 1 Dctr_cnt = 0
Digital Design (laser off) (clear count) (laser on) (laser off) (load D reg with Dctr/2)
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12
Step 4: Deriving the Controller’s FSM
B’ S’
B S
S0 S1 S2 S3 S4
Step 4
B L
to laser
Controller
Dreg_ld
Dreg_clr
Dreg_ld 16
Dctr_clr
Dctr_clr clear clear I
Dctr_cnt count Dctr: 16-bit Dreg: 16-bit
Dctr_cnt up-counter load register
D
to display Q Q
16 300 MHz Clock 16
16
D
B’ S’
• Implement
B S
S0 S1 S2 S3 S4 FSM as state
L=0 Dctr_clr = 1 L=1 L=0 Dreg_ld = 1 register and
Dreg_clr = 1 (laser on) Dctr_cnt = 1
(laser off)
(clear count)
(laser off)
Dctr_cnt = 0 logic (Ch3) to
(load D reg with Dctr/2)
(clear D reg) (count up) (stop counting) complete the
design
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13
5.3
14
RTL Example: Bus Interface
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits)
Outputs: D (32 bits)
Local register: Q1 (32 bits)
rd’ rd
((A = Faddr)
and rd’)
WaitMyAddress SendData
(A = Faddr)
D = “Z” and rd D = Q1
Q1 = Q
clk
Inputs
rd
State W W SD W W SD SD W
Outputs
D Z Q1 Z Q1 Z
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D_en
32
a
15
RTL Example: Bus Interface
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits)
Outputs: D (32 bits)
Local register: Q1 (32 bits)
rd’ rd A Faddr Q
Inputs: rd, A_eq_Faddr
((A =(bit)
Faddr)
Outputs: Q1_ld, D_enand
(bit)rd)’ 4 4 32
‘
rdSendData Q1_ld
rd WaitMyAddress rd ld
(A = Faddr) Q1
and (A_eq_Faddr
rd D = Q1
D = “Z”
Q1 = Q and rd)‘
= (4-bit) 32
WaitMyAddress SendData A_eq_Faddr
A_eq_Faddr
D_en = 0 and rd D_en = 1 D_en
a Q1_ld = 1 Q1_ld = 0 32
Datapath
Bus interface
16
RTL Example: Video Compression – Sum of Absolute
Differences
compare Each is a pixel, assume
Frame 1 Frame 2
represented as 1 byte
(actually, a color picture
might have 3 bytes per
pixel, for intensity of
red, green, and blue
components of pixel)
• Need to quickly determine whether two frames are similar
enough to just send difference for second frame
– Compare corresponding 16x16 “blocks”
• Treat 16x16 block as 256-byte array
– Compute the absolute value of the difference of each array item
– Sum those differences – if above a threshold, send complete frame
for second frame; if below, can use difference method (using
another technique, not described)
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A SAD
256-byte array
integer
B sad
256-byte array
go
<
)!(i
6
5
2
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17
RTL Example: Video Compression – Sum of Absolute
Differences
A SAD
Inputs: A, B (256 byte memory); go (bit)
Outputs: sad (32 bits)
B sad Local registers: sum, sad_reg (32 bits); i (9 bits)
go
S0 !go
go
• S0: wait for go sum = 0 a
S1
i=0
• S1: initialize sum and index
(i<256)’
• S2: check if done (i>=256) <
)!(i
6
5
2
S2
• S3: add difference to sum, i<256
sum=sum+abs(A[i]-B[i])
increment index S3
i=i+1
• S4: done, write to output
S4 sad_reg = sum
sad_reg
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i<256 32 32 8
sum=sum+abs(A[i]-B[i]) sad_reg_ld
S3
i=i+1
<
t_
)l(i!
6
5
2
sad_reg +
S4 sad_reg=sum 32
Datapath
sad
• Step 2: Create datapath
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18
RTL Example: Video Compression – Sum of Absolute
Differences
go AB_rd AB_addr A_data B_data
i_lt_256
<256 8 8
S0 go’
9
go i_inc
S1
sum=0 sum_clr=1
i_clr
i –
i=0 i_clr=1
8
?
S2 sum_ld
i<256 i_lt_256 sum 32 abs
sum_clr
S3 sum=sum+abs(A[i]-B[i])
sum_ld=1; AB_rd=1
<
)!(i
6
5
2
32 32 8
i=i+1 i_inc=1 sad_reg_ld
<
t_
)l(i!
6
5
2
S4 sad_reg=sum a
sad_reg +
<
t_
)l(i!
6
5
2
sad_reg_ld=1
Controller 32
sad
• Step 3: Connect to controller
Digital Design • Step 4: Replace high-level state machine by FSM
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19
RTL Design Pitfalls and Good Practice
• Common pitfall: Assuming Local registers: R, Q (8 bits)
register is update in the
state it’s written R<100 C
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Q ? ? 99 99
(b)
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20
RTL Design Pitfalls and Good Practice
• Common pitfall: Inputs: A, B (8 bits) Inputs: A, B (8 bits)
Reading outputs Outputs: P (8 bits) Outputs: P (8 bits)
Local register: R (8 bits)
– Outputs can only be
written
– Solution: Introduce S T S T
additional register,
which can be written P=A P=P+B R=A P=R+B
and read P=A
(a) (b)
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21
Control vs. Data Dominated RTL Design
• Designs often categorized as control-dominated or data-
dominated
– Control-dominated design – Controller contains most of the
complexity
– Data-dominated design – Datapath contains most of the complexity
– General, descriptive terms – no hard rule that separates the two
types of designs
– Laser-based distance measurer – control dominated
– Bus interface, SAD circuit – mix of control and data
– Now let’s do a data dominated design
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22
Data Dominated RTL Design Example: FIR Filter
• FIR filter
– “Finite Impulse Response” X Y
– Simply a configurable weighted 12 digital filter 12
sum of past input values clk
– y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
• Above known as “3 tap”
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
• Tens of taps more common
• Very general filter – User sets the
constants (c0, c1, c2) to define
specific filter
– RTL design
• Step 1: Create high-level state
machine
– But there really is none! Data
dominated indeed.
• Go straight to step 2
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clk
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23
Data Dominated RTL Design Example: FIR Filter
• Step 2: Create datapath X Y
12 digital filter 12
(cont.) clk
– Instantiate registers for
c0, c1, c2
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
– Instantiate multipliers to
compute c*x values
3-tap FIR filter
x(t) x(t-1) x(t-2)
c0 c1 c2
xt0 xt1 xt2
X
a
clk
∗ ∗ ∗
Y
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clk
a
∗ ∗ ∗
+ +
Y
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24
Data Dominated RTL Design Example: FIR Filter
• Step 2: Create datapath (cont.) X Y
12 digital filter 12
– Add circuitry to allow loading of clk
particular c register
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
CL 3-tap FIR filter
e
3
Ca1 2x4 2
Ca0 1
0
C
clk
* * *
+ + yreg
Y
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25
5.4
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Critical Path
• Example shows four paths
– a to c through +: 2 ns
– a to d through + and *: 7 ns
a b
– b to d through + and *: 7 ns
– b to d through *: 5 ns
• Longest path is thus 7 ns 2 ns + * 5 ns
delay delay
• Fastest frequency 7 ns 7 ns
2 ns
5 ns
7 ns
7 ns
– 1 / 7 ns = 142 MHz c d
Max
(2,7,7,5)
= 7 ns
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26
Critical Path Considering Wire Delays
• Real wires have delay too
– Must include in critical path
• Example shows two paths
– Each is 0.5 + 2 + 0.5 = 3 ns clk a b
• Trend
0.5 ns
– 1980s/1990s: Wire delays were tiny 0.5 ns
compared to logic delays
– But wire delays not shrinking as fast as + 2 ns
logic delays
• Wire delays may even be greater than 0.5 ns
3 ns
s
n
3
3 ns
logic delays!
c
• Must also consider register setup and
hold times, also add to path
• Then add some time to the computed
path, just to be safe
– e.g., if path is 3 ns, say 4 ns instead
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automatically very
helpful
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5.5
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28
Converting from C to High-Level State Machine
• Convert each C construct to
equivalent states and
transitions
• Assignment statement
target= a
– Becomes one state with target = expression;
expression
assignment
• If-then statement
– Becomes state with condition !cond
check, transitioning to “then” cond
if (cond) {
statements if condition true, // then stmts (then stmts) a
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29
Simple Example of Converting from C to High-
Level State Machine
Inputs: uint X, Y
Outputs: uint Max !(X>Y) !(X>Y)
X>Y X>Y
if (X > Y) {
Max = X; (then stmts) (else stmts) Max=X Max=Y
}
else {
Max = Y;
(end) (end)
}
a a
30
5.6
Memory Components
• Register-transfer level
design instantiates datapath
components to create
datapath, controlled by a
controller
M words
– A few more components are
often used outside the
controller and datapath
• MxN memory
– M words, N bits wide each N-bits
wide each
• Several varieties of memory,
which we now introduce M×N memory
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31
RAM Internal Structure
32
data
10
addr Let A = log2M wdata(N-1) wdata(N-2) wdata0
1024x32
rw RAM word bit storage
en enable block
d0 (aka “cell”)
addr0 a0 word
addr1 a1 AxM
d1
r
d
a
decoder
addr(A-1) a(A-1) data cell
word word
e d(M-1) enable enable
clk
en rw data
rw to all cells
d1
decoder
en a(A-1) data cell
addr(A-1) a
word word
e d(M-1) enable enable
clk
rw data
en
rw to all cells
word 0
rdata(N-1) rdata(N-2) rdata0 enable
32
Static RAM (SRAM)
wdata(N-1) wdata(N-2) wdata0
32 Let A = log2 M
data word bit storage
10 enable block ,,
,,
addr d0 (aka cell )
1024x32 addr0 a0 word
rw RAM addr1 a1 A ⋅ M
addr
d1
decoder
en a(A-1) data cell
addr(A-1)
word word
e d(M-1) enable enable
clk
rw data
en
rw to all cells
SRAM cell
• “Static” RAM cell rdata(N-1) rdata(N-2) rdata0
data data’
– Reading this cell 1 1
• Somewhat trickier d
• When rw set to read, the RAM logic sets
1 0
both data and data’ to 1
a
• The stored bit d will pull either the left line or
the right bit down slightly below 1 1 1 <1
word
• “Sense amplifiers” detect which side is enable
slightly pulled down To sense amplifiers
d1
decoder
en a(A-1) data cell
addr(A-1)
word word
e d(M-1) enable enable
clk
rw data
en
rw to all cells DRAM cell
data
• “Dynamic” RAM cell rdata(N-1) rdata(N-2) rdata0
cell
– 1 transistor (rather than 6)
word
– Relies on large capacitor to store bit enable
d
capacitor
• Write: Transistor conducts, data voltage slowly
level gets stored on top plate of capacitor discharging
d discharges
(b)
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33
Comparing Memory Types
• Register file MxN Memory
– Fastest implemented as a:
34
RAM Example: Digital Sound Recorder
4096⋅ 16
RAM
data
addr
rw
en
wire 16
analog-to- digital-to-
digital 12 analog
ad_buf Ra Rrw Ren wire
microphone converter converter
ad_ld processor da_ld
• Behavior speaker
– Record: Digitize sound, store as series of 4096 12-bit digital values in RAM
• We’ll use a 4096x16 RAM (12-bit wide RAM not common)
– Play back later
– Common behavior in telephone answering machine, toys, voice recorders
• To record, processor should read a-to-d, store read values into
successive RAM words
– To play, processor should read successive RAM words and enable d-to-a
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35
RAM Example: Digital Sound Recorder
4096x16
– Now create play behavior RAM data bus
– Use local register a again,
create state machine that 16
counts from 0 to 4095 again analog-to-
digital 12
digital-to-
analog
ad_buf Ra Rw Ren
• For each a converter converter
ad_ld processor da_ld
– Read RAM
– Write to digital-to-analog conv.
• Note: Must write d-to-a one Play behavior
cycle after reading RAM, when
Local register: a (12 bits)
the read data is available on
the data bus a<4095
V W
– The record and play state a=0
a
ad_buf=0
machines would be parts of a Ra=a
X
larger state machine controlled Rrw=0
Ren=1
by signals that determine when da_ld=1
a=a+1
to record or play
a=4095
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36
Read-Only Memory – ROM
32
data
10 1024x32
addr Let A = log2M
ROM
en bit storage
word
enable block
ROM block symbol d0 (aka “cell”)
addr0 a0 word
addr1 a1 AxM
d1
r
d
a
decoder
addr(A-1) a(A-1) data
word word
e d(M-1) enable enable
clk
en data
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ROM Types
• If a ROM can only be read, how Let A = log2 M
word
enable
bit storage
block ,,
d1
first place?
decoder
data
addr(A-1) a(A-1) cell
word word
e d(M-1) enable enable
programming
data(N-1) data(N-2) data0
– Several methods
• Mask-programmed ROM 1 data line 0 data line
37
ROM Types
• Fuse-Based Programmable Let A = log2 M
word
enable
bit storage
block ,,
,,
d0 (a cell )
ROM addr0
addr1
a0
a1 A ⋅ M
word
addr
d1
decoder
data
addr(A-1) a(A-1) cell
as 1s enable
Digital Design
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ROM Types
• Erasable Programmable ROM Let A = log2 M
word bit storage
enable block ,,
(EPROM) addr0
addr1
a0
a1 A ⋅ M
d0
,,
(a cell )
word
addr
d1
decoder
– Uses “floating-gate transistor” in each cell addr(A-1) a(A-1)
data
word word
cell
t
1 0
gate) will be 1 word
n
ti
g
eÐeÐ
– 2-bit word on right stores “10” enable
a
t
e
trapped electrons
idea is necessary here
– To erase, shine ultraviolet light onto chip
• Gives trapped electrons energy to escape
• Requires chip package to have window
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38
ROM Types
• Electronically-Erasable Programmable ROM
(EEPROM)
– Similar to EPROM
• Uses floating-gate transistor, electronic programming to
trap electrons in certain cells
– But erasing done electronically, not using UV light
– Erasing done one word at a time
• Flash memory
– Like EEPROM, but all words (or large blocks of
words) can be erased simultaneously r
o
32
data
– Become common relatively recently (late 1990s) n
ti
a
g
10
t
e
addr
• Both types are in-system programmable
t
en 1024x32
– Can be programmed with new stored bits while in the EEPROM
system in which the ROM operates write
• Requires bi-directional data lines, and write control input busy
• Also need busy output to indicate that erasing is in
progress – erasing takes some time
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4096x16 ROM
samples, stored
in ROM “Hello there!”
a
16 a
digital-to-
analog vibration
Ra Ren converter sensor
da_ld
processor
39
ROM Example: Talking Doll
Local register: a (12 bits)
4096x16 ROM
v a<4095
a=0 S T
a
16 Ra=a
digital-to- Ren=1
analog U a
Ra Ren converter v’
da_ld=1
da_ld a=4095 a=a+1
processor
v
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40
ROM Example: Digital Telephone Answering Machine
Using a Flash Memory
• High-level state machine 4096x16 Flash
d r n
e
16
er=1 analog-to-
digital 12 digital-to-
ad_buf Ra Rrw Ren er bu
converter analog
– Wait for flash to finish ad_ld processor converter
da_ld
erasing by waiting for
rec
bu=0 record play
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41
5.7
Queues
• A queue is another component
sometimes used during RTL
back front
design
• Queue: A list written to at the
back, from read from the front
– Like a list of waiting restaurant
customers write items read (and
to the back remove) items
• Writing called a push, reading of the queue from front of
called a pop the queue
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Queues
7 6 5 4 3 2 1 0
• Queue has addresses, and two
pointers: rear and front
– Initially both point to 0
• Push (write) rf
7 6 5 4 3 2 1 0
– Item written to address pointed to
by rear A
A a
– rear incremented
• Pop (read) r f
– Item read from address pointed 7 6 5 4 3 2 1 0
to by front
– front incremented B B A a
7) B A
Digital Design r f
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42
Queues
• Treat memory as a circle 7 6 5 4 3 2 1 0
– If front or rear reaches 7, next (incremented)
value should be 0 rather than 8 (for a queue B A
with addresses 0 to 7)
r f
• Two conditions of interest
– Full queue – no room for more items 0
• In 8-entry queue, means 8 items present
1 7 a
• No further pushes allowed until a pop occurs
• Causes front=rear B
– Empty queue – no items
f
• No pops allowed until a push occurs
2 r
r
6
• Causes front=rear
– Both conditions have front=rear
• To detect whether front=rear means full or
empty, need state machine that detects if
previous operation was push or pop, sets full 3 5
or empty output signal (respectively) 4
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Queue Implementation
• Can use register file for 16
8⋅ 16 register file
16
wdata rdata
item storage wdata rdata
3 3
• Implement rear and front waddr raddr
using up counters wr rd
– rear used as register file’s
clr
write address, front as read wr clr
address inc
inc
rd 3-bit 3-bit
• Simple controller would up counter up counter
Controller
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43
Common Uses of a Queue
• Computer keyboard
– Pushes pressed keys onto queue, meanwhile pops and sends to
computer
• Digital video recorder
– Pushes captured frames, meanwhile pops frames, compresses
them, and stores them
• Computer network routers
– Pushes incoming packets onto queue, meanwhile pops packets,
processes destination information, and forwards each packet out
over appropriate port
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44
5.8
Province 2
• Hierarchy
Province 3
Province 1
CityF
– An organization with a few items at the CityB
top, with each item decomposed into other CityE
items CityC
CityG
– Common example: A country Country A
• 1 item at the top (the country) Map showing all levels of hierarchy
• Country item decomposed into
state/province items
• Each state/province item decomposed into
Province 2
Province 3
Province 1
city items
• Hierarchy helps us manage complexity P
o
P
o
P
n
i
v n
i
v
n
i
v
r r
o o
c c
n
i
v n
i
v
2
e
1
e
Country A
n
vi
c c
1
e
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Frank Vahid
• Abstraction
– Hierarchy often involves not just grouping
items into a new item, but also associating
higher-level behavior with the new item,
known as abstraction
• e.g., an 8-bit adder has an understandable a7.. a0 b7.. b0
high-level behavior – it adds two 8-bit binary
numbers 8-bit adder ci
– Frees designer from having to remember,
co s7.. s0
or even from having to understand, the P
r
P
r
P
lower-level details
o o
P P
n
i
v n
i
v
n
i
v
r r
o o
c c
n
i
v n
i
v
2
e 3
e
1
e
n
vi
c c
2
e 3
e
1
e
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45
Hierarchy and Composing Larger Components
from Smaller Versions
4⋅ 1
• A common task is to compose smaller components i0 i0
into a larger one i1 i1 a
– Gates: Suppose you have plenty of 3-input AND gates, i2 i2 d
but need a 9-input AND gate
i3 i3
• Can simple compose the 9-input gate from several 3-input
gates 2⋅ 1
s1 s0 i0
– Muxes: Suppose you have 4x1 and 2x1 muxes, but
need an 8x1 mux d
4⋅ 1 i1
• s2 selects either top or bottom 4x1
• s1s0 select particular 4x1 input i4 i0 s0
• Implements 8x1 mux – 8 data inputs, 3 selects, one output i5 i1
i6 P
r
P
r
i2 P
r
d
o o
P
P
r
P
r
n
i
v
n
i
v
i7 i3
n
i
v
o o
c c
n
i
v n
i
v
2
e 3
e
1
e
n
vi
c c
1
e
2
e 3
e
s1 s0
s1 s0 s2
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P P
8 8 8 8
r r
o o
P P
n
i
v
r r
o o
data(31..0)
r
n
i
v n
i
v
3
e
n
vi
c c
2
e 3
e
10
c
1
e
r
d
a
1024x32
ROM
n
e
data
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46
Hierarchy and Composing Larger Components
from Smaller Versions
11
a9..a0
• Creating memory with more words r
d
a
addr
– Put memories on top of one another until the a10 1x2 d0 1024x8
number of desired words is achieved i0 dcd ROM
– Use decoder to select among the memories e d1 en data
• Can use highest order address input(s) as 8
decoder input n
e
r
8 P
o o
a 0 0 0 0 0 0 0 0 0 1 0
P
1024x8
P
n
i
v n
i
v
ROM
r r
o o
c c
n
i
v n
i
v
2
e 3
e
0 1 1 1 1 1 1 1 1 1 0
n
vi
en data
c
2
e 3
e
a
0 1 1 1 1 1 1 1 1 1 1
c
which memory
to access 1 0 0 0 0 0 0 0 0 0 0 words and wider words, can first
1 0 0 0 0 0 0 0 0 0 1 addr
compose to enough words, then
1 0 0 0 0 0 0 0 0 1 0 1024x8
ROM
widen.
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Chapter Summary
– Modern digital design involves creating processor-level components
– Four-step RTL method can be used
• 1. High-level state machine 2. Create datapath 3. Connect datapath
to controller 4. Derive controller FSM
– Several example
• Control dominated, data dominated, and mix
– Determining fastest clock frequency
• By finding critical path
– Behavioral-level design – C to gates
• By using method to convert C (subset) to high-level state machine
– Additional RTL components
• Memory: RAM, ROM
• Queues
– Hierarchy: A key concept used throughout Chapters 2-5
Digital Design
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47