IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.

3, MARCH 2010 631

Observer-Controller Digital PLL

Won Namgoong, Senior Member, IEEE

Abstract—A digital phase-locked loop (DPLL) has been re-

cently developed to exploit the increasing transistor speed of
modern process technology. By employing a digitally controlled
oscillator (DCO) and a time-to-digital converter (TDC), the loop
filter of a DPLL becomes all-digital. Instead of designing the
loop filter by digitizing a continuous-time loop response as has Fig. 1. Digital phase-locked loop.
been commonly done, more sophisticated control schemes can be
employed. In this paper, we propose to design the feedback loop in
the time-domain by first modeling the DCO and TDC as a noisy The DPLL reported in [1]–[4] is basically a digitized ver-
“plant” in state-space form. Based on a Kalman observer of the
“plant,” the proposed approach then generates optimal control sion of a conventional analog PLL. The digital loop filter is
signals that accurately account for the additive noise as well as constructed by converting a continuous-time loop response to
the transport delay in the digital feedback system. The proposed a discrete-time -domain approximation by sampling at the ref-
observer-controller loop filter achieves rapid transient response erence clock frequency. This approximation is valid as long as
time and significantly reduces the steady-state phase noise jitter the loop bandwidth is a small fraction (e.g., typically at least
compared to the conventional DPLL. Furthermore, the proposed
approach enables modeling of other noise sources such as due to ten times smaller [5], [6]) of the reference clock frequency. Al-
oscillator pulling, which is a common problem in many modern though its loop bandwidth can, in principle, be set to be as wide
transceivers. By employing the observer-controller loop filter, as approximately one-tenth of the reference clock frequency,
the effect of oscillator pulling can be effectively removed without the cycle delays of the digital feedback loop that are inevitably
degrading the overall phase noise performance. present in any practical system require that the loop bandwidth
Index Terms—Digital phase-locked loop (DPLL), digitally con- be significantly reduced to maintain stability. If the VCO phase
trolled oscillator (DCO), Kalman filter, oscillator pulling, time-to- noise is high relative to reference clock jitter, the loop band-
digital converter (TDC). width may not be as wide as needed to achieve the optimum
phase noise performance. Furthermore, the narrow loop band-
width may severely limit the transient response time to a step
I. INTRODUCTION
input frequency.
In many highly integrated transceivers, another sinusoidal
HASE-LOCKED loop (PLL) is commonly used to gen- signal or its harmonics may couple with the oscillator circuit
P erate the desired RF frequency based on a reference os-
cillator, which typically operates at a much lower frequency
through the substrate, supply line, or other parasitic paths. This
injected signal pulls the oscillator frequency away from its
(e.g., 26 MHz). Recently, a digital PLL (DPLL) has been de- desired operating frequency. If the injection frequency offset
veloped to exploit the increasing transistor speed of modern relative to the desired oscillator frequency is well within the
process technology [1]–[4]. The salient features of the DPLL loop bandwidth, the PLL can suppress this pulling effect. How-
are that the phase detector (PD) is performed digitally using a ever, since the loop bandwidth needs to be narrow to maintain
time-to-digital converter (TDC), and the voltage-controlled os- stability, the range of injection frequencies that the oscillator
cillator (VCO) is digitally controlled and referred to as a digi- can suppress is very limited. Oscillator pulling, therefore, can
tally controlled oscillator (DCO). A simplified block diagram of be a major source of performance degradation in conventional
the DPLL is shown in Fig. 1. The use of TDC and DCO enable DPLL.
the loop filter to be fully digital. The all-digital nature of the As the loop filter is completely digital in DPLL, we can em-
ploy more sophisticated control schemes than the currently em-
loop filter enables the DPLL to enjoy many implementation ad-
vantages, among which are improved noise immunity from cir- ployed loop filter. The DCO and TDC can be modeled as a noisy
cuit nonidealities (e.g., charge pump feedthrough, mismatches, “plant” in state-space form. When viewed from this perspective,
etc.), compatibility with digital deep-submicron CMOS process, controlling the noisy plant to generate the desired frequency
can be posed as a linear regulator problem, which is a classical
simplified testing and calibration, and ease of integration with
digital baseband circuitries. problem of optimal linear control theory. As the optimal con-
trol is a linear feedback of the state vectors, which cannot be
observed directly, a Kalman filter is used to estimate the state
Manuscript received January 25, 2009; revised April 10, 2009. First published
June 10, 2009; current version published March 05, 2010. This work was sup-
variables. Such a system consisting of the optimal controller and
ported in part by the National Science Foundation (NSF) under Contract CCF the optimal observer (i.e., Kalman filter) is stable by the separa-
07-33124. This paper was recommended by Associate Editor G. Manganaro. tion principle in control theory.
The author is with the Electrical Engineering Department, The University Designing the feedback in the time domain using observer-
of Texas at Dallas, Richardson, TX 75080-3021 USA. (e-mail: namgoong@ut-
dallas.edu). controller approach instead of using poles and zeros in the fre-
Digital Object Identifier 10.1109/TCSI.2009.2024985 quency domain as in the conventional DPLL provides several
1549-8328/$26.00 © 2010 IEEE

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
632 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

advantages. The transient response performance is not limited

by the loop filter bandwidth, enabling rapid transient response
time. In addition, the proposed approach enables a systematic
design of optimal control signals that account for the additional
poles introduced by cycle latency that are inevitably present in
a digital feedback system. Another important advantage is that
the proposed state-space approach enables modeling of other
sources of noise such as oscillator pulling. By incorporating Fig. 2. Discrete-time model of second-order PLL with N transport delay.
in the state-space model, the effect of oscillator pulling can be
effectively removed without degrading the overall phase noise
performance. The more general case when also includes the effect of
The organization of this paper is as follows. In Section II, we flicker noise will be addressed in a future publication.
develop a state-space model of the DCO and TDC. In addition,
the conventional PLL is also modeled in state-space form. Based B. Conventional Second-Order Loop
on the system model developed, the proposed observer-con- Since the DCO is updated at the reference clock frequency,
troller-based loop filter is proposed in Section III. Its steady- the DPLL can be modeled in discrete time. A discrete-time
state phase noise jitter and spectrum are also derived in this sec- model of the second-order PLL with transport delay of cy-
tion. In Section V, the proposed loop filter is employed to miti- cles is shown in Fig. 2. The effect of transport delay is mod-
gate the effects of oscillator pulling. Simulation results are pre- eled by in the loop filter. The DPLL in Fig. 2 is a
sented in Section VI and conclusions are drawn in Section VII. pole system because of the additional poles introduced by the
transport delay. In Fig. 2, the dc-offset noise at the DCO (i.e.,
II. SYSTEM MODEL AND CONVENTIONAL DPLL
) is filtered out by the loop filter, which is a high-pass
In this section, we first develop a mathematical model of the filter from the DCO input. Analysis of the conventional DPLL
DCO. A conventional second-order loop filter with transport has been reported in [9]–[11].
delay is then described. The conventional second-order DPLL is Denoting the desired excess phase at discrete time as ,
used in subsequent sections as a reference for comparison when the difference equations for the digital PD output and the
quantifying the performance of the proposed DPLL. In the last second-order loop filter output are given, respectively, as
section, a state-space model of the DCO and the TDC is pre- follows:
sented.

A. DCO Model
(4)
The DCO can be modeled as a conventional VCO with a
quantized input control signal. The VCO output is given by
(5)

where for , represents TDC quantization

noise, and and are scaling factors of the second-order loop
filter. Noise can also be used to model jitter of the reference
clock and any additional noise from the frequency divider prior
(1) to TDC.
From Fig. 2, the open-loop transfer function in -domain is
where is the VCO frequency, is the phase noise, is
the VCO control signal voltage, is the nominal frequency that
(6)
is multiple of the reference clock frequency , and .
Since the DCO is updated at the reference clock frequency ,
A commonly used approach to ensure the stability of the
the excess phase in (1) can be written as a difference equa-
-order DPLL system is to set the loop gain (via and ) so
tion. Sampling in (1) at , where is an integer,
that the phase margin is sufficiently high (e.g., 45 ) [12]. To
and assuming is a Wiener phase noise [7], [8], the excess
do this, we first convert the discrete-time open-loop frequency
phase can be written in discrete time as
response to continuous-time using the following approximation
(2) of the -operator [11]:

where is the additive white Gaussian noise in Wiener phase (7)

noise, is the DCO input quantization noise, and
where is the angular radian frequency. This approximation
is valid as of interest, which correspond to frequencies near
(3) the loop bandwidth, is small relative to the sampling reference
frequency.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
NAMGOONG: OBSERVER-CONTROLLER DIGITAL PLL 633

may need to be much wider than the loop bandwidth required

for stability. Another drawback is that the response time to a
frequency step may be very slow. Since the response time is
approximately the inverse of the loop bandwidth, a maximum
loop bandwidth of 310 kHz in our example earlier requires a re-
sponse time in excess of 3 s, which may be too high in many
applications.

C. State-Space Model of DCO and TDC

Unlike conventional loop filter, the PLL loop in the proposed
approach is closed using advanced signal processing and con-
trol theory techniques. The VCO and PD are viewed as a noisy
“plant” that needs to be controlled. The states of the plant are
estimated using a Kalman filter. State-vector feedback is then
employed to control the plant.
The VCO and PD represent the plant. This section describes
Fig. 3. Normalized maximum loop bandwidth versus number of transport cycle the modeling of the plant, so that appropriate estimator and con-
delaysN assuming  : and phase margin of 45 . =07 troller can be determined. Let the desired excess phase be given
by

Substituting (7) into (6), the approximate open-loop transfer (12)

function in the -domain is
The output of an ideal PD (i.e., no additive noise) can then be
(8) written as

Since the poles introduced by transport delay are at ,

we can reduce the loop bandwidth so that the closed loop still
behaves as a second-order system. By comparing (8) with (13)
to the standard form type-II open-loop filter [13], the natural
frequency and the damping factor ratio can be shown to be As the objective is to drive both the phase and frequency errors
(i.e., and ) to zero, simply attempting to minimize
(9) the phase error can result in a constant frequency error. To make
this objective more explicit, we can rewrite the previous equa-
(10)
tion as

For the commonly employed damping factor ratio of (14)

and phase margin of 45 , the maximum loop bandwidth normal-
(15)
ized by is plotted as a function of transport delay cycles in
Fig. 3. For a transport delay of five clock cycles, the maximum
where , , and control
loop bandwidth is approximately 1% of the reference clock fre-
signals and are related to the DCO input by
quency, e.g., 310 kHz for .
The phase noise performance at steady state can be readily
analyzed by computing the power transfer function from the (16)
noise sources to the phase error output
In (15), no additive noise is assumed when updating . In
practice, small noise should be added for numerical stability and
(11) to model any variations in .
where is the variance of , and is the sum of the variance Representing (14) and (15) in matrices, the state-space equa-
of and . The noise sources are assumed independent and tion can be written as
white. The phase noise jitter can be computed by integrating the
power spectral density in (11). (17)
In the presence of oscillator pulling, this constraint on the (18)
maximum loop bandwidth may limit the PLL’s ability to sup-
press the effects of the injected signal. Even in the absence of os- where , ,
cillator pulling, the loop phase noise performance may be poor , and . The plant output is the PD
if the DCO noise is large relative to the TDC noise. To best bal- output with representing the quantization noise of the TDC,
ance the effects of both the DCO and TDC noise, the bandwidth the noise in the frequency divider, and reference clock jitter. It

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
634 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

(25)
(26)

where is the variance of in (18), is the

correlation matrix of in (17), and is an identity matrix. The
Kalman gain values can be pre-computed and stored in memory
for lookup. To reduce the size of the lookup table, a smaller set
of precomputed Kalman gain values can be used at the expense
of slightly reduced convergence speed.
The SVF gain can be determined by employing the linear
Fig. 4. Overall system model. quadratic regulator (LQR) method. Given the state values, the
objective in LQR is to determine such that the following
cost function is minimized:
can be readily shown that the discrete-time model of the con-
ventional second-order loop can be represented in state-space (27)
form with the control signals given by
where and are the weighting factors for the states
(19) and input, respectively. The purpose of this cost function is to
reduce the system state to zero quickly at modest control ef-
(20) fort. Weighting factors and , both of which are usu-
ally diagonal matrices, penalizes the trajectories of the system
state and control unit, respectively.
III. OBSERVER-CONTROLLER DPLL In our system, we set the elements of high and
low. A high ensures that the state variables, which repre-
For ease of explanation, we first describe the feedback con-
sent the excess phase and frequency, are kept as close to zero as
troller with no transport delay. The controller is then modified
possible. A low allows the DCO input to change abruptly,
to account for the loop latency. In the subsequent two sections,
which is possible since the DCO input is digital. A larger
the steady-state jitter performance and the spectral density using
may be needed if the instantaneous DCO input exceeds its dy-
the proposed feedback controller are derived.
namic range. By setting high and low, the closed-
A. Proposed Observer-Controller Loop Filter loop eigenvalues are very close to the origin, suggesting a dead-
beat system. A deadbeat system brings the output to zero in the
Unlike in the conventional loop filter where the locations of fewest number of time steps. For an th-order system, the min-
the poles are set by fixing stability margins, all of the closed imum number of steps is . In the remainder of this paper, we
loop system poles can be placed in any desired locations by assume that the SVF gain is set to be a deadbeat system, i.e.,
employing a proportional feedback of the state variables, i.e., .
In the presence of transport delay , the observer at time
(21) index needs to predict based on observations up to time
. The SVF then operates on the predicted state value, i.e.,
The state-variable feedback (SVF) requires knowledge of
states and , which are not available from the plant. A (28)
Kalman filter observer, therefore, is used to estimate the two
states based on the plant output . The Kalman filter is able where the -step prediction is given by
to reconstruct the state vector from measurement output
since the system matrix is fully observable, i.e., is
full-rank. The SVF operates on the estimated state vectors as if (29)
they were the actual states. The overall system model is shown
in Fig. 4. The block diagram of the overall system model is illustrated in
The Kalman filter state estimates are updated as follows: Fig. 4.

(22) B. Steady-State Phase Noise Jitter Analysis

(23) Assuming a deadbeat system (i.e., ), the state-
space equation in (17) becomes
where represents the estimate of based on all prior
observations up to . is the Kalman gain, which is recur- (30)
sively updated using the following set of well-known equations
[14]: and the variance of is

(24) (31)

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
NAMGOONG: OBSERVER-CONTROLLER DIGITAL PLL 635

where represents the expectation operation, and is

a 2 2 correlation matrix of . At steady state,
i.e., as , only the (0,0)th element of is nonzero,
since in (15) is modeled without additive noise. Therefore,
at steady state, the plant becomes effectively a first-order system
with and a scalar value.
To compute in (31), we need to first determine
as . To do this, we compute the scalar Kalman gain
as . From (24), the steady-state Kalman gain value,
denoted as , becomes

(32) Fig. 5. Observer structure.

Substituting (32) in (25) then combining with (26), we have

(33)

Since

(34)
(38)
the variance of as in (31) can be shown to be
where is the steady-state Kalman gain given in (32). The
first and second equalities are obtained by recursively expanding
to using (30). The third equality results from (22)
(35) and (23). The final equality is simply the sum of finite geometric
To better understand the effects of TDC noise , DCO noise series. From (31) and (35), we can readily compute
, and transport delay on the overall jitter performance, as , i.e.,
we make simplifying assumptions. If , the jitter
(39)
variance in (35) simplifies to
Combining (39) with (38), the steady-state auto-correlation
function of becomes
(36) (40)
As is clear from (36), output jitter is directly proportional to where the dependency on transport delay is buried in the
transport delay and is independent of when . phase noise jitter variance given in (35). Performing the
If , the jitter variance in (35) becomes Fourier transform on (40), the phase noise spectrum is given by
(37)

Even if , has a multiplicative effect on the phase

noise jitter. Hence, reducing DCO noise is critical to re- (41)
ducing the overall phase noise jitter.

C. Phase Noise Spectrum Analysis The approximation assumes that , which

As described in the previous section, the plant becomes ef- is valid for sufficiently small (i.e., frequencies much less
fectively a first-order system at steady state with and than ). As evident from (41), the phase noise spectrum is
state vector a scalar value. To determine the phase noise Lorentzian, i.e., the shape of the power spectrum of a first order
spectrum, we compute the auto-correlation of for transport lowpass filter. The effect of transport delay is to simply
delay of assuming a deadbeat system. The auto-correlation scale up the spectrum, since has approximately a linear
of at steady state can be expressed as dependency on .

IV. LOOP FILTER IMPLEMENTATION

The loop filter of the proposed observer-controller DPLL can
be decomposed into two components, namely the observer (or

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
636 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

Kalman estimator) and the controller in Fig. 4. To determine the

structure of the Kalman observer, we can rewrite (23) as

(42)
(43)

where the Kalman gain at the th time index is

. Substituting (43) into (42) and rearranging,

(44) Fig. 6. Controller structure with N transport delay.

The observer structure of (44) is shown in Fig. 5. If we as-

sume that no control signal is applied (i.e., , [15]. As this reduction is at the expense of increased capaci-
for all ), the observer structure is that of a classical second-order tance at the input bus, a combination of direct and transposed
PLL. The difference is that the weighting of the proportional and forms can also be used. Although a direct-form realization is
integral coefficients is time-varying according to the Kalman shown in Fig. 6 for clarity of explanation, other structures can
gain values. In practice, the Kalman gain values can be precom- be employed depending on the implementation constraints.
puted and stored in a lookup table. Approximate Kalman gain
values can also be used to simplify the multiplier (e.g., to simple A. Relation to Conventional DPLL
shifts and adds) at the expense of some performance degrada- The proposed observer-controller loop filter structure is in
tion. Based on the difference between the actual and the esti- general different from the conventional loop filter except when
mated PD output (i.e., ), the observer attempts to there is no transport delay (i.e., ). When , (45) and
optimally estimate the next PD output . Signals and (46) simplify to
, which are generated by the controller, are applied to ad-
just the state values of the observer to account for the DCO input (47)
signal.
(48)
The controller of the loop filter operates on the state variables
of the observer to generate the DCO input signal . To deter-
Using (16), the relationship between the loop filter input and
mine the structure of the controller, we substitute (29) into (28)
output (or DCO input) becomes
with to obtain

(49)

(45)
Compared to the conventional loop filter given in (5), the pro-
portional–integral structure is the same. The only difference is
(46) that the fixed proportional gain and integral gain of the
conventional loop filter are replaced with Kalman gain values
and , respectively. Therefore, by appropriately
The DCO input can be determined from and selecting and , the steady-state jitter variance in (35)
using (16). The controller structure, which is shown in becomes equivalent for .
Fig. 6, operates on the observer state values and
to generate . The controller also gener-
V. OSCILLATOR PULLING
ates and to drive the observer.
The controller structure in Fig. 6 has a critical path corre- The proposed observer-controller approach to DPLL design
sponding to the time required to perform the series of additions, can be made more robust to oscillator pulling, which occurs in
the number of which increases with . As the cascaded delay many highly integrated modern transceivers. Oscillator pulling
elements and adders are basically of FIR/IIR direct-form real- generally refers to an aggressor signal operating at a nearby fre-
ization, the equivalent transposed form can be used to reduce quency coupling with the oscillator circuit via parasitic paths.
the critical path flow to one addition between delay elements This aggressor signal could be a sinusoidal signal from another

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
NAMGOONG: OBSERVER-CONTROLLER DIGITAL PLL 637

oscillator or a data modulated signal such as from the power am- Linearizing about the estimate , the linear tran-
plifier (PA) output in a direct modulation transmitter. This paper sition matrix at time is
focuses on the oscillator pulling from a sinusoidal aggressor.
The effect of oscillator pulling on VCO (or DCO) is modeled as
in [16] and [17].
When a small sinusoidal signal (relative to oscillator output)
with frequency is injected to a VCO operating at frequency
, the excess phase in (1) can be described by the fol-
lowing differential equation (first derived by Adler [16] and al- (53)
ternatively derived by Razavi [17]):
Unlike in (17), the state transition matrix changes with
every time step. Estimation of is achieved
using (53) with the Kalman filter equations in (24)–(26) and the
(50) nonlinear prediction estimate in (52). These estimates can then
where is referred to as the “one-sided” lock range (in ra- be used to update the DCO as described earlier. In formulating
dians). The ideal PD output (i.e., no additive noise) in (13) and the nonlinear state transition equations in (52) and (53), we as-
(14) is then given by sumed exact knowledge of and . In practice,
they need to be estimated, which can be accomplished during
calibration by operating the PLL in open-loop mode. A poten-
tial calibration approach is to collect a large sample of PD output
(51) in (51) in open-loop mode then perform an FFT. The magnitude
and frequency of the largest non-dc tone are related to
where represents the phase uncertainty due to sampling offset and , respectively. To minimize the spectral leakage
and any random variations in . caused by noninteger number of sine wave cycles in the FFT
The sinusoidal term in (51) can be viewed as a DCO additive input, can be slightly adjusted and/or a windowing func-
noise centered at frequency . In a conventional PLL, tion can be applied.
the effect of the injected sinusoidal noise is suppressed if the In the presence of transport delay and assuming a deadbeat
loop filter bandwidth is sufficiently wide compared to . system, the SVF operates on the predicted state value, i.e.,
Increasing the loop bandwidth to mitigate oscillator pulling is
not always possible, since the loop may no longer be stable. (54)
Even if it were stable, the loop may be too wide to adequately at-
tenuate the TDC noise, greatly degrading the output phase noise where is a vector of zeros. The -step prediction is given by
performance. Unlike the conventional loop filter, however, the
proposed loop filter can be designed to suppress the injected si-
nusoidal noise while maintaining low phase noise. (55)
In the proposed observer-controller loop filter, the Kalman
filter as described earlier cannot be used, since the sine operation A. Implementation Structure
makes the difference equation in (51) nonlinear. Instead, the ex-
tended Kalman filter (EKF) is employed to estimate the excess To determine the observer structure, (52) is expanded then
phase. EKF operates by linearizing the nonlinear state transition rearranged to obtain
function around the current state estimate then employing stan-
dard linear Kalman filter equations on the linearized transition
matrices.
The nonlinear state transition estimate used in EKF is repre-
sented by

(56)

(57)

where represents the estimate of the sinusoidal phase term

(52) due to the injected tone, i.e.,

where (58)

The observer structure of (56)–(58) is shown in Fig. 7. Com-

pared to the observer structure in Fig. 5, the phase uncertainty
due to the injected tone (i.e., ) is also estimated. Based on

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
638 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

Fig. 7. Observer structure to suppress oscillator pulling.

, the phase of the injected tone is computed and used to im-

prove the PD output estimate for the next cycle (i.e., ).
The operation can be achieved using a lookup table.
The controller structure is determined by substituting (55)
into (54) to obtain
Fig. 8. Controller structure to suppress oscillator pulling.

update occurring at the reference clock frequency. When com-

paring the performance of the proposed and conventional DPLL,
the same transport delay is assumed.
In Fig. 9, steady-state jitter is plotted as a function of
transport delay cycles for both the conventional and proposed
(59)
loop filters. Typical values of and are as-
sumed. Analytically derived of the conventional loop filter
and is the same as (46). The controller structure to sup- in (11) and the proposed observer-controller approach given in
press oscillator pulling is shown in Fig. 8. The difference com- (35) are also shown. A close agreement with simulation and
pared to the controller structure in Fig. 6 is the presence an addi- analysis is observed. The steady-state output phase noise vari-
tional branch at the top of Fig. 8, which computes the last term ance is lower for the observer-controller loop filter compared
of (59). This branch uses from the observer to precompen- to the conventional loop filter. As the transport delay increases,
sate the DCO so that the injected tone is removed at the DPLL both approaches suffer from increased jitter, although the con-
output. ventional approach appears slightly more sensitive.
To better understand the effect of the two additive noise
sources on the overall performance, steady-state jitter is
VI. SIMULATION RESULTS
plotted in Fig. 10 as a function of DCO noise assuming
The performance of the proposed observer-controller-based and . In both loops, increases linearly
loop filter is compared with the conventional loop filter. with . As is reduced (i.e., ), of the two
Throughout the simulations, the open-loop gain of the con- approaches are approximately the same. This is because the
ventional loop filter is set so that the damping factor ratio conventional loop filter is most effective when , so
is 0.7 and the phase margin is 45 . When determining the that a narrow loop bandwidth can be used to minimize jitter
steady-state jitter , the loop bandwidth of the conventional .
loop filter is determined in the following manner. Starting with Fig. 11 is similar to Fig. 10 except that steady-state jitter
the maximum loop bandwidth for a given , as shown in Fig. 3, is plotted as a function of TDC noise assuming
the loop bandwidth is reduced until jitter is minimized. and . At low values, the difference between the two
Hence, the jitter results reported for the conventional loop loop filters widens. This occurs because as becomes compa-
filter represent the lowest achievable jitter while maintaining a rable to , the conventional loop filter bandwidth cannot be in-
damping factor ratio of 0.7 and phase margin of 45 . creased beyond the maximum bandwidth required for stability.
The time-domain simulations of the proposed and conven- As TDC noise increases, the jitter in both loop filters in-
tional DPLL are performed using MATLAB. The DCO, TDC, creases but with an approximately fixed absolute difference. The
and the loop filter are all modeled in discrete time with each relative difference (in percentage) between the two loop filters,

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
NAMGOONG: OBSERVER-CONTROLLER DIGITAL PLL 639

Fig. 9. Phase noise output jitter standard deviation  versus number of trans- Fig. 11. Phase noise output jitter standard deviation  versus  . Conven-
port delays N . Conventional loop bandwidth is set to minimize  assuming tional loop bandwidth is set to minimize  assuming number of transport
 =04 : and  =4
. Jitter analysis is based on (11) and (35). delay N =5 and  =04 : . Jitter analysis is based on (11) and (35).

Fig. 12. Transient response of conventional and proposed loop filters assuming
Fig. 10. Phase noise output jitter standard deviation  versus  . Conven- N =5 , and frequency step of 10 kHz is applied at time step 10. The conven-
tional loop bandwidth is set to minimize  assuming number of transport tional loop bandwidth is set to the maximum allowed, as shown in Fig. 3.
delay N =5 and  . Jitter analysis is based on (11) and (35).=4
the state feedback is a deadbeat system, the response time to an
however, decreases with increasing TDC noise. Therefore, the input stimulus is the number of poles in the system. Since the la-
proposed loop filter is most effective compared to the conven- tency is five cycles and the plant introduces additional two poles,
tional loop filter when , while the jitter performance seven cycles are needed to converge after an input frequency
advantage diminishes as TDC noise becomes more significant step.
compared to the DCO noise. Figs. 13 and 14 plot the phase noise spectrum of the con-
In Fig. 12, the transient response of the conventional and pro- ventional and proposed loop filter, respectively, with oscillator
posed loop filters are shown when a step input frequency of 10 pulling. The two figures assume , , ,
kHz is applied at the tenth time step. Fig. 12 plots in de- , and . To best suppress
grees as a function of discrete time increments of inter- the effect of the oscillator pulling, the conventional loop band-
vals, where is assumed to be 26 MHz. As in earlier simu- width in Fig. 13 is set to the maximum allowed, as specified
lations, a transport delay of is assumed. The conven- in Fig. 3, for . When the conventional loop filter is em-
tional loop bandwidth is set at the maximum allowed as shown ployed, the phase noise spectrum has a tone at 1 MHz offset,
in Fig. 3 for . The response time of the conventional as shown in Fig. 13. By contrast, the injected tone interferer is
loop filter is roughly the inverse of the loop bandwidth, which essentially removed from phase noise spectrum of the proposed
is approximately and corresponds to a response time of observer-controller loop filter in Fig. 14. Furthermore, as de-
approximately 100 cycles. In the proposed loop filter, seven cy- rived in Section III-C, the phase noise spectrum at low frequen-
cles are needed to stabilize the loop, as shown in Fig. 12. As cies of the proposed DPLL is that of a first-order lowpass filter.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
640
Fig. 13. Phase noise spectrum of conventional loop filter with injection pulling
assuming N =5 , : , , ! =f : , and f
1 MHz . Loop bandwidth is set to the maximum.
Fig. 14. Phase noise spectrum of proposed observer-controller loop filter with
injection pulling assuming N , : , , ! =f
f 0 f = 1 MHz . Circuits Conf., Feb. 2005, pp. 316–318.
It is worth noting that since the objective function that the pro-
posed loop filter minimizes is jitter, the conventional loop filter
may achieve a lower phase noise spectral density at certain fre-
quencies. Minimizing the integrated phase noise does not nec-
essarily require that the phase noise power spectral density be
lower than that of a conventional loop filter at all frequencies.
Since the DCO and TDC in a DPLL enable the use of a fully
digital loop filter, more sophisticated control schemes can be
employed than the conventional loop filter, which is obtained
by digitizing a continuous-time loop response. We propose a
DPLL based on the observer-controller loop filter. Compared to
the conventional DPLL, the proposed approach enables a sys-
tematic design of optimal control signals that account for all
the additive noise as well as the additional poles introduced by
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010
cycle latency in the digital feedback system. As a result, the pro-
posed approach outperforms the conventional DPLL in phase
noise performance and transient response time. The difference
in phase noise performance between the two approaches be-
comes more pronounced when the DCO noise is large relative
to the TDC noise and/or the transport delay is long. With re-
cent advances in TDC design achieving picosecond resolution
[4], [18] coupled with the trend toward higher operating carrier
frequencies, TDC noise contribution should be small relative to
DCO noise in many DPLLs. The steady-state phase noise jitter
and spectrum are analytically derived. Another important ad-
vantage of the proposed observer-controller approach is that the
effect oscillator pulling, which is a common problem in modern
transceivers, can be modeled and effectively removed without
degrading the overall phase noise performance.
The implementation structure of the proposed loop filter has
been derived. The observer is basically a second-order loop filter
f = 04 =4 =01 0 = with time-varying proportional and integral gain values. Based
on the state values of the second-order loop filter, the controller
uses integrators and delay elements to generate the DCO input.
The structure of the two loop filters become equivalent only for
the case of no transport delay (i.e., ). In the presence of
oscillator pulling, an additional branch is added in both the ob-
server and controller to estimate then precompensate the DCO
for the phase uncertainty introduced by the injected tone. Com-
pared to the conventional loop filter, the proposed observer-con-
troller loop filter is modestly higher in complexity while pro-
viding significant performance improvements in phase noise,
transient response time, and robustness to oscillator pulling.
REFERENCES
[1] I.-C. Hwang, S.-H. Song, and S.-W. Kim, “A digitally controlled
phase-locked loop with a digital phase-frequency detector for fast ac-
quisition,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1574–1681,
Oct. 2001.
[2] J. Lin and B. Haroun et al., “A PVT tolerant 0.18 MHz to 600 MHz
self-calibrated digital PLL in 90 nm CMOS process,” in Proc. IEEE
Int. Solid-State Circuits Conf., Feb. 2004, pp. 488–541.
[3] R. B. Staszewski and J. Wallberg et al., “All-digital PLL and GSM/
: , and =5 =04 =4 =01 EDGE transmitter in 90 nm CMOS,” in Proc. IEEE Int. Solid-State
[4] V. Kratyuk, P. Hanumolu, K. Ok, U.-K. Moon, and K. Mayaram, “A
digital PLL with a stochastic time-to-digital converter,” IEEE Trans.
Circuits Syst. I, Reg Papers, to appear, to be published.
[5] B. Razavi, “Design of monolithic phase-locked loops and clock re-
covery circuits: A tutorial,” in Monolithic Phase-Locked Loops and
Clock Recovery Circuits: Theory and Design. Piscataway, NJ: IEEE
Press, 1996.
[6] F. M. Gardner, Phaselock Techniques. New York: Wiley, 1979.
[7] A. Demir, A. Mehrotra, and J. Roychowdhury, “Phase noise in oscil-
lators: A unifying theory and numerical methods for characterization,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 47, no. 5, pp. 655–674,
May 2000.
[8] A. Mehrotra, “Noise analysis of phase-locked loops,” IEEE Trans. Cir-
VII. CONCLUSION cuits Syst. I, Reg. Papers, vol. 49, no. 9, pp. 1309–1316, Sep. 2002.
[9] N. Da Dalt, “Noise analysis of phase-locked loops jitter transfer and
jitter generation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55,
no. 1, pp. 3663–3675, Dec. 2008.
[10] P. V. Hanumolu, G.-Y. Wei, U.-K. Moon, and K. Mayaram, “Digi-
tally-enhanced phase-locking circuits,” in Proc. IEEE Custom Integr.
Circuits Conf., 2007, pp. 361–368.
[11] R. B. Staszewski and P. Balsara, All-Digital Frequency Synthesizer in
Deep Submicron CMOS. New York: Wiley, 2006.
[12] J. Bergmans, “Effect of loop delay on phase margin of first-order and
second-order control loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 52, no. 10, pp. 621–625, Oct. 2005.
NAMGOONG: OBSERVER-CONTROLLER DIGITAL PLL 641

[13] R. E. Best, Phase Locked Loops, Theory, Design and Applications. Won Namgoong (SM’08) received the B.S. degree
New York: McGraw-Hill, 1984. in electrical engineering and computer science from
[14] Applied Optimal Estimation, A. Gelb, Ed. Cambridge, MA: MIT the University of California at Berkeley, in 1993, and
Press, 1974. the M.S. and Ph.D degrees in electrical engineering
[15] L. Rabiner and B. Gold, Theory and Application of Digital Signal Pro- from Stanford University, Stanford, CA, in 1995 and
cessing. Englewood Cliffs, NJ: Prentice-Hall, 1975. 1999, respectively.
[16] R. Adler, “A study of locking phenomena in oscillators,” IEEE Proc., He is currently an Associate Professor in the
vol. 61, no. 10, pp. 1380–1385, Oct. 1973. Electrical Engineering Department, the University
[17] B. Razavi, “A study of injection locking and pulling in oscillators,” of Texas at Dallas. Previously, he was with the
IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 1994. University of Southern California and Atheros Com-
[18] M. Lee and A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to- munications. His current research interests include
digital converter in 90 nm CMOS that amplifies a time residue,” IEEE signal processing systems and RF/analog circuits.
J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. Dr. Namgoong has received the National Science Foundation (NSF) Faculty
CAREER Award in 2002.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:43 UTC from IE Xplore. Restricon aply.