Front End: -

Front End mostly deals with RTL Design, ASIC(SOC/IP) Verification,

Synthesis, Timing analysis profiles of VLSI.
In case of RTL design, you need to have good knowledge of HDL and Coding on
VHDL, Verilog and C. Now most recently System Verilog has also been used as
a standard for HDL. Moreover you will get a good understanding on the
specification of a chip or IC and industry related protocols.
In case of ASIC Verification profiles, similar to RTL design you need to be well
versed with the coding and HDVL like System Verilog and methodologies like
UVM/OVM.
But the difference of ASIC Verification with RTL design is that as a verification
engineer you mostly deals with catching of bugs, creation of testbench to debug
the RTL block and also to create coverage reports.
Backend: -
If we look at the ASIC flow starting from Specification, Functional Simulation,
Synthesis, Timing Analysis is consumed in Front End and then Floor Planning,
Placement, Routing, ATPG insertion, Back annotation, DFT, SPEF analysis are
consumed for Backend.
Now to have knowledge on all the aspects of ASIC flow mentioned above for
Backend you need to well equipped with the concepts of CMOS, Analog
Circuits, Scripting knowledge for automation, memory characterisation, SRAM,
DRAM memories, Complete Hands on Tools for layout, physical design.

Front end Design in VLSI generally requires understanding of the Design

specification and its implementation using RTL coding and also some role
includes RTL integration, Perform Timing analysis and synthesis, Running Lint
and use cases of CDC.
To perform all the above-mentioned activities following skills are useful in Front
end Design
STEP 1: -
 Be thorough with your electronics basics providing more focus
to Digital Circuits. Try to focus more
on Combinational and Sequential Circuits and study in depth and solve
more problems. After that move on to FSM and solve problems more
on Sequence Detector. You can solve more problems of FSM from the
book of Charles’s Roth.
 Next you can move on to Advance Digital Design where you need to
focus on STA and the topics you need to focus on Setup and Hold time,
Slack, Slew, clock skew, Metastability, Noise margin, Glitch, Jitter,
Propagation Delay, ECO.
 After your Digital got over you need to go through some of the
Basic CMOS fundamentals. Since you are aiming for Front end
studying in-depth of CMOS is not required. Study the Stick diagrams,
formation of different gates through NMOS and PMOS, DRC and LVS
checks, Electromigration, formation of chip.

STEP 2: -
 Complete understanding of the ASIC and the FPGA flow.
 Good Coding knowledge on VHDL and Verilog. (Study both of them
first and later you can focus more on Verilog)
 Knowledge on System Verilog considering only
it's Synthesizable Constructs.
 Study the concepts of DPI and PLI.
 Linux Knowledge.

STEP3: -
 Study some Communication and Interface Protocols like AXI, AHB,
APB, I2C and SPI.
 All the related Concepts of FIFO providing focus on both Synchronous
and Asynchronous FIFO.
 Clock Domain Crossing and Related use of Synchronizers.
 Knowledge on Lint and use of related Tools.

Additional Skills: -
 Knowledge on DFT(Basic)
 Knowledge on Scripting language like PERL.