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Design and DC Analysis of Sram 6T Cell
Design and DC Analysis of Sram 6T Cell
INTERNSHIP REPORT
Submitted By
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INDIAN INSTITUTE OF TECHNOLOGY BOMBAY, INDIA
CERTIFICATE
This is to certify that Ms. Nisha Joshi has successfully completed her Internship at IIT
Bombay, on Design and DC Analysis of SRAM 6T Cell, from 20th May-20th July.
IIT Bombay
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Date: Prof. Sachin Ptakar
ACKNOWLEDGEMENT
I would like to thank Professor Sachin B. Patkar, Professor Jayanta Mukherji and Rewati
Raman Raut for their reviews and invaluable comments and suggestions for the clarity of
this report. I would like to thank the VLSI Lab staff Marshnil, Vineeth, Ani Xavier,
Pallavi and Rajesh for helping me out with the Cadence 6.1 Tool issue and also for giving
me few designing tip. I would also like to thank HPC lab colleagues for giving me ideas
and helping me with my work.
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CONTENTS
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I. Introduction to Memory:
1. Primary Storage:
Primary storage (or main memory or internal memory), often referred to simply as
memory, is the only one directly accessible to the CPU. The CPU continuously
reads instructions stored there and executes them as required. Any data actively
operated on is also stored there in uniform manner.
2. Secondary Storage:
Secondary storage (or external memory) differs from primary storage in that it is
not directly accessible by the CPU. The computer usually uses its input/output
channels to access secondary storage and transfers the desired data using
intermediate area in primary storage. Secondary storage does not lose the data
when the device is powered down—it is non-volatile. Per unit, it is typically also
two orders of magnitude less expensive than primary storage. Consequently,
modern computer systems typically have two orders of magnitude more
secondary storage than primary storage and data is kept for a longer time there.
3. Tertiary Storage:
Tertiary storage or tertiary memory provides a third level of storage. Typically it
involves a robotic mechanism which will mount (insert) and dismount removable
mass storage media into a storage device according to the system's demands; this
data is often copied to secondary storage before use.
4. Offline Storage:
Off-line storage is used to transfer information, since the detached medium can be
easily physically transported. Additionally, in case a disaster, for example a fire,
destroys the original data, a medium in a remote location will probably be
unaffected, enabling disaster recovery. Off-line storage increases general
information security.
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Figure1. Types of Computer data storage
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II. Classification of CMOS Memories:
CMOS MEMORIES
NON VOLATILE
VOLATILE
1) Volatile memories:
These are memories that require power to maintain the stored information. Random-
access memory (RAM) is a form of computer data storage. It takes the form of
integrated circuits that allow stored data to be accessed in any order. "Random" refers
to the idea that any piece of data can be returned in a constant time, regardless of its
physical location and whether or not it is related to the previous piece of data.
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Non-volatile memory, NVM or non-volatile storage, is computer memory that can
retain the stored information even when not powered. Examples of non-volatile
memory include read-only memory, flash memory and most types of magnetic
computer storage devices.
a) Read Only Memory (ROM): Is a class of storage which is fabricated with desired
data permanently fixed in it, thus it cannot be modified.
Computers store most commonly used instructions and data in faster but smaller memory
called cache. Cache is usually built out of SRAM on the same chip as the processor. If
the processor requests data that is available in the cache, it is returned quickly. This is
called cache hit. Otherwise, the processor retrieves the data from main memory (DRAM).
This is called cache miss.
The performance analysis i.e. the miss rate, the hit rate and average memory access time
(AMAT) where AMAT is the average time a processor must wait for memory per load or
store instruction.
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III. Static Random Access Memory (SRAM)
Random access memories which can retain their data content as long as electric power is
supplied to the memory device, and do not need any rewrite or refresh operation, are
called static random access memories.
The following elements are required to build a SRAM,
Row Decoder & Column Decoder: The operation of the SRAM starts with the
detection of an address change in the address register, and the decoders select a
single memory cell.
6T bit cell Array: is used as it has fixed cell size and easy to design as a logic
circuit. It consists of 6 CMOS transistor which performs read and write operation.
Sense Amplifier: main function is to sense or detect stored data from a read
selected memory cell.
Control Circuit: to access the bit cells the read/write circuitry is implemented to
control the data being read or written. This is achieved by control circuitry which
consists of tristate buffers.
1. Row Decoder:
SRAM adopts a multi-divided memory cell array structure to achieve high speed
word decoding and reduce column power dissipation. The multi-stage decoder circuit
technique is adopted as it has advantage over the one-stage decoder in reducing the
number transistors and fan-in. For column decoders, which select the desired bit pairs
out of the set of the sets of bit pairs in the selected row a typical dynamic and gate
could be used.
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Figure 3.2 Static CMOS AND Gate
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Figure 3.4 Decoders
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1 0 1 1 1 D23
1 1 0 0 0 D24
1 1 0 0 1 D25
1 1 0 1 0 D26
1 1 0 1 1 D27
1 1 1 0 0 D28
1 1 1 0 1 D29
1 1 1 1 0 D30
1 1 1 1 1 D31
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3. Sense Amplifier:
Sense amplifiers, in association with memory cells, are key elements in defining the
performance and environmental tolerance of CMOS memories. In an integrated
memory circuit sensing means the detection and determination of the data content of
a selected memory cell.
CMOS memories are required to increase speed, improve capacity and maintain low
power dissipation. These objectives are somewhat conflicting when it comes to
memory sense amplifier design. With increased memory capacity, usually comes an
increased bit-line parasitic capacitance. This increased bit line capacitance in turn
slows down voltage sensing and makes bit line voltage swings expensive.
The main function of sense amplifier is to sense or detect stored data from a read
selected memory cell. The memory cell being read produces a current Idata that
removes some charge (dQ) stored on the pre-charged bit lines. Since bit lines are very
long and are shared by other similar cells, the parasitic resistance Rbl and capacitance
Cbl are large. Thus the resulting bit line voltage swing (dVbl) caused by removal of
dQ from the bit line is very small dVbl=dQ/Cbl. Sense amplifiers are used to translate
this small voltage signal to a full signal that can be further used by digital logic.
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Digital analysis of Positive Feedback Voltage Sense Amplifier:
The positive feedback amplifier has 2 data nodes Vin/out1 and Vin/out2 and 3 control
nodes SANen, SAPen and PRE. The data nodes act as input and output to the sense
amplifier and its operation is as follows:
Due to its positive feedback this voltage sensing amplifier achieves a very high
differential gain. This high gain minimizes sensing time by being able to sense small
voltage swings on the bit line.
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Figure3.8 Read/Write Control Circuit
5. Tristate buffers:
Tristate buffers are the buffers which are used to control the read and write
operations. The write enable and output enable signals are generated through these
buffers.
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IV. Detailed analysis of 6T Cell Read Operation
The figure given below shows a typical static memory cell. The circuit consists of a
flipflop comprising two cross-coupled inverters and two access transistors Q5 and Q6.
Prior to initiating a read operation, the bit lines are precharged to Vdd. The read
operation is initiated by enabling the word line and connecting bit lines, BL and BLB
to the internal nodes of the cell.
Assume that the cell is storing a 1. In this case Q will be at Vdd and Qbar will be at
0 V. When the word line is selected and access transistors are turned Q5 and Q6 are
turned on.
From the above given figure, we see that current flows from Bbar line through Q5.
This current charges CQbar. Equilibrium is reached when CQbar is charged to VQbar
at which I1 equals I5. To provide a non destructive read operation, the following
design constraints are to be taken care of:
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1. VQbar should be less than Vtn of the next inverter i.e. in the figure it should be
less than Vtn of Q3. Vtn is the threshold voltage of individual NMOS and is
process dependent.
2. a). Aspect ratio of pass transistor for read 1 is given below
b). The aspect ratio for read 0 is same as above except for the fact that the access
transistors are different i.e. ratio if Q6/Q2 = Q5/Q1.
3. In read 1 operation, VBL is maintained at precharge voltage and VBLB is
discharged to ∆V.
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V. Analog Analysis Of 6T Cell Read
For economic reasons, minimizing the die area becomes important in memory design as
the basic storage cell gets repeated over and over again. The circuit consists of latch
and pass-transistor switches. Depending on the preserved state of the inverters, data is
stored in cell. To access the cell, we need switches which are connected between cell
and bit line, which is controlled by read/write circuitry.
Design Strategy:
The most important and basic requirement for efficient 6T cell design is the aspect ratio
of the transistors which is calculated depending on the following requirements:
The data read operation should not destroy stored information in SRAM cell.
The latch should allow modification of stored information in write operation.
From the above figure we see that the value initially stored is 0. Output Enable (OE) is
turned on and the word line is activated. The voltage then developed between BL and
BLbar with VBbar lower than VB when the stored value is 0 which is given by V21.
RESULTS:
VBL=747.7 mV and VBLB=913.7mV, Vtn =0.677 (process defined)
Step1: VQbar = 606.1mV, we see that is VQbar is less than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38-747.7mV=0.6323V, we see that ∆V<= Vtn
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Step3: Aspect Ratio (W/L) m26/ (W/L) m4 = 5
b) Sense Amplifier:
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c) Pre-charge Circuit
i) Before clock, WL and OE is activated
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d) Control Circuit:
The aspect ratio of all the transistors used in this design is tabulated in the table shown
below:
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2) DC ANALYSIS OF READ ONE:
a) 6T Cell:
From the above figure we see that the value initially stored is 1. Output Enable (OE) is
turned on and the word line is activated. The voltage then developed between BL and
BLbar with VB higher than VBbar when the stored value is 1 as given by V21.
RESULTS:
VB=1.208V and VBbar=827mV Vtn= 0.6777 (process dependant)
Step1: VQbar = 468.6mV, we see that is VQbar is less than Vtn.
Step2: ∆V= VBLB (pre) –VBLB (new) = 1.38-827mV=0.553V, ∆V<=Vtn
Step3: Aspect Ratio (W/L) m25/ (W/L) m0 = 730
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b) Sense Amplifier:
c) Pre-charge Circuit:
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d) Control Circuit:
The aspect ratio of all the transistors used in this design is tabulated in the table shown
below
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VI. Detailed Analysis Of Write Operation
Write Operation:
The figure given below is the circuit diagram of a basic 6T cell. We wish to write a
zero, the objective now is to pull down the node Q (as VQ= Vdd and VQbar= 0V) and
node Qbar up and have the voltages of at least one of these two nodes pass.
For read operation, the upper bound ensured that VQbar should not rise above Vtn.
But our write zero operation, will be accomplished by pulling node Q down in order
to initiate the regenerative action of the latch. The following figure illustrates the
write circuitry during write zero operation.
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From the figure we see that initially VQ is at Vdd. When transistor Q6 is turned ON,
I6 quickly discharges CQ and VQ begins to fall. The important requirements for write
operation to be completed are as follows:
1. VQ should be below Vtn of Q1 for read zero and vice-versa.
2. The aspect ratio of access and P transistor is as follows; where µn/µp is process
dependent quantity.
… General form
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VII. Analog Analysis Of 6T Cell Write
a) 6T CELL :
From the above figure we see that the value stored is 1. Write Enable (WE) are turned
on and the word line is activated. The voltage then developed between BL and BLB
with VBL higher than VBLB when the value to be written is 1 as given by V21.
RESULTS:
VBL=1.001V and VBLB=836.6mV, Vtn= 0.6777 (process dependant)
Step1: VQ = 1 V, we see that is VQ is more than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38-1.001V=0.379V
Step3: Aspect Ratio (W/L) m26/ (W/L) m5 = 10
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Figure current in access transistor during write 1
b) Sense Amplifier:
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c) Pre-charge Circuit:
d) Control Circuit:
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The aspect ratio of all the transistors used in this design is tabulated in the table
shown below:
a) 6T Cell:
From the above figure we see that the value stored is 0. Write Enable (WE) are turned
on and the word line is activated. The voltage then developed between BL and BLB
with VBL lower than VBLB when the value to be written is 0.
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RESULTS:
VBL=218.1mV and VBLB=927.8mV, Vtn= 0.6777 (process dependant)
Step1: VQ = 592.7m V, we see that is VQ is less than Vtn.
Step2: ∆V= VBL (pre) –VBL (new) = 1.38- 218.1mV=1.1619V
Step3: Aspect Ratio (W/L) m26/ (W/L) m5 = 10
b) Sense Amplifier:
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c) Precharge Circuit:
d) Control Circuit:
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The aspect ratio of all the transistors used in this design is tabulated in the table
shown below
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VIII. Problems to be solved
a. Full voltage Swing has to be provided by the sense amplifier during read/write
operations especially in read operations where the zero and one is not being
completely read.
b. Transient analysis of individual operation.
c. Area optimization of pre-charge and 6T cell has to be done as W/L ratio is too
large.
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IX. How to use Cadence
What is cadence?
Cadence is an electronic design automation (EDA) software and engineering
services company.
How to open cadence?
Cadence can be opened from any operating system. From windows it can be
opened on Xmanager.
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After giving the icfb& command, the following window opens up
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As the library window opens up, Namedo not need process information
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The figure shown below is the Virtuoso Schematic Editor which opens when we
make a new library and cell view.
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How to draw the schematic on Virtuoso Window?
LibraryBrowse the window below opens up. Select the component you want to
use.
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The figures given below shows how to use wire, instance properties, move, copy,
delete, pin names, wire names.
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Once the schematic is complete, you do check and save and no errors should be
there on the CIW window.
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How to do the simulation?
Once the design is checked and saved with no errors, we have to perform the
simulation. That can be achieved by clicking on LaunchADE L. it would look
like the following two window as shown in the figure.
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Then we have to set the model libraries by selecting Setup model libraries as
shown in the figure given below.
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As the model library setup window opens as shown in the figure given below,
click on the grey tab to browse the libraries to be added.
The browser window opens up to choose the model file as shown in the figure
given below.
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Once the model libraries are setup, we can choose the analyses we want to run by
clicking on Analyses.
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We choose the type of analyses whether it is transient or dc or ac.
Once the analyses are chosen we can plot the outputs by selecting the Outputto
be plottedSelect on Schematic. The parameters to be plotted are shown in the
figure given below
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Once all these things are taken care of then we can simulate it by clicking on
Netlist and Run
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The CIW window showing that simulation is completed successfully.
Once the simulation is successful, the outputs to be plotted are displayed. To read
the output in more detail, few steps have to be followed. The figure given below
is the merged graph of the outputs to be plotted.
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To read in detail click on AxisStrips
The graph will show individual readings of each output. To read the value on a
particular point on graph, click on MarkerPlaceTrace Marker as shown
below.
The point at which you place the marker will show the x-axis and y-axis reading
at that particular point.
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X. References
[1] Sedra/ Smith, Microelectronic Circuit, chapter 15, 6th edition
[2] Wai-Kai-Chen, Memory, Microprocessor an ASIC, 2003
[3] Tegze P. Haraszti, CMOS Memory Circuits, Kluwer Publication, 2002
[4] David Money Harris & Sarah L. Harris, Digital Design and Computer
Architecture
[5] Mohammed Sharifkhani, Design and Analysis of low power Sram, thesis report,
Waterloo University, Canada
[6] Prof. Etienna Sicard and Asst Prof. Sonia Delmas Bendhia, INSA Electronic
Engineering School of Toulouse, France, Advanced CMOS Cell Design
[7] Randall L. Geiger, Phillip E. Allen and Noel R. Strider, VLSI Design Techniques
for Analog and Digital Circuits
[8] R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS Circuit Design, Layout
and Simulation
[9] Neil Weste, CMOS VLSI Design: A Circuit and System Perspective, International
Edition
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