UNIVERSITY OF GONDAR

INSTITUTE OF TECHNOLOGY
Department of Electrical and Computer Engineering
COURSE NAME: DIGITAL LOGIC DESIGN
COURSE CODE: ECEG3141
COURSE INSTRUCTOR: AMARE WORKU
CONTACT INFORMATION:
EMAIL: AMAREWORKU2154@GMAIL.COM
CONSULTATION HOURS:
FRIDAY: FROM 8:00-10:00
 7.3 counter

 Synchronous counters

 Asynchronous counters

 Up/down counters

 Design of synchronous counters

 Cont.….

 Counters are important digital electronic circuits.

 They are Sequential logic circuits because timing is obviously important and they need a
memory characteristic.
 Digital counters have the following important characteristics,
 Maximum number of count
 Up-Down Count
 Asynchronous or Synchronous Operation
 Free-Running or Self-Stopping
 asynchronous and synchronous

• Counter are classified into two:-

 asynchronous

 synchronous
• Asynchronous counter are commonly referred to as ripple counter because the effect of the
input clock pulse is first “felt” by first flip-flop (FF0).
• Cannot get to the second flip-flop (FF1) immediately because of the propagation delay through
FF0.
• So the effect of an input clock pulse “ripples” through the counter, taking some time, due to
propagation delays, to reach the last flip-flop.
 Only the first FF receive clock pulse from the source ( clock genarator), others FFs receive
clock pulse from either Q or Q’ of prior FF
 two-bit asynchronous binary counter

Both flip-flop are connected to toggle condition

and initially assumed to be reset.
three-bit asynchronous binary counter
Cont.……
four-bit asynchronous binary counter
Cont.……….
 Asynchronous
Decade
Counter
 Module 10
 Uses four flip-flop
 Counts only BCD coded number
 Example

Solution
Cont.………….
 Synchronous binary Counter

 The term Synchronous refers to events that have a fixed time relationship with each
other AND receive clock pulse from a common source.
2-bit synchronous binary counter.
 The arrangement is different from that of the asynchronous flip- flop.
 assume initially reset state of both flip-flop,
 In clock one Q0= 1 and Q1=0 which is the binary state is one
 In clock two Q0=0 and Q1=1 which the binary state of two
 In clock three Q1=1 and Q0= 1which is the binary state three.
 In clock four Q1=0 nad Q0= 0which is recycling to the first state.
Cont.……
2-bit synchronous binary counter.
four-bit synchronous binary counter.
Up/down synchronous counter
From the table
Q0 is toggle for both up and down function
So J0=K0=1
Q1 change state in up counting when Q0 is 1 and in down counting when Q0 is 0
There for J1=K1=Q0*UP+ Q0’*DOWN
Q2change in up sequence when Q1=Q0=1 and IN DOWN sequence when Q0=Q1=0
J2=K2=Q1.Q0.UP +Q1’.Q2’.DOWN
 The UP/DOWN control input is LOW for down and HIGH for up.
Example
The timing diagram is converted to the table form
 Synchronous Counter Design

• Several methods are available that follow arbitrary sequence.

• Here we will learn one common method using JK flip-Flops.
• In synchronous counters all the FF’s are clocked at the same time.
 Cont.………
1: draw the state diagram
State diagram shows the progression of states through which the counter advances when it is clocked.
The following diagram is an example of 3 bit Gary counter.
 Cont.……
2: determine the next stable state
Next stable state is the state that the counter goes to from its present state upon the application of clock pulse and it is
derived from state diagram. For three bit Gary code counter, its present and next state can be tabulated as follows:
 Cont.…………
3. Flip-flop transition table:
Here all possible values of J-K that cause transition of the output will be listed.
 4. Karnaugh maps:
they are used to determine the logic required for the J and K inputs of each FF in the counter.
K-map for J input and K-map for K input, the cells represent the present state in the counter.
5. Logic expressions for FF inputs
From K-map, the reduced logic expression should be derived and written. For our example, the logic
ex expression will be:
 6. Implement the counter:
 from the expressions the logic diagram of thee counter will be realized. Three bit Gray counter logic diagram will be
 as follows:
Example two
 Step 1. the state diagram is shown above

 Stapes 2.state table

Stapes 3. state transition table

4.Jand K k-map for flip-flop 1,2 and 3
 Stapes 5.

Step 6. implement the counter ckt.

 Example three

Step one: state diagram

 Step two :state diagram
 Steps three :state transition table

Steps four :k map

Step five:
Step six:
implement
the circuit
 Example four
 Design a JK synchronous counter that has the following sequence:000,001,010,011,100 and
repeat. The undesired states 101,110,111 must always go to 000 on the next clock pulse.
 Step one:Draw the state transition diagram showing all the possible states,
including those that are not part of the desired counting sequence
 STEP -2 Use the state transition diagram to set up a table
that lists all PRESENT states and their NEXT states

Present state Next state

C B A C B A
1 0 0 0 0 0 1
2 0 0 1 0 1 0
3 0 1 0 0 1 1
4 0 1 1 1 0 0
5 1 0 0 0 0 0
6 1 0 1 0 0 0
7 1 1 0 0 0 0
8 1 1 1 0 0 0
Step three: Add a column to this table for each J and K input. For each PRESENT state, indicate the level
required at each J and K input in order to produce the transition to the NEXT state.

Present state Next state

C B A C B A jC kC jB kB jA kA
1 0 0 0 0 0 1 0 X 0 X 1 X
2 0 0 1 0 1 0 0 X 1 X X 1
3 0 1 0 0 1 1 0 X X 0 1 X
4 0 1 1 1 0 0 1 X X 1 X 1
5 1 0 0 0 0 0 X 1 0 X 0 X
6 1 0 1 0 0 0 X 1 0 X X 1
7 1 1 0 0 0 0 X 1 X 1 0 X
8 1 1 1 0 0 0 X 1 X 1 X 1
STEP- 4
Design the logic expression to generate the level required at
each J and K, using K-maps.
SETP -5
Finally implement the final expressions.
 Example Four : design a JK synchronous counter that has the following sequence:
000,010,101,110 and repeat. The undesired states 001,011,100 and 111 must always go
to 000 on the next clock pulse.

 STEP -1 :State Transition Diagram

 Cont.……
 STEP- 2 : Table to list PRESENT and NEXT status
STEP- 3 : Table indicate the Level required at each J and K inputs in order to
produce the transition to the NEXT
STEP- 4 :Design the logic circuits to generate the levels
required at each J and K inputs
STEP- 5 :Simplify the SOP expression using K-maps
 Example five:
Design a JK synchronous counter that has the following sequence:000,010,101,110 and
repeat. For undesired states their NEXT states can be DON’T CARES

STEP -1 :State Transition Diagram

STEP- 2 : Table to list PRESENT and NEXT status
STEP- 3 : Table indicate the Level required at each J and K
inputs in order to produce the transition to the NEXT
STEP- 4 :Design the logic circuits to generate the levels
required at each J and K inputs
STEP- 5 :Simplify the SOP expression using K-maps
Step six : implement the ckt
 Example six :Design a mod-6 counter using J-K FFs with separate logic circuitry for each J and
K input. Construct a state diagram to determine whether the counter is self-starting or not.

 Step one: state diagram is

Cont.…….
 Counter decoding

 The output of counter is in the form of code.

 Hence, it is necessary to decode the output of decoder once the counter is designed.
 By using appropriate decoder, the output of the counter will be converted to its familiar
symbol.
 Reading assignment

 Cascading counter
 Counter application
 Digital clock
 Automobile parking control
 Parallel to serial data conversion(multiplexing)
assignment