Lecture: Counter

Digital Systems, EE-208

Dr. S.K.Vishvakarma, IIT Indore

Asynchronous Counters (UP counter)
°Ripple Counter
• When the output of a flip-flop is used as the clock input for the next flip-
flop, we call the counter a ripple counter, or asynchronous counter.

What is the clock frequency ? If the period of the waveform at C is 24 us ?

Eight clock is one cycle of C---
°n flip-flop count 2n-1 digital equivalent

°3 FF, count 8 states called Modulus (mod) 8

counter.
°4 FF, count 16 count called Modulus 16 counter.

°How many FF are required to construct a mod-128

Counter ? A mod-32?
Asynchronous Counters (Down counter)

°Previous count was from 000 to 111

°Now how to design 3 bit down counter
°Complement of A, A bar should used to drive B,
like wise, B bar should used to drive C.
°A will toggle on each negative clock
°But FF B will toggle each time A goes high. Notice
that each time A goes goes high, A bar goes low
and it is the negative transition on A that triggers B
°Solitarily, FF C triggered by B bar and so C will
toggle each time B goes high.
Asynchronous Counters (UP-Down counter)
°Control line – Count UP and Count Down with AND
and OR gate
 Decoding Gates
°A decoding gate can be connected to the outputs of a counter in
such a way that the output of the gate will be high (or low) only
when the counter contents are equal to a given state.
A=1, B=1 and C=1 to count 7

A=1, B=0 and C=1 to count 5

 Synchronous Counters (UP)
°The flip-flop delay time and possibility of glitches are overcome by the use of a
synchronous or parallel counter.
°Every flip-flop is triggered in synchronism with the clock.
°Whenever A is high, AND gate X is enabled and a clock pulse is passed through
the gate to the clock input of FF B. Thus B changes the sates with every NT at
points b,d and f.

Y is enabled and will

transmit the clock to C
when A and B are high.

FF C changes the state

At d and h

Mod-8 parallel binary counter

 Changing the counter modulus

°Counter Modulus
• Counters are said to have a “natural count” of 2n. A counter
having a modulus of 3 or 5 would be useful and such counters
are said to have a modified count.
°A MOD-3 Counter
 Decade Counters
°A MOD-5 Counter
 Decade Counters
°A MOD-10 Counter
• A 2x5 or a 5x2 will form a mod-10 counter, or a decade counter.
 Presettable Counters
°Synchronous UP Counters
 Presettable Counters
°Synchronous UP-DOWN Counters
 Counter design as a synthesis problem
°Let us try to design a modulo-
6 counter, the counting states Cn Bn An Cn+1 Bn+1 An+1 JC KC JB KB JA KA
(memory values) of which are
shown in state transition
diagram. We need three 0 0 0 0 0 1 0  0  1 
memory element or flip-flops
for this as with n flip-flop we
can get at most 2n number of
different counting states. 0 0 1 0 1 0 0  1   1

000 0 1 0 0 1 1 0   0 1 

101 001
0 1 1 1 0 0 1   1  1

010
100
1 0 0 1 0 1  0 0  1 
011
State sequence of a modulo-6 counter
1 0 1 0 0 0  1 0   1
 Counter design as a synthesis problem
°Our next objective is to get logic equation for each flip-flop input as
a function of present state of the counter.

Bn An Bn An
Cn 00 01 11 10 Cn 00 01 11 10

0 0 1 1 0 0    

1     1 0 1  

JC = An KC = An

Bn An Bn An
Cn 00 01 11 10 Cn 00 01 11 10

0 0 1   0   1 0

1 0 00
0   1    
_
JB = Cn An KB = An
Counter design as a synthesis problem
°The final step is to draw the circuit diagram from the design
equations, which is shown in previous slide.

1 JA JB B JC C
A

_ _
KB _
KA A B
1 1 KC C

CLK

Circuit diagram of modulo-6 synchronous counter

Counter with unused states
 BCD ripple counter

State Diagram of decimal BCD counter