Digital Logic Design

Ch 7

Finite state machines

note 6
Topics
 Sequential circuits
 primitive sequential elements
 combinational logic
 Models for representing sequential circuits
 finite-state machines (Moore and Mealy)
 Basic sequential circuits revisited
 shift registers
 counters
 Design procedure
 state diagrams
 state transition table
 next state functions

2 Digital Logic Design

Counters

 Sequential logic circuit that proceed through a well defined

sequence of states
 3-bit binary up-counter
 000, 001, 010, 011, 100, 101, 110, 111; and return to 000
 Decade counter
 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001; and return to
0000 (binary-coded decimal)
 Gray-code counter
 Only a single bit of the counter changes at a time to avoid circuit hazard
 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110,
1010, 1011, 1001, 1000 and repeat
 Ring counter, Johnson counter, …

3 Digital Logic Design

Ring counter

 Shift registers can also be used as a kind of primitive

counter
 Uses minimal hardware for its implementation
 Not efficient state encoding
 4-bit basic ring counter

4 Digital Logic Design

Johnson counter

 aka Möbius counter

 Requires only one
inverter more than
the basic ring counter
 Can sequence through
twice as many states

5 Digital Logic Design

Counter design procedure

 Example: 3-bit binary up-counter

 3 bits (memory cells) represent states: 000, 001, …
 At each clock, current states are transited to new ones.
 Design Step1: describe state transition diagram & truth table

6 Digital Logic Design

3-bit binary up-counter design

 Step2: design combinational logic through K-map methods

A’C+B’C+ABC’
= (AB)’C+ABC’
= (AB)C OUTA OUTB OUTC

D Q D Q D Q
CLK
A’B+AB’
= AB

"1"
A’

7 Digital Logic Design

More complex counter example
000 110
 3-bit quinary counter
 repeats 5 states in sequence
 not a binary number representation 010 101

 Step 1: derive the state transition 011

diagram
 count sequence: 000, 010, 011, 101, 110 Present State Next State
C B A C+ B+ A+
 Step 2: derive the state transition 0 0 0 0 1 0
0 0 1 – – –
table from the state transition 0 1 0 0 1 1
0 1 1 1 0 1
diagram 1 0 0 – – –
1 0 1 1 1 0
1 1 0 0 0 0
1 1 1 – – –
Note the don't care conditions that
arise from the unused state codes
8 Digital Logic Design
One way to implement the counter

 Step 3: K-maps for next state functions

C+ C B+ C A+ C
0 0 0 X 1 1 0 X 0 1 0 X

A X 1 X 1 A X 0 X 1 A X 1 X 0
B B B

Present State Next State

C+ <= AB + B’C C B A C+ B+ A+
0 0 0 0 1 0
B+ <= AB’ + A’C’ 0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 1
A+ <= BC’ 1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 1 1 0 0

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 The problem with this implementation

 Start-up states
 At power-up, a counter may be in an unused or invalid state
 Designer must guarantee that it (eventually) enters a valid state
 Ex: implementation on previous slide
If the counter is initiated at state 100 or 111, 000 110
it can never enter a valid state.
111
010 101
 Self-starting solution
100 011
 Must design a counter so that
invalid states eventually transition 001
to a valid state
 May limit exploitation of don't cares

10 Digital Logic Design

 Self-starting counters

 Re-deriving state transition table from don't care assignment

for the quinary counter
C+ C B+ C A+ C
C+ <= A
0 0 0 X 1 1 0 X 0 1 0 X
B+ <= B’ + A’C’
A X 1 X 1 A X 0 X 1 A X 1 X 0 A+ <= BC’
B B B
 Now, from any invalid state, the
counter will enter a valid state 111 001

Present State Next State

C B A C+ B+ A+ 000 110
0 0 0 0 1 0 100
0 0 1 1 1 0
0 1 0 0 1 1
0 1 1 1 0 1
1 0 0 0 1 0 010 101
1 0 1 1 1 0
1 1 0 0 0 0
1 1 1 1 0 0 011
11 Digital Logic Design
 Abstraction of state elements

 Divide circuit into combinational logic and state

 Localize the feedback loops and make it easy to break cycles
 Finite state machine (FSM)
➔ a finite set of states + a combinational logic

Inputs Outputs
Combinational
Logic

State Inputs State Outputs

Memory Cells

states
12 Digital Logic Design
 Finite state machine representations
In = 0 In = 1
 Components 001 010 111
 States: determined by possible
values in sequential memory cells
100 110
 Transitions: change of state In = 1

 Clock: controls when state can Inputs Outputs

change by controlling memory cells Combinational

Logic

 Sequential logic in a FSM 0

1
 sequences through a series of 0
states State Inputs State Outputs

Tsu
 based on sequence of values on
input signals Clock
Input
 State time is the time between
Output
related clocking events
13 Digital Logic Design
 FSM design procedure

Step 1. Define the problem

 Describe a FSM in an unambiguous manner
Step 2. Obtain an abstract representation of the FSM
 State diagram
Step 3. Perform state minimization
 Certain paths through the state machine can be eliminated
Step 4. Perform state assignment
 Symbolic states are assigned logic values.
 Good state encoding may lead to a simpler logic implementation
Step 5. Implement the FSM
 Using Boolean equations or K-maps

14 Digital Logic Design

 Problem definition

 Example: counter
 The states of the circuit stored in registers (flip-flops) represent
counter values
 Next state is a function of current state and inputs
 Outputs are the state reset, up/down
 FSM model for a counter
 Combinational logic implements the function for next state
 Outputs are directly connected to registers
reset, up/down next state
Next counter value
logic

registers

Outputs
Current counter value
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 State diagram

 Nodes for states or outputs & Arcs for inputs or outputs

 Example1: counter 000 110
 Example2: combination lock in Note 1
 5 nodes for states & outputs 010 101

 12 arcs for inputs 011

◼ 1 reset transition (from all states) to state S1
◼ 5 self-transitions
◼ 6 other transitions between states ERR
closed
not equal
& new not equal
not equal & new
& new
S1 S2 S3 OPEN
reset closed closed closed open
mux=C1 equal mux=C2 equal mux=C3 equal
& new & new & new
not new not new not new
16 Digital Logic Design
 State diagram for a sequential system

 Can any sequential system be represented with a state

diagram? OUT1 OUT2 OUT3

 Ex: shift register

IN D Q D Q D Q

CLK
Input value shown
on transition arcs
1
100 110
1 0 1 1
1

0 000 1 010 101 0 111 1

0
0 0 1 0

Output values shown 001 011

0
within state node

17 Digital Logic Design

 General state machine model

 Values stored in registers represent the state of the circuit

 Next state is a function of current state and inputs
 Outputs are
 function of current state and inputs (Mealy machine)
 function of current state only (Moore machine)
 General FSM model
 Combinational logic implements the functions for next state and
outputs output Outputs
logic
Inputs
next state Next State
logic
registers
Current State
18 Digital Logic Design
 Components of a FSM model
output Outputs
 States: S1, S2, ..., Sk logic
Inputs
next state
 Inputs: I1, I2, ..., Im logic
Next State

 Outputs: O1, O2, ..., On registers

Current State
 Transition function: Fs(Si, Ij)
 Output function: Fo(Si) or Fo(Si, Ij)

Tsu Th

Next State

State
Clock 0 1 2 3 4 5

19 Digital Logic Design

 Specifying outputs for a Moore machine

 States change over input

 Output is only a function of state
 specify in state bubble in state diagram
 Ex: sequence detector for 01/10 current next
0 reset input state state output
1 – – A
1 0 0 A B 0
B/0 D/1 0 1 A C 0
0 0 0 B B 0
0 0 1 B D 1
reset 0 0 C E 1
A/0 1 0
0 1 C C 0
1 0 0 D E 1
1
0 1 D C 0
C/0 E/1 0 0 E B 0
0 0 1 E D 1
1
20 Digital Logic Design
 Specifying outputs for a Mealy machine

 States change over input

 Output is a function of state and inputs
 specify output on transition arc between states
0/0
current next
reset input state state output
B 1 – – A 0
0/0 0 0 A B 0
reset/0 0 1 A C 0
A 0/1 1/1 0 0 B B 0
0 1 B C 1
1/0 0 0 C B 1
C 0 1 C C 0

1/0

21 Digital Logic Design

 Mealy vs. Moore machines

 Mealy machines tend to have less states

 different outputs on arcs (n2) rather than states (n)
 Mealy machines react faster to inputs
 react in the same cycle – don't need to wait for clock
 In Moore, more logic may be necessary to decode state into outputs
→ more gate delays after clock edge
 Moore machines are safer to use
 Outputs are synchronous (changing at clock edge: 1 cycle later)
 Mealy outputs are asynchronous.
◼ Input change can cause output change as soon as logic is done
◼ It may cause a problem when two machines are interconnected

22 Digital Logic Design

 Mealy vs. Moore machines
inputs
combinational
 Moore logic for
next state logic for
reg outputs outputs

state feedback

logic for
inputs outputs outputs
 Mealy combinational
logic for reg
next state

state feedback logic for

inputs outputs outputs

 Registered/Synchronous combinational
logic for reg
next state
Mealy
state feedback
23 Digital Logic Design
Registered Mealy machine

 Synchronous (or registered) Mealy machine

 registered state AND outputs
 avoids ‘glitchy’ outputs
 easy to implement in PLDs
 It is really a Moore machine with no output decoding
 outputs computed on transition to next state rather than after entering
 view outputs as expanded state vector
output Outputs
logic
Inputs
next state
logic

Current State
24 Digital Logic Design
 FSM design example: Vending machine

 Step1: problem definition

 Release item after 15 cents are deposited
 Single coin slot for dimes, nickels
 No change
 Tabulate typical input sequences
Reset
◼ 3 nickels
◼ nickel, dime
◼ dime, nickel
N
◼ 2 dimes Vending Open
Coin Machine Release
Sensor FSM Mechanism
D

Clock
25 Digital Logic Design
 Step2: abstract representation

 Draw state diagram:

R
 inputs: Nickle, Dime, Reset 9 arcs
 output: open chute
 9 states 9 nodes S0
N D
 Assumptions:
 Assume N and D asserted S1 S2
for one cycle
N D N D
 Each state has a self loop
S4 S5 S6
for N = D = 0 (no coin) S3
[open] [open] [open]
N D
S7 S8
[open] [open]

26 Digital Logic Design

 Step3: state minimization ➔ Note 7

 Reuse states whenever possible

R present inputs next output
state D N state open
0¢ 0 0 0¢ 0
0 1 5¢ 0
0¢ 1 0 10¢ 0
1 1 – –
N 5¢ 0 0 5¢ 0
0 1 10¢ 0
5¢ D 1 0 15¢ 0
1 1 – –
N 10¢ 0 0 10¢ 0
0 1 15¢ 0
D 10¢ 1 0 15¢ 0
1 1 – –
N+D 15¢ – – 15¢ 1

15¢ symbolic state table

[open]

27 Digital Logic Design

 Step4: state encoding ➔ Note 7

 Uniquely encode states

present state inputs next state output
Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 – – –
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 – – –
1 1 – – 1 1 1

28 Digital Logic Design

 Step5: Moore implementation

 Mapping to logic D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

Q1 D1 = Q1 + D + Q0 N
D1
0 0 1 1 OPEN = Q1 Q0
0 1 1 1
N
D X X 1 X
1 1 1 1
Q0
D0 Q1
0 1 1 0
1 0 1 1
N
D X X 1 X
0 1 1 1
Q0
Open Q1
0 0 1 0
0 0 1 0
N
D X X 1 X
0 0 1 0
Q0
29 Digital Logic Design
 Equivalent Mealy/Moore state diagrams
Moore machine Mealy machine
➔ outputs associated with state ➔ outputs associated with transitions

R N’ D’ + R R/0 (N’ D’ + R)/0

0¢
N’ D’ 0¢ N’ D’/0
[0]
N N/0
5¢ D/0
D N’ D’ 5¢ N’ D’/0
[0]
N N/0
10¢
D N’ D’ D/1 10¢ N’ D’/0
[0]
N+D N+D/1
15¢ R’/1
Reset’ 15¢
[1]

30 Digital Logic Design

 Mealy implementation
R/0 R/0
present state inputs next state output
Q1 Q0 D N D1 D0 open
0¢ 0 0 0 0 0 0 0
N’ D’/0
0 1 0 1 0
1 0 1 0 0
N/0
1 1 – – –
D/0 0 1 0 0 0 1 0
5¢ N’ D’/0 0 1 1 0 0
1 0 1 1 1
N/0 1 1 – – –
1 0 0 0 1 0 0
D/1 10¢ N’ D’/0 0 1 1 1 1
1 0 1 1 1
N+D/1 1 1 – – –
1 1 – – 1 1 1
15¢ R’/1
Open Q1
0 0 1 0 D0 = Q0’N + Q0N’ + Q1N + Q1D
0 0 1 1 D1 = Q1 + D + Q0N
N
D X X 1 X
OPEN = Q1Q0 + Q1N + Q1D + Q0D
0 1 1 1
Q0
31 Digital Logic Design
 Mealy implementation

D0 = Q0’N + Q0N’
+ Q1N + Q1D
D1 = Q1 + D + Q0N
OPEN = Q1Q0 + Q1N
+ Q1D + Q0D

Make sure OPEN is 0

when reset
– by adding AND gate

32 Digital Logic Design

Moore to synchronous Mealy
 OPEN = Q1Q0 creates a combinational delay after Q1 and Q0
change in Moore implementation
 This can be corrected by retiming, i.e., move flip-flops and
logic through each other to improve delay
 OPEN.d = (Q1D1+ D •+ Q0N)(Q0'N
D0 + Q0N' + Q1N + Q1D)
= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D
 Implementation now looks like a synchronous Mealy machine
 It is common for programmable devices to have FF at end of logic

33 Digital Logic Design

 D0 Q1
0 1 1 0 Q1
Mealy to synchronous Mealy 1
X
0 1 1
X 1 X
N
D1
0 0 1 1
0 1 1 1
D N
0 1 1 1 X X 1 X
D
Q1 Q0 1 1 1 1
Open.d
0 0 1 0 Q0
0 0 1 1 Open.d Q1
N
D X X 1 X 0 0 1 0
0 1 1 1 0 0 1 1
N
Q0 D 1 0 1 1
0 1 1 1
Q0

OPEN.d = Q1Q0 + Q1N + Q1D + Q0D

OPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)

= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N‘D
34 Digital Logic Design
 Mealy and Moore examples

 Recognize A,B = 0,1 A

out
 Mealy or Moore? B

A Moore with 2 state bits and next
out
D Q states are defined only by inputs
B
clock A
Q D Q out

Q
Synch. Mealy w/o state
or equivalently… B
D Q
Moore where next states are only clock 10
11
dependent on inputs as shown below Q
S10
10
[0] S11
01 01
10 10 11 [0]
00,
S0 S1 S00
10, 01 S01 01
[0] [1] [0]
11 00,10,11 01
[1]
00 01
00

35 Digital Logic Design

 Mealy and Moore examples
Mealy: Next State = Inputs
 Recognize A,B = 1,0 then 0,1 Output = Fo(Inputs, Cur. State)
 Mealy or Moore? out

A
D Q

B
S1101 D Q
… [0] … Q
clock
11
SQ3Q2Q1Q0
S0110 out
[1]
A Q3 Q1
01 D Q D Q
… 10
Q Q
S1001 … Q2 Q0 Moore: 16 states generated
[0] B
D Q D Q
by 4 state bits
Q Q
clock
36 Digital Logic Design
 Example: reduce-1-string-by-1

 Remove one 1 from every string of 1s on the input

Moore Mealy

zero
[0] 0/0
zero
1 0
0 one1 0/0 1/0
[0]
0 one1
1
1 1/1
two1s
[1]

37 Digital Logic Design

 Summary

 Models for representing sequential circuits

 abstraction of sequential elements
 finite state machines and their state diagrams
 inputs/outputs
 Mealy, Moore, and synchronous Mealy machines
 Finite state machine design procedure
 deriving state diagram
 deriving state transition table
 determining next state and output functions
 implementing combinational logic

38 Digital Logic Design