Integrated Circuit Fabrication

Assumed Background
Prerequisites: Physics of Semiconductor Physics

In this course fundamental physical and chemical

processes will be used to describe and model a range
of fabrication processes making up the various silicon
integrated circuit technologies.
It is assumed that students have a
quantitative understanding of the basic device physics
and construction of diodes, bipolar junction and field-
effect transistors
1. Semester: Monsoon 2020/2021

2. Course Code and Credit: ECE 522 [4 (3+0)]

3. Nama: Integrated Circuit Fabrication

4. Time Table:
Day Time Place
From To
Monday 16:00 17:30 Online
Thursday 16:00 17:30 Online

5. Name of Lecturer: Prof. Sudhanshu Shekhar Jamuar

6. Office No.: B304 Academic Block

7. Telephone No.: 9304812392

8. E-mail: sudhanshu@iiitd.ac.in
 Topic
Remark
Week

Reading Assignment,
Introduction – IC Production Cycle, Semiconductor Group assignment
1 materials and their properties (Simulation I)

Material Properties – Crystal structure, crystal

2 axis and plane, crystal defect and defect Reading Assignment,
Group assignment
electronic properties (Simulation I)

Crystal Growth – Elementary material, growth Group assignment

3 from liquid and doping in liquid state (Simulation I), Quiz 2

Oxidation - Themal oxidation, Dielectric deposition

4 and polysilicon deposition Group assignment
(Simulation I), Quiz 3

Film deposion and metalization Group assignment 2

5
 Topic
Week Remark

Photolithography – Optical lithography, Pattern

generation and mask making printing problems, Group assignment
6 2, Quiz 4
New techniques in lithography

Etching – Wet chemical etching, dry etching, Group assignment 2,

7 microelectromechanical systems Quiz 5
Mid Term Test

Diffusion – Basic diffussion process, extrinsic

8 diffussion, diffussion related process, Silicon Group assignment 2,
and GaAs impurity behaviour Quiz 6

Ion Implantation – Basic of ion implantation,

range of implanted ions, implant damage and Quiz 7
9
annealing, implantation related process
Process Integration – IC fabrication process,
mask layout, , isolation techniques, Passive
10
components
 Topic Remark
Week

Bipolar technology, MOS and CMOS

11 TechnologyTechnology

Bipolar technology, MOS and CMOS

Quiz 8
12 TechnologyTechnology (cont.)

BiCMOS, MESFET technology

13

Assembly and packaging, Future trends in IC

14 fabrication
 Text Books
• Gary S. May and S. M. Sze – Fundamentals of Semiconductor
Fabrication, John Wiley Int Edition, 2004
• S. M. Sze – Semiconductor Devices Physics and Technology, John
Wiley, 2nd Ed. 2002
• S. K. Ghandi – VLSI Fabrication principles, John Wiley, 1993
• W. Runyan and K. Bean, Semiconductor Integrated Circuit
Processing Technology, Addison Wesley, 1990

Evaluation

Quiz - 20%
Project - 20%
Midterm – 20%
Final Exam. - 40%
 Overview of the course

• This course is basically about silicon chip fabrication,

the technologies used to manufacture ICs.
• Special emphasis on computer simulation tools has
helped to understand these processes and as design
tools.
• These simulation tools are more sophisticated in some
technology areas than in others, but in all areas they
have made tremendous progress in recent years.
• Progress due to:
 Feature size reduction - 0.7X/3 years (Moore’s
Law).
 Increasing chip size - » 16% per year.
 “Creativity” in implementing functions.
The first transistor
The first metal-oxide-semiconductor field-effect transistor
The first monolithic integrated circuit
1960s and early 1990s integrated circuits
The first microprocessor
 Overview of Silicon Technology

Course Goals
It is expected that upon successful
completion of the course, students will:

• acquire an overview of modern semiconductor technology

• have quantitative understanding of various fabrication processes
• understand various aspects of device physics applicable to sub-
micron devices
• know the state of development and trends of present day
semiconductor industry
• be able to process and device simulation tools to study various
fabrication processes and device characteristics
 Overview of Silicon Technology

The main aim of silicon wafer fabrication technology

(usually referred to as the front end processing) is to
selectively dope regions of the silicon wafer with different
impurity atoms to form the necessary n- and p-type regions
of transistors and diodes (and in some instances as
resistors and conductors) and to grow insulating layers for
gate dielectric of mosfets and for isolation of devices and
conducting wires
 Overview of Silicon Technology

In this course we will only be dealing with “silicon technology”

which is the most mature of the semiconductor technologies.
Some of the processes described will be applicable to the
fabrication of other semiconductor devices such as gallium
arsenide devices.
The level of integration of silicon technology as measured in
terms of number of devices per integrated circuit has more or
less been doubling every two years since the beginning of the
technology in the early 1960’s.
 Overview of Silicon Technology

This comes about in two ways – size reduction of the

individual devices and increase in the chip or dice size.
As an indication of size reduction, it is interesting to
note that feature size was measured in mils (1/1000
inch, 1 mil = 25 mm) up to early 1970’s, whereas now all
features are measured in mm’s (1 mm = 10-6 m or 10-4
cm).
 Overview of Silicon Technology

To accommodate this change, the size of the silicon

wafers on which the integrated circuits are fabricated
have also increased by a very significant factor – from
the 2 and 3 in diameter wafers to the 8 in(200 mm) and
12 in (300 mm) diameter wafers.
The latest catch phrase in semiconductor technology (as
well as in other material science) is nanotechnology –
usually referring to GaAs devices based on quantum
mechanical phenomena. These devices have feature
size (such as film thickness, line width etc) measured in
nanometres or 10-9 metres.
 Overview of Semiconductor Technology

Year Semiconductor Device Author(s )/Inventor( s)

1874 Metal-semiconductor contact Braun
1907 Light emitting diode Round
Bardeen, Brattain,
1947 Bipolar transistor
and Shockley
1949 p-n junction Shockley
1952 Thyristor Ebers
Chapin, Fuller, and
1954 Solar cell
Pearson
1957 Hetero-junction bipolar transistor Kroemer
1958 Tunnel diode Esaki
1960 MOSFET Kahng and Atalla
1962 Laser Hall et al
Kroemer, Alferov and
1963 Hetero-structure laser
Kazarinov
1963 Transferred-electron diode Cunn
 Overview of Semiconductor Technology

Year Semiconductor Device Author(s )/Inventor( s)

Johnston, DeLoach,
1965 IMPATT diode
and Cohen
1966 MESFET Mead
Nonvolatile semiconductor
1967 Kahng and Sze
memory
1970 Charge-coupled device Boyle and Smith
Chang, Esaki, and
1974 Resonant tunneling diode
Tsu
1980 MODFET Mimura et aI.
1994 Room-temp. single-electron Yano et aI.
memory cell
2001 20 nm MOSFET Chau
Overview of Semiconductor Technology

Year Technology Author(s)/Inventor

1918 Czochralski crystal growth Czochralski
1925 Bridgman crystal growth Bridgman
1952 III-V compounds Welker
1952 Diffusion pfann
1957 Lithographic photoresist Andrus
1957 Oxide masking Frosch and Derrick
Sheftal,
1957 Epitaxial CVD growth Kokorish,and
Krasilov
1958 Ion implantation Shockley
1959 Hybrid integrated circuit Kilby
1959 Monolithic integrated circuit Noyce
1960 Planar process Hoemi
Overview of Semiconductor Technology

Year Technology Author(s)/Inventor

1963 CMOS Wanlass and Sah
1967 DRAM Dennard
Kerwin, Klein, and
1969 Polysilicon self-aligned gate
Sarace
Manasevit and
1969 MOCVD
Simpson
Irving, Lemons, and
1971 Dry etching
Bobos
1971 Molecular beam epitaxy Cho
1971 Microprocessor (4004) Hoff et al.
Rung, Momose, and
1982 Trench isolation
Nagakubo
Chemical mechanical
1989 Davari et al.
polishing
1993 Copper interconnect Paraszczak et al.
 Overview of Silicon Technology

Overview
The process sequence of two typical fabrication technologies
– the bipolar technology and the n-mos technology. These
may not be the latest technology, they however give a good
indication of the fabrication processes and the way these are
linked together to form what is referred to as the “technology”.

Basic n-MOS technology

Basic bipolar technology
Basic Bipolar technology
Basic Bipolar technology
Basic n-MOS technology
Basic n-MOS technology
 Overview of Silicon Technology

What are shown on previous

diagrams cover only the so
called front-end processing
- fabrication steps that go towards
forming the devices and
inter-connections between these
devices to produce the
functioning IC's. The end result
are wafers each containing a
regular array of the same IC
chip or die. The wafer then has
to be tested and the chips diced
up and the good chips mounted
and wire-bonded in different
types of IC package and tested
again before being shipped out.
 Overview of Silicon Technology

Ever since the invention of integrated circuit, the smallest

feature size has been reducing every year. Currently
(2002) the smallest feature size is about 0.13 micron. At
the same time the number transistors per chip is
increasing due to feature size reduction and increase in
chip area. Classic example is the case of memory chips:
Gordon Moore of Intel in early 1970s found that:
“density” (bits per chip) growing at the rate of four times
in 3 to 4 years - often referred to as Moore’s Law. In
subsequent years, the pace slowed down a bit, data
density has doubled approximately every 18 months –
current definition of Moore’s Law.
Overview of Silicon Technology
Exponential increase of dynamic random access memory
density versus year
Exponential increase of microprocessor computational power versus year.
Growth curves for different technology drivers.
 IC Production Process

Processing Steps
 Crystal Preparation
 Masking
 Photolithography
 Etching
 Deposition
 Diffusion and Ion Implantation
 Metallisation
A bare n-type Si wafer

An oxidized Si wafer
by dry or wet oxidation

Application of resist

Resist exposure
through the mask
 Wafer after p-n junction formed
development after diffusion or ion
implantation process

Wafer after Final result after

SiO2 removal complete lithographic
process

Wafer after A p-n junction after

metallization complete processes
 Introduction to Fabrication

S.S. Jamuar

8/21/2020 Introduction to CMOS 51

 CMOS TECHNOLOGY

8/21/2020 Introduction to CMOS 52

8/21/2020 Introduction to CMOS 53
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