Sandhya Dholani

E-mail : sandhya.dholani@gmail.com Phone : +91-9638036061

Address : 4 , Satgurupark - 2 , Bunglow Area ,, Kubernagar, Ahmedabad, Gujarat -
382345

Summary of Key Skills

Good knowledge of verification concepts.
Hands on experience on NC-Sim, VCS.
Hands on experience on ASIC Design tools for Synthesis( Synopsys DC), STA (Synopsys PT), and Tetramax.
Good debugging skills.
Considerable experience and knowledge of using System Verilog and OVM/UVM for VIP development.
Well versed with scripting languages like Tcl.
Considerable experience of using Verilog HDL for RTL generation and developing self checking test benches.

Technical Skills
Programming : C, C++
HDL: Verilog, VHDL
HVL: System Verilog, OVM/UVM
Scripting: Tcl
Tools: FPGA Design: Xilinx ISE, Xilinx ISim
ASIC Design: Synopsys Design Compiler, PrimeTime, IC-Compiler, Tetramax
Simulation: Modelsim, VCS,NC-Sim.
OS: Windows, Linux (Command-line)
Protocols: AMBA AHB, USB 3.0

Work experience
PerfectVIPs May 2013 — Present
Designation : ASIC Verification Engineer
Projects:
VIP Development of USB 3.0

Roles and Responsibilities:

Responsible for developing directed and random test cases in System Verilog/OVM and running regressions.
Responsible for writing functional coverage and ensure coverage goals are met.
Participated in understanding and debugging client issues pertaining to integration of VIP with DUT.

eInfochips Training and Research December 2012 — March 2013

Academy
Designation : Technical Associate

Coordinated the training programme for a team of interns belonging to the ASIC division

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Qualifications
Diploma in Digital Design from Brain Support Integration Technologies( Ahmedabad : June 2011 to March
2012)
Projects:

1. Design of SPI Bus Controller

Tools used : Xilinx ISE
Responsible for design of SPI Master through finite state machine followed by RTL coding
using Verilog HDL and functional simulation.
1. Xilinx Virtex 6 FPGA based Design of H.264 Video Encoder(Baseline Profile)
Tools used: Xilinx ISE, Xilinx ISim, ModelSim, Matlab Image Processing Toolbox
Team Size: 3
Responsible for carrying out architecture design of DCT , Quantizer and Intra Prediction
blocks and subsequent RTL generation using Verilog HDL .

Completed Modular Training Program on Semi Custom ASIC Flow from M.S. Ramaiah School of Advanced
Studies(Bangalore: July 2012 to October 2012)
Projects:
Design and Implementation of AMBA AHB Arbiter
Tools used: Synopsys DC, Synopsys PT, Tetramax
Responsible for architecture design of arbiter , RTL generation and synthesis (Synopsys DC), static
Timing Analysis ( Synopsys PT) and carried out DFT using Tetramax.

Education
Bachelor of Engineering July 2008 — July 2012
Vishwakarma Govt. Engineering college

Successfully accomplished graduation with CGPA 8.23 on a 10 point scale

Secured a national scholarship granted by the Ministry of Human Resource Development
Successfully cleared GATE 2011 with 95.27 percentile.

H.S.C June 2006 — May 2008

Infocity Junior Science College

Successfully completed higher school with 87.60 %

Interests
Playing Guitar , Table Tennis.

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