VLSI Test and Testability

BIST pattern generation Techniques

Seminar #2

BITS Pilani Aishwarya Venketraj

Department of Electrical and Electronics
Pilani|Dubai|Goa|Hyderabad
BITS Pilani Dubai Campus

Aishwarya Venketraj 1
Outline
1. Introduction
1.1 Typical BIST Architecture
1.2 4 - Parameters to be considered
1.3 Benefits of BIST
1.4 Issues of BIST
2. BIST Pattern Generation Techniques
2.1 Stored Patterns
2.2 Exhaustive Patterns
2.3 Pseudo Exhaustive patterns
2.4 Pseudo Random Pattern Generation

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Typical BIST Architecture

 DFT technique – Physical placing of test functions to the CUT

Components of BIST:
1. Test Pattern Generator: (seq)
• Rom + Stored Patterns
• Counter
• Linear Feedback Shift register
2. Response Analyzer : Comparator with Stored patterns  Analyze
3. Test Controller : Activates the test  several test related funcs

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4 - Parameters to be considered
1. Fault Coverage:
• Exposed by the test patterns produced by pattern generator and
detected by output response monitor.
• If input bit stream  errors computed signature matches the golden
signature CUT: fault free undesirable property called masking or
aliasing.
2. Test Set Size:
• No of test patterns produced by the test generator.
• Closely linked to fault coverage: Large test sets imply high fault
coverage.
3. Hardware Overhead:
• Extra hardware required for BIST is overhead.
• High hardware overhead is not acceptable.
4. Performance Overhead:
• Impact of BIST h/w on normal circuit performance such as
• worst-case
• critical path delays.
• More important than hardware overhead.

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Benefits of BIST
• Reduces testing and maintenance cost
• Requires simpler and less expensive ATE
• Reduces cost of ATPG
• Reduces storage and maintenance of test patterns. ƒ
• It can test many units in parallel. ƒ
• It takes shorter test application times. ƒ
• It can test at functional system speed.

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Issues of BIST
• Area Overhead: Additional area due to test controller, pattern
generator, response evaluator and testing of BIST hardware
• Pin Overhead: At least 1 additional pin is needed to activate
BIST operation
• Input MUX adds extra pin overheads
• Performance overhead: Extra path delays are added due to
BIST. ƒ
• Yield loss increases due to increased chip area. ƒ
• Design effort and time increases due to design BIST. ƒ
• The BIST hardware complexity increases when the BIST
hardware is made testable.

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BIST Pattern Generation Techniques

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Stored Patterns
• Pattern generated by
• ATPG
• Fault simulation technique
• A good test pattern set is stored in a ROM on the chip.
• When BIST is activated, test patterns are applied to the CUT
and the responses are compared with the corresponding
stored patterns.
• Although stored-pattern BIST can provide excellent fault
coverage, it has limited applicability due to its high area
overhead.

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Exhaustive Patterns

• Eliminates the test generation process Has very high fault coverage.
• Shows every state and transition works
• For n inputs it requires 2^n vectors
• Impractical for n>20

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Pseudo-Exhaustive Patterns

 Partition large circuit into fanin cones

 Backtrack from each PO to PIs influencing it
 Test fanin cones in parallel
 Reduced # tests from
n=8
2^8= 256
Pseudo Exhaustive Pattern fanin cone
(2^5)x2=64

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Pseudo-Exhaustive Patterns

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Pseudo-Exhaustive Patterns

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Random Patterns

Bottom curve represents Random Pattern Resistant Curve

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Random Patterns
Key: Random Should be unbiased patterns
Non repetitive
How to compare the response of Random Pat on the fly?
Solution !
Algorithm
Algorithmic repetitive
SA1/SA0

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Pseudo-Random Patterns
Linear Feed Back Shift Register
Most desirable random Pattern Property
Preserve Randomness and is Deterministic
Synchronous 3 FF Example
Initial
1. 111
2. 011
3. 001
4. 100
5. 010
6. 101
7. 110
8. 111

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Pseudo-Random Patterns

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Matrix Equaton of a Pseudo-Random Patterns

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Primitive Polunomial in Modular Expression

1+x^K
Where, (1+x^7)
K=(2^n)-1 Factorial :
n# inputs (1+x)(1+x+x^3)(1+x^2+x^3)
Here n=3
K=7

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Transtion Counting
Count Transitions from
#10
#01
Aliasing should be as small as possile

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Test Time

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Reduced Func Faults

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