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Memory Addressing of 8086 (CS502) PDF
Memory Addressing of 8086 (CS502) PDF
The 8086 memory address space can be viewed as a sequence of one million bytes in which
any byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit
data element. There is no constraint on byte or word address boundaries. The address space is
physically connected to a 16-bit data bus by dividing the address space into two 8-bit banks of up
to 512K bytes each.
One bank is connected to the lower half of the 16-bit data bus (D0 – D7) and contains even
address bytes. i.e., when A0 bit is low, the bank is selected. The other bank is connected to the
upper half of the data bus (D8 - D15) and contains odd address bytes. i.e., when A0 is high and
BHE (Bus High Enable) is low, the odd bank is selected. A specific byte within each bank is
selected by address lines A1-A19.
Higher Lower
Address Address
Bank Bank
(512K x 8) BHE (512K x 8) A0
ODD EVEN
Fig. 5
Data can be accessed from the memory in four different ways. They are:
8 - bit data from Lower (Even) address Bank.
8 - bit data from Higher (Odd) address Bank.
16 - bit data starting from Even Address.
16 - bit data starting from Odd Address.
8-bit data from Even address Bank
O dd B an k Even Ba n k
x + 1 x
x + 3 x + 2
x + 5 x + 4
BH E = 1 A0 = 0
D 8 -D 15 D 0 -D 7
A1 -A1 9
D 0 -D 15
1
Example: Consider loading a byte of data into CH register (higher order 8-bits of CX
register) from the memory location with an even address. The data will be accessed from the even
bank via the (D0 - D7) DATA BUS. Although this data is transferred into the 8086 over the
lower 8-bit lines, the 8086 automatically redirects the data to the higher 8-bits of its internal 16-
bit data path and hence to the CH-register. This capability allows bytes input - output transfer via
the AL register to access I/O device connected to either
the upper half of the data bus or the lower half of the 16-bit data bus.
8-bit Data from Odd Address Bank
To access memory byte from an odd address information, is transferred over the higher
half of the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is
output high to disable the lower memory bank. It is illustrated in fig. 7
O dd B ank Even Bank
x + 1 x
x + 3 x + 2
BHE =0 A0 = 1
A 1 -A 1 9
D 0 -D 7
D 8 -D 1 5
D 0 -D 1 5
Fig. 7
16-bit Data Access starting from Even - Address
x+1 x
x+3 x+2
A0 = 0
BHE =0
A1-A19 D8-D15
D0-D7
D0-D15
Fig. 8
16-bit data from an even address is accessed in a single bus cycle. Address lines A1 -
A19 select the appropriate byte within each bank. A0 low and BHE low enables both banks
simultaneously. This is illustrated in fig. 8.
2
Odd Bank Even Bank Odd Bank Even Bank
A1-A19 A1-A19
A1-A9 A1-A9
D0-D7 D0-D7
D8-D15 D8-D15
(a) First Access from Odd Address (b) Next Access from Even Address Fig. 9
During the second bus cycle, the upper byte (with the even address 0006H as in fig. 9
(b)) is accessed. During the first bus cycle, A1 - A19 address bus specifies the address and A0 as
1 and BHE is low. Therefore the even memory bank is disabled and odd memory bank is
enabled. During the second bus cycle, the address is incremented. Therefore A0 is zero and
BHE is made high. The even memory bank is enabled and the odd memory bank is disabled.
When MN/ MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be in
maximum mode. An 8288 bus controller interprets status information coded into S0, S1 and S2 to
generate bus timing and control signals compatible. DEN, DT/ R and ALE control outputs, are
now generated by the 8288 bus controller. The DEN from 8288 is inverted and given to 8286
transceiver to enable the output. The output enable of 8282 latch is grounded. As in minimum
mode the address-data lines are latched through 8282 latch. The ALE signal from the 8288 bus
controller latches the address during the T1 state of the microprocessor. The DEN signal is used to
enable the transceiver either to transmit or receive data from I/O devices and memory. The
DT/ R signal is used to transmit or receive the data as the need may be.
3
PCLK
+5V
C lo c k CLK M /IO
READY C o n tr o l
g e n e r a to r IN T A
RES RESET Bus
RD
AEN2 WR
AEN1
F /C M N /M X +5V
8086 C PU
A D 0 -A D 1 5 L a tc h
A 1 6 -A 1 9
BHE BHE
D0 - D15
8286 16
D T /R T
DEN OE
+5V
MN/MX Gnd CLK MRDC
CLK
S0 S0
Clock READY MWTC
RES S1 S1
Bus Controller
generator AMWC
S2 S2
8288
RESET IORC
DEN IOWC
DT/R AIOWC
Wait-State ALE INTA
Generator
8086 CPU
STB A0 - A19
OE
Address Bus
AD0-AD15 8282
A16-A19 Latch BHE
T
OE DATA
8286
Transceiver
4
the memory location that it wants to read. Since the latches are enabled by ALE being high, this
address information passes through the latches to their outputs. The 8086 then makes the ALE
output low. This disables the latches (8282) and holds the address information latched on the
latch outputs. The address information latched on the latch outputs can now be used to select the
desired memory or port location.
In the timing diagram, the first point at which the two (AD0 – AD15) cross represents the
time at which the 8086 has put a valid address on these lines. Two lines DO NOT indicate that
all 16 lines are going high or going low at this point. The crossed lines indicate the time at which
a valid address is on the bus.
T1 T2 T3 Twait T4
CLK
AD0-AD15
BHE
ALE
S2 -S0
M/IO
RD
READY
DT/R
DEN
WR
5
The DEN signal is used to enable bi-directional buffers on the data bus. The data enable
signal, DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data
transmit / receive signal DT/ R from the 8086 is used to specify the direction in which the buffers
are enabled. When DT/ R is asserted high, the buffers will, if enabled by DEN, transmit data
from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if enabled
by DEN, will allow data to be received from Memory or I/O ports of the 8086. DT/ R is
asserted during T1 of the machine cycle. The DEN is asserted after the 8086 finishes using the
data bus to send the lower 16 address bits.
6
Comparison of 8086 with the 8088 Microprocessor
The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most
internal functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles
the external bus the same way the 8086 does, one difference being hat the
8088 handles only 8-bits at a time. 16-bit operands are fetched or written in two
+5V S S o (H ig h )
G n d (2 )
NM I M N /M X
IN T R
C lk RD
A D 0 -A D 7 (8 )
H O L D (R G /G T 0 )
A 8 -A 1 5 (8 ) H L D A (R Q /G T 1)
A 1 6 /S 3 (4 )
A 1 9 /S 6
8088 W R (LO C K )
IO /M (S 2 )
Te s t
D T /R (S 1 )
R eady
D E N (S 0)
A L E (Q S 0 )
R e se t
IN T A (Q S 1 )
A8-A15: These pins are only address outputs on the 8088. These address lines are
latched internally and remain valid throughout a bus cycle in a manner similar to the
8085 upper address lines.
SS0 provides the S0 status information in the minimum mode. This output occurs
on pin 34 in minimum mode only. DT/ R , IO/ M and SS0 provide the complete bus
status in minimum mode. This is shown in table 5
7
1 0 0 Interrupt Acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
Table 5
BHE has no meaning on the 8088 and has been eliminated.
IO/ M has been inverted. i.e., (In 8086, this pin as IO /M)
ALE is delayed by one clock cycle in the minimum mode when entering
HALT to allow the status to be latched with ALE.
Fig 15 illustrates the 8088 microprocessor system configuration. The Address-Data lines
AD0-AD7 are connected to the 74LS373 latch. The address from the multiplexed bus is latched
into the 74LS373 when an ALE (Address latch enable) is active during T1 state of the
microprocessor. The address A0-A7 is available on the output of 74LS373 and can be used for
memory (along with A16-A19), and I/O devices. The address lines A8-A15 are not multiplexed
with data lines or status lines, hence there is no need to latch these address lines. The data bus is
connected to the 74LS245 transceiver. The 74LS245 is controlled by DT/ R and DEN to
transmit and receive and Data respectively.
Since 74LS373 and 74LS245 are also buffered chips, it is not required to add buffers to
these chips. The address lines A8-A15 need to be buffered and hence the 74LS 244 buffer is used
for these lines. The output of 74LS244 is always enabled.
OE
A 1 9 /S 6 - A 1 6 /S 3 A19 - A16
7 4 L S 37 3
ALE G
74LS
A15 - A8
244
OE
8088 OE
G A0 - A7
AD0 - AD7
7 4 L S 37 3
D T /R DEN
D0 - D7
7 4 L S 24 4
G D /R
Fig. 15
1. Compare 8086 and 8088 microprocessors. In what ways are they similar? In what ways do they differ?
2. What is the purpose of the ALE signal in an 8086 system?
3. What is the major difference between an 8086 operating in minimum mode and an 8086 operating in
maximum mode?
4. Describe the response of an 8086 when its RESET input is asserted high.
5. Why are buffers often needed on the address, data and control buses in a microprocessor system?
6. What are the function of the 8086 DT/ R and DEN signals?
7. Explain the difference between a memory read cycle and an I/O read cycle.
8
8. What are the main functions provided by the 8288 bus controller when used with the 8086/8088
maximum mode operation?
9. Explain the operation of the LOCK pin.
10. What conditions do the QS1 and QS0 pins indicate about the 8086/8088?
11. What three house keeping chores are provided by the 8284 clock generators?
12. Explain the operation of the TEST pin and the WAIT instruction.
13. What is the function of QS0 and QS1 signals?
14. With a timing diagram explain I/O read machine cycle.
15. With a timing diagram explain I /O Output-Write machine cycle with two wait states.
16. Mention an affiliation of the OSC signal in 8284?
17. What is the application of the PCLK signal?
18. Briefly describe the purpose of each of the T-states T1, T2, T3 and T4.
19. What is the purpose of the status bits S3 and S4?