A New 5–Level Voltage Source Inverter
Apparao Dekka, Ali Ramezani, Saeed Ounie, and Mehdi Narimani
Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4L8, Canada
E-mail: dapparao@ieee.org, ounies@mcmaster.ca, ramezana@mcmaster.ca, narimanm@mcmaster.ca
Abstract—This paper presents a new 5-level voltage source
inverter for medium-voltage, high-power applications. The pro-
posed topology uses a less number of active components in
comparison with classical 5-level topologies. In the proposed
inverter, the flying capacitors voltage needs to be regulated at 1/4
of the net dc-link voltage to generate a 5-level voltage waveform
at the output. In order to control the output voltage and flying
capacitors voltage, a space vector modulation (SVM) scheme
is developed. This technique utilizes the redundancy switching
states to generate a desired output voltage and regulate the flying
capacitors voltage at their nominal value, simultaneously. The
steady-state and transient performance of the proposed inverter
are verified through MATLAB simulations.
Index Terms—Flying capacitor voltage balancing, multilevel
converter, space vector modulation, voltage source inverter.
I. I NTRODUCTION
Nowadays, multilevel inverters are preferred choice for
medium-voltage, high-power applications. These inverters
generate a high-quality output voltage and current waveforms
with a smaller ripple and low dv/dt [1]. The past few years,
several multilevel inverters are developed. Among them, the
neutral-point clamped (NPC), flying capacitor (FC), and cas-
caded H-bridge (CHB) topologies are referred to as classical
inverter topologies [2]. These topologies are commercially
available in different output voltage levels for an operating
voltage of 2.3–13.8 kV.
The NPC topology is commercially available in three-
levels with an operating voltage of 2.3 kV [3]. For a higher
operating voltage, the NPC topology requires a large number
of clamping diodes to increase the output voltage levels. Also,
the NPC requires a complex control structure to achieve the
capacitor voltage balancing [4]. Similarly, the FC topology is
available in four-levels, and it requires a large number of bulky
flying capacitors to increase the operating voltage and output
voltage levels. These capacitors affect the reliability of the
converter and requires pre-charging circuits. Furthermore, the
FC topology needs to operate at a higher switching frequency
to achieve capacitor voltage balancing as well to minimize the
voltage ripple [5]. The CHB topology can reach an operating
voltage of 13.8 kV by using low-voltage semiconductor de-
vices. The CHB topology has a modular construction which
enables a high-voltage and high-power operation with a simple
control structure [6]. However, the CHB requires a phase-
shifting transformer to generate the isolate DC sources for
each H-bridge module [7].
Other improved topologies are H-bridge/NPC (HNPC), ac-
tive neutral-point clamped (ANPC), and nested neutral-point
clamped (NNPC) inverters [8]–[10]. The HNPC topology is
978-1-5386-8330-9/19/$31.00 ©2019 IEEE
realized by using two classical three-level NPC legs connected
in the form of H-bridge. So that, the HNPC topology can
generate a five-level voltage waveform at the output. However,
HNPC topology requires a phase-shifting transformer similar
to CHB topology to generate isolated dc-sources. Hence, the
HNPC topology is available only for an operating voltage of
6.6 kV [11].
ANPC topology is designed by replacing the clamping
diodes with active devices in a three-level NPC. These active
devices help to balance the loss distribution among the devices
[12]. However, ANPC topology requires a higher number of
semiconductor devices. The three-level ANPC topology can
reach an operating voltage of 2.3–3.3kV. The ANPC topology
is extended to five-level operation by combining the three-level
ANPC and half-bridge FC module [13]. In five-level ANPC
topology, some of the devices have to block a voltage of Vdc /2,
and some have to rated for Vdc /4. Hence, to realize a five-level
ANPC topology, the devices with a rating of Vdc /4 should
be connected in series to replace the Vdc /2 rating devices or
use the devices with different voltage ratings. Hence, the five-
level topology is not an attractive solution for medium-voltage
applications [14].
Another interesting topology for medium-voltage applica-
tions is the nested neutral-point clamped (NNPC) converter
[15]. NNPC topology is designed for four-level operation and
requires a fewer number of semiconductor conductor devices
compared with the existing four-level inverters [16]. In the case
of five-level operation, the NNPC topology requires a series
connection of devices, which is not preferable in industry.
Furthermore, the five-level NNPC has less redundancy, and
it is difficult to achieve voltage balancing in the complete
operating range by using classical control methods [17].
In this paper, a new five-level voltage source inverter is
proposed for medium-voltage, high-power applications. Unlike
CHB and HNPC, the proposed topology does not require iso-
lated dc-sources; hence the need of phase-shifting transformer
can be eliminated as shown in Table I. Furthermore, the new
topology is suitable for back-to-back configuration due to a
single dc-bus. The proposed topology requires zero clamping
diodes compared with 5L-NPC and 5L-NNPC inverters, 25%
lesser flying capacitors compared with 5L-FC, and 16.67%
lesser active devices compared with a 5L-ANPC inverter as
shown in Table I. Overall, the lower number of components
can reduce the size, weight, cost and improve the reliability
of the inverter. To control the inverter output voltage and
flying capacitor voltages, a simple switching technique based
on space vector modulation (SVM) scheme is presented. The
2511
 Sa1 Sb1 Sc1

iCa1 Sa2 iCb1 Sb2 iCc1 Sc2

Vdc vCa1 vCb1 vCc1
2
Ca1 Cb1 Cc1

Sa3 Sb3 Sc3

Sa7 Sb7 Sc7

iCa2 iCb2 iCc2
ia va ib vb ic vc
o vCa2 Ca2 a vCb2 Cb2 b vCc2 Cc2 c

Sa8 Sb8 Sc8

iCa3 iCb3 iCc3

Sa4 Sb4 Sc4
Vdc vCa3 vCb3 vCc3
2
Ca3 Cb3 Cc3

Sa5 Sb5 Sc5

Sa6 Sb6 Sc6

Figure 1. Configuration of a new 5L-VSI.

Table I
C OMPONENT C OUNT IN F IVE -L EVEL I NVERTERS The switching states of the five-level inverter are shown in
Table II. The inverter has eight switching states to generate
Topology Number of Number of Flying Isolated five-level voltage waveform at the output. The voltage levels
Switches Diodes Capacitors dc Sources 3 Vdc /4, Vdc /2, and Vdc /4 has two switching states referred
5L-NPC [4] 24 36 – – to redundant switching states. The redundant switching states
5L-FC [5] 24 – 18 – can be used to control the flying capacitor voltages. Table II
5L-CHB [18] 24 – – 6 shows the effect of redundant switching states on charging
5L-ANPC [19] 36 – 3 – and discharging of each flying capacitor for both positive and
5L-HNPC [20] 24 12 – 3 negative direction of the currents.
5L-NNPC [17] 24 6 6 – For example, the output voltage level “1” can be generated
5L-VSI 30 – 9 – by using the states “1” and “2”. For the state “1” and the
positive direction of the current, the voltage of capacitors
Cx1 and Cx2 are not affected, whereas the capacitor Cx3 is
stead-state and transient performance of the proposed topology charging. In the case of state “2” and the positive direction of
are validated through MATLAB simulations. the current, the capacitors Cx1 , Cx2 , and Cx3 are charging.
This paper is organized as follows: In Section II, the struc- Similarly, each switching state is analyzed, and their impact
ture and switching states of proposed topology are presented. on the flying capacitor voltages is presented in Table II.
The implementation of SVM scheme and voltage balancing
issues are presented in Section II. The simulation studies B. Space Vector Modulation Scheme
of the proposed topology are presented in Section III. The In this converter, the flying capacitor voltages are con-
conclusions are given in Section IV. trolled using a space vector modulation technique. This control
scheme keeps the capacitor voltages balanced and provides
II. T OPOLOGY AND M ODULATION S CHEME
a desired output voltage to the load. In this scheme, the
A. Topology space vector diagram is divided into six sectors. Each sector
The configuration of the proposed five-level inverter is contains nine triangles, which represent possible switching
shown in Fig. 1. Each phase consists of ten semiconductor state vectors. The five-level space vector diagram in αβ-frame
devices with a voltage rating of Vdc /4 and three flying is shown in Fig. 2. According to Fig. 2, each voltage reference
→
−
capacitors Cx1 , Cx2 , and Cx3 where x ∈ {a, b, c}. Each flying vector V ref can be realized by using the three adjacent
capacitor voltage is regulated at Vdc /4 so that the inverter can switching vectors to the reference vector [21], [22].
generate a five-level voltage waveform at the output terminals. If the reference vector is located in the shaded triangle as

2512
 Table II
S WITCHING S TATES OF 5L-VSI

Sx1 Sx2 Sx3 Sx4 Sx5 Sx6 Sx7 Sx8 vxo ix > 0 ix ≤ 0 Level State
1 1 0 0 0 0 1 0 Vdc vCx1 ≈,vCx2 ≈,vCx3 ≈ vCx1 ≈,vCx2 ≈,vCx3 ≈ 4 7

1 0 1 0 0 0 1 0 vCx1 ↑,vCx2 ≈,vCx3 ≈ vCx1 ↓,vCx2 ≈,vCx3 ≈ 6

3 Vdc /4 3
0 1 0 0 0 1 1 0 vCx1 ↓,vCx2 ↓,vCx3 ↓ vCx1 ↑,vCx2 ↑,vCx3 ↑ 5

1 0 0 1 0 0 0 1 vCx1 ↑,vCx2 ↑,vCx3 ≈ vCx1 ↓,vCx2 ↓,vCx3 ≈ 4

Vdc /2 2
0 0 1 0 0 1 1 0 vCx1 ≈,vCx2 ↓,vCx3 ↓ vCx1 ≈,vCx2 ↑,vCx3 ↑ 3

1 0 0 0 1 0 0 1 vCx1 ↑,vCx2 ↑,vCx3 ↑ vCx1 ↓,vCx2 ↓,vCx3 ↓ 2

Vdc /4 1
0 0 0 1 0 1 0 1 vCx1 ≈,vCx2 ≈,vCx3 ↓ vCx1 ≈,vCx2 ≈,vCx3 ↑ 1
0 0 0 0 1 1 0 1 0 vCx1 ≈,vCx2 ≈,vCx3 ≈ vCx1 ≈,vCx2 ≈,vCx3 ≈ 0 0

Sector II 440
According to Table II, each switching vector can be realized
by using redundancy switching states, and these switching
441
330
430 states are employed to achieve the flying capacitor voltage
Sector III Sector I balancing in the proposed 5L-VSI. In order to consider the
442 V2 431 420 voltage balancing of the flying capacitors in the described
331 320
443
220 Vref space vector modulation, a cost function J is defined as
332
221
321 421
310
410 follows:
444 210
110 V3 V1
333 J = Ja + Jb + Jc
222 422 411
433 400
111 3  2
000
322 311 300 X X 1 Vdc (2)
211 200
= Cxi vCxi −
100
i=1
2 4
x=a,b,c

where, i ∈ {1, 2, 3} represent the flying capacitors, Ja , Jb ,

Sector VI and Jc represent the cost function of phase-a, -b, and -c,
Sector IV
respectively, Cxi represents the flying capacitor size, and vCxi
represents the flying capacitor voltage.
The cost function J is minimized such that the flying
capacitor voltages are regulated at their nominal value as
Sector V
3  
d Jx X Vdc d vCxi
Figure 2. Space vector diagram of a 5L-VSI. = Cxi vCxi − ≤0 (3)
dt i=1
4 dt
where,
3
− −
→ → →
−
 
X Vdc
shown in Fig. 2, then the switching vectors V 1 , V 2 , and V 3 Cxi vCxi − i ≤0 (4)
are used to realize the reference vector. These three switching i=1
4 Cxi
vectors are applied for a time duration of t1 , t2 , and t3 over a where, iCxi represents the flying capacitor Cxi current.
sampling interval (Ts ), respectively. According to the volt-sec The average capacitor current remain constant over one
balance, the reference vector is given by [23]: sampling period (Ts ). Hence, the equation (4) becomes,
→
− →
− →
− →
−
V ref Ts = V 1 t1 + V 2 t2 + V 3 t3 X3 
Vdc

T s = t1 + t2 + t3 Cxi vCxi − i ≤0 (5)
(1) 4 Cxi
−
→ π i=1
jθ
V ref = |Vref | e , 0 ≤ θ ≤ ,
3 where, iCxi represents the average current flowing through
where Ts represents the sampling time, and t1 , t2 , and t3 are flying capacitor Cxi .
→ −
− → The objective of the control scheme is to minimize J to
the switching times of the switching vectors V 1 , V 2 , and
→
− achieve a flying capacitor voltage balancing. This goal can be
V 3 , respectively, Vref is the reference vector, and θ is the
reference vector position. realized by selecting the switching state among all possible

2513
 Table III 10.0 kV
S YSTEM PARAMETERS vab
5.0 kV

Variable Description Simulation 0.0

S Load Apparent power (kVA) 2500 -5.0 kV
vLL Load L-L RMS voltage (V) 7200 -10.0 kV
i Load RMS current (A) 200.49 (i)
0.2 kA
f Frequency (Hz) 60
Vdc Net DC-bus voltage (V) 11800 0.1 kA ia ib ic
Cxi Flying capacitor (µF) 2200 0.0
VCxi DC-bus capacitor voltage (V) 2950
-0.1 kA
fs Sampling frequency (Hz) 1000
-0.2 kA
(ii)
4.0 kV
3.0 kV
redundancy switching combinations that result in the least vCa1 vCa2 vCa3
value for the cost function. 2.0 kV
1.0 kV
III. S IMULATION S TUDY 0.0 kV
0.0 0.028 (iii) 0.056 time (sec) 0.084
The performance of the proposed five-level inverter is
validated under different operating conditions using MAT- Figure 3. Steady-state performance: (i) output line-to-line voltage, (ii) three-
LAB/Simulink. The parameters of the five-level inverter are phase output currents, and (iii) phase-a flying capacitor voltages.
shown in Table III. The inverter is designed for power capacity
of 2.5 MVA. The net dc-bus voltage is around 11.8 kV ma = 0.55 ma = 0.9
to generate a line-to-line ac voltage of 7.2 kV at an unity 12.0 kV
vab
modulation index. Each flying capacitor voltage is rated to 6.0 kV
2.95 kV. The five-level inverter is controlled by using SVM
0.0
scheme with a sampling frequency of 1 kHz.
-6.0 kV
A. Steady-state Performance -12.0 kV
(i)
0.3 kA
The steady-state performance of the proposed five-level ia ib ic
inverter is validated at ma = 0.7 and power factor 0.7 (lagging). 0.15 kA

The inverter generates a 7-level line-to-line voltage waveform 0.0

at the load terminals as shown in Fig. 3(i). The load draws a -0.15 kA
current magnitude of 180 A as shown in Fig. 3(ii), whereas -0.3 kA
the proposed switching technique regulates the flying capacitor (ii)
4.0 kV
voltages at their nominal value of 2.95 kV as shown in Fig.
3.0 kV
3(iii). vCa1 vCa2 vCa3
2.0 kV
B. Transient Performance 1.0 kV
The transient performance of the proposed five-level inverter 0.0 kV
0.0 0.033 (iii) 0.067 time (sec) 0.1
is validated with a sudden step-change in the modulation index
as shown in Fig. 4. Initially, the inverter is controlled at a Figure 4. Transient performance: (i) output line-to-line voltage, (ii) three-
modulation index of 0.55, and power factor 0.7 (lagging). phase output currents, and (iii) phase-a flying capacitor voltages.
Under this condition, the inverter generates a five-level output
voltage with a voltage step of 2.95 kV as shown in Fig. 4(i).
The inverter generates balanced and sinusoidal currents with C. Effectiveness of Voltage Balancing Approach
a peak value of 120 A at the load terminals as shown in
Fig. 4(ii). The flying capacitor voltages are regulated at their The effectiveness of flying capacitor voltage balancing is
nominal value of 2.95 kV as shown in Fig. 4(iii). validated by disabling the balancing approach for a short
At t = 0.045 s, the modulation index is changed from 0.55 duration of time, as shown in Fig. 5. Initially, the inverter
to 0.9, whereas the power factor remains constant. The output is controlled by voltage balancing algorithm, and it maintains
voltage levels are increased from 7 to 9 levels corresponding each flying capacitor voltage at its rated value of 2.95 kV. At
to the modulation index. The output current magnitude is in- t = 0.05 s, the balancing approach is disabled, and the flying
creased to 220 A proportional to the change in the modulation capacitor voltages are diverging from their nominal values. At
index. As can be seen from Fig. 4, the proposed switching t = 0.08s, the balancing is enabled. The algorithm is able to
technique effectively regulates the flying capacitor voltages at bring back the flying capacitor voltages to their nominal value
their rated values of 2.95 kV during the step-change. as shown in Fig. 5.

2514
 With Without
With Control
Control Control
6.0 kV
4.5 kV
3.0 kV
vCa1 vCa3 vCa2
1.5 kV
0.0 kV
0.0 0.06 0.12 time (sec) 0.18
Figure 5. Transient performance of capacitor voltage balancing approach.
IV. C ONCLUSION
In this paper, a new five-level multilevel inverter is proposed
for medium-voltage, high-power applications. The proposed
topology does not require isolated dc source unlike CHB and
HNPC topologies and requires fewer components compared
with the existing 5-level multilevel inverters. To control the
inverter output voltage and flying capacitor voltages, a simple
switching state selection algorithm based on the SVM scheme
is developed. The steady-state and transient performance of
the proposed inverter and switching state selection algorithms
are validated through MATLAB simulations. The results show
that flying capacitor voltages well regulated at their nominal
value irrespective of the operating condition, and therefore the
inverter generates multilevel stepped waveforms and sinusoidal
currents at the load terminals.
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