A Doubly Grounded Boost Seven Level PV Inverter

Topology with Model Predictive Controller

Mokhtar Aly1 , Eltaib Abdeen D. Ibrahim2 , Fernanda Carnielutti3 , Margarita Norambuena4
Samir Kouro5,6 , José Rodriguez1
1 Facultad de Ingenierı́a, Arquitectura y Diseño, Universidad San Sebastián, Bellavista 7, Santiago 8420524, Chile
2 Electrical Engineering Department, High Institute for engineering and technology in Sohag, Sohag, Egypt
3 Federal University of Santa Maria (UFSM), Santa Maria, Brazil
4 Electrical Engineering department, Universidad Tecnica Federico Santa Maria, Valparaiso 2390123, Chile
5 Department of Electronic Engineering, Universidad Tecnica Federico Santa Maria, Valparaiso 2390123, Chile
6 Department of Electronics Engineering, Universidad de seville, 41092 Seville, Spain

mokhtar.aly@uss.cl, eabdeen@ieee.org, fernanda.carnielutti@gmail.com, margarita.norambuena@usm.cl

samir.kouro@ieee.org, jose.rodriguezp@uss.cl

Abstract—Leakage currents reduction and elimination process
is important task during the development of photovoltaic (PV)
inverters and their associated control and modulation schemes.
Compared to existing solutions, doubly grounded (DG) PV
inverters represent vital solution for total cancellation of existing
common mode voltages and hence their resulting leakage current
components. This paper presents a new DG PV inverter topology
with boosting capability of PV voltages, outputting seven level
output voltage, having continuous current from PV side, and
possessing reduced component count and elements. Moreover, a
model predictive controller (MPC) is proposed for the proposed
topology for controlling multiple objectives without the need for
cascaded linear control loops, and with achieving fast tracking
and response. The simulation results are provided in this paper
with performance comparisons with existing DG PV inverter
topologies in literature. The results also prove superior output
and control characteristics of the proposed topology with reduced
control complexity and reduced component counts.
Index Terms—Doubly grounded inverter, leakage currents,
model predictive controller, multilevel inverters, photovoltaic
(PV) inverters.
I. I NTRODUCTION
Recent global orientation to fasten the energy transition for
new renewable and environmentally friendly energy sources
has become clear in different sectors [1], [2]. Among existing
different renewable sources, photovoltaic (PV) based genera-
tion has found wide installations and future plans in different
capacities [3], [4]. However, leakage current in PV systems
represents one of the most important challenges in the develop-
ment of PV grid connected systems [5], [6]. Some codes state
limiting values for leakage currents for their grid connections.
There are several methods for reducing/eliminating leakage
currents in the literature [7]–[9]. Some proposals include
the development of modulation and/or control methods for
controlling common mode voltages (CMVs), which is the main
cause of leakage currents. Another method is the development
of particular topologies, such as H5, H6, iH5, etc [10], [11].
Another solution is through developing topologies with
connecting the negative terminal of PV side with neutral ter-
minal of grid side, namely doubly grounded (DG) PV inverter
[12]–[14]. The DG connection leads to total elimination of
CMVs in these topologies, and hence total elimination of
the resulting leakage currents [15], [16]. In comparison with
other leakage current reduction/elimination techniques, the
DG connection eliminates the source (CMVs) of producing
the leakage currents. Hence, they are more effective solution
with theoretical zero leakage currents. Several DG solutions
have been provided in literature, including the buck, boost,
and buck-boost topologies [17]–[19]. In addition, single and
multiple stages based DG inverters have been presented in
literature. In which, integrated two stages boost DG inverters
have proven superior performance with reduced components
count. While, they are capable of generating multilevel output
voltage [20].
In this regards, a new seven level DG PV inverter topology
is proposed in this paper with model predictive controller. The
main advantages of the new proposed topology include: seven
level output voltage waveform, continuous PV side current,
zero leakage currents, and reduced number of elements and
components. The proposed topology integrates the boosting
stage and control inside the inverter itself. This, in turn, leads
to having reduced component count in the proposed topology.
Moreover, a model predictive controller (MPC) is proposed
for controlling the proposed topology. The proposed MPC
can simultaneously control capacitor voltages at their desired
references, injecting high quality AC current to the grid side,
and controlling PV side DC current based on desired MPPT
operating point. The proposed MPC method can control the
switching signals of the topology for boosting the PV voltage
in addition to achieving the multilevel inverter operation in the
same time.
The remaining of the paper is organized as following: Sec-
 TABLE I: The pulses of switches and corresponding voltage at
S6 S8
S1 S4 Lf Rf inverter output for proposed topology (1 represents ON-state
L1
ic1 C1 ic2 C2 io case, and 0 represents OFF-state case).
VDC
S7 vC1 S9 vC2
CDC PV S5
S2 vgrid Outputs Switches Signals
No.
Level S1 S2 S3 S4 S5 S6 S7 S8 S9
1 VDC 0 1 1 1 0 0 1 0 1
2 0 1 1 0 1 0 0 1 0 1
S3 3 VDC 1 0 1 1 0 0 1 0 1
4 0 0 1 1 0 1 0 1 0 1
Fig. 1: Control block diagram of the proposed FCS-MPC 5 -VDC 1 1 0 0 1 0 1 0 1
6 0 1 0 1 0 1 0 1 0 1
algorithm. 7 2VDC /3 0 1 1 1 0 1 0 0 1
8 -VDC /3 1 1 0 1 0 1 0 0 1
9 2VDC /3 1 0 1 1 0 1 0 0 1
10 -VDC /3 0 1 1 0 1 1 0 0 1
tion II presents the new proposed topology and its operation. 11 -VDC /3 1 0 1 0 1 1 0 0 1
The proposed MPC representation is provided in Section III. 12 2VDC /3 0 1 1 1 0 0 1 1 0
Section IV presents obtained simulation results of the proposed 13 -VDC /3 1 1 0 1 0 0 1 1 0
14 2VDC /3 1 0 1 1 0 0 1 1 0
seven level topology and MPC method. The paper conclusions 15 -VDC /3 0 1 1 0 1 1 0 0 1
are provided in Section V. 16 -VDC /3 1 0 1 0 1 1 0 0 1
17 VDC /3 0 1 1 1 0 1 0 1 0
II. T HE N EW P ROPOSED S EVEN L EVEL DG T OPOLOGY 18 -2VDC /3 1 1 0 1 0 1 0 1 0
19 VDC /3 1 0 1 1 0 1 0 1 0
Fig. 1 shows the circuit diagram of the new proposed seven 20 -2VDC /3 0 1 1 0 1 1 0 1 0
level DG PV inverter topology. The topology includes a single 21 -2VDC /3 1 0 1 0 1 1 0 1 0
inductor, three DC capacitors, and nine power semiconductor
switches. The topology is capable of generating seven different
voltage levels (VDC , 2VDC /3, VDC /3, 0, -VDC /3, -2VDC /3, - reactive power Qref is adjusted based on grid requirements.
VDC ). The topology is capable of boosting PV voltage through The reference AC current of grid side io,ref is represented as:
using the inductor L1 and the capacitor CDC , which works
as DC link capacitor. The two switched capacitors (C1 and Pref
C2 ) with their reference voltages (VC1 and VC2 equal to io,ref (k + 1) = 0.5Vgrid(peak) cos(θ) sin(2πfl t + θ) (1)
VDC /3), respectively are responsible for generating the seven-
where Vgrid(peak) is grid peak voltage and θ is angle of power
level output voltage waveform. Thence, the proposed topology
factor, which is determined as:
realizes the boosting of PV voltage with generating multilevel
output waveform using a single stage power conversion. In Q
θ = tan−1 Pref
ref
(2)
addition, the inductor L1 has DC current, which is designed
to operate in continuous conduction mode for maintaining The injected current io representation of grid side L filter
continuous current for the PV side. (given by inductor Lf and resistance Rf ) is related to output
From another side, we can see that the proposed DG seven voltage of inverter vo and grid instantaneous voltage vgrid is
level inverter topology has a direct connection between the grid given as:
neutral point with the negative terminal from PV side. This, in
turn, leads to eliminating CMV components of the inverter and vo = vgrid + Rf io + Lf di
dt
o
(3)
hence leakage current components are cancelled inherently in
the proposed seven level DG inverter topology. The topology Then, we can get:
has total of 21 switching states and seven level outputs. Some
dio 1
states are redundant and hence they can be employed for dt = Lf (vo − vgrid − Rf io ) (4)
controlling capacitor voltages and inductor currents at their
Based on Euler approximation, dio /dt is determined for
reference values. The switching states for the proposed DG
sample period Ts for (k+1)th sample and io (k+1) is predicted
seven level inverter are provided in Table. I.
using:
III. P ROPOSED MPC M ETHOD
Ts Rf Ts
A MPC method is proposed for the seven level PV inverter io (k + 1) = Lf (vo (k) − vgrid (k)) + (1 − Lf )io (k)
topology as shown in Fig. 2. A PI controller is used in the outer (5)
loop to control the DC capacitor CDC at its reference value In (5), calculation of the possible 21 states in the proposed
of VDC . The MPC controller is responsible for controlling topology is made for vo in each sample period. Then, all
the injected grid AC current io , the PV side DC current possible current prediction set is obtained for the control
IDC , and the two capacitor voltages (VC1 , and VC2 ). The variables. The output voltage of proposed seven level inverter
outer loop generates the reference active power Pref , while is represented based on Table. I as follows:
 Power Inverter Stage
vo (k) = (S3 S4 − S1 S2 S5 )vDC (k) − S6 vC1 (k) − S8 vC2 (k) Grid
(6)
For controlling DC current IL , its prediction is made as PV Filter
follows: Proposed
DG Inverter
Ts
IL (k + 1) = IL (k) + Lin (Vin (k) − S1 S3 vDC (k)) (7)
VC1
Whereas its reference IL,ref value is determined by PV side VC2 2 Sj 9
MPPT algorithm as:
IL(k)
PP V
IL,ref (k + 1) = VP V (8) IL,ref (k+1) io(k)
MPC Cost Function
where, PP V and VP V denote PV maximum power and voltage, io,ref (k+1)
VC1,ref (k+1) g(k)
respectively. Moreover, capacitors voltages are predicted as:
VC2,ref (k+1)
Ts
vC1 (k + 1) = vC1 (k) + C1 (S6 io (k)) (9) VDC,ref Pgrid Ref. grid
Ts ( )2 PI current
vC2 (k + 1) = vC2 (k) + C2 (S8 io (k)) (10)
VDC calculation
Finally, the four control objectives are included in a single ( )2 Qgrid
objective function as following: MPC Stage
g(k) = λ1 (io,ref (k + 1) − io (k + 1)) Fig. 2: Control diagram of proposed predictive control scheme.
+λ2 (IL,ref (k + 1) − IL (k + 1))
(11)
+λ3 (VC1,ref (k + 1) − VC1 (k + 1))
+λ4 (VC4,ref (k + 1) − VC4 (k + 1))
A zoomed view of the tracking performance of the proposed
where λ1 , λ2 , λ3 , and λ4 represent objectives’ weighting MPC method in Fig. 5 and Fig. 6 for PV power increase,
factors of AC grid current, DC inductor current, capacitor and decrease, respectively. It can be seen that the proposed
C1 voltage, and capacitor C2 voltage, respectively. At the MPC method achieves fast tracking of control objectives. In
end of evaluating objective function, the FCS-MPC selects addition, it is capable of control multiple objectives simulta-
the best switching state that possesses the minimized cost neously. The injected AC current is sinusoidal and follows the
function. Thence, improved tracking is guaranteed using FCS- determined reference sinusoidal reference value. Additionally,
MPC algorithm by ensuring the application of best state of the the proposed topology can generate seven level voltage with
inverter. continuous PV side current. Also, the proposed controller can
IV. S IMULATION R ESULTS track the control objectives with fast response and high quality
output is obtained.
A case study has been implemented using MAT-
LAB/SIMULINK platform with: input DC voltage of 75V,
grid AC peak voltage 311V, grid filter of 3.5 mH, MPC V. C ONCLUSIONS
sampling frequency 20 kHz, and PV side inductance 4.5 mH. A new DG seven level PV inverter topology is proposed in
The obtained simulation results are shown in Fig. 3 for the this paper with MPC method. The main advantages of the
proposed seven level DG inverter and MPC method (DC proposed DG topology are: eliminating totally the leakage
current, AC current, and inverter voltage, respectively). It can currents, continuous PV side current, low number of com-
be seen that the proposed topology generates seven different ponents and passive elements, and multilevel output voltage
level, which proves the multilevel output voltage using the waveform. Additionally, MPC method is proposed in the paper
proposed topology. It can be seen that the control of DC that achieves control of multiple objectives simultaneously,
current as well as the AC current follow the supplied PV fast response, and proper tracking performance. Simulation
MPPT power reference. results and detailed mathematical modelling and operation of
Additionally, the results of the capacitor voltage tracking the new proposed topology are provided in the paper.
are shown in Fig. 4 for the DC voltage control, capacitor C1
voltage control, and capacitor C2 voltage control, respectively. VI. ACKNOWLEDGMENTS
It can be seen that the proposed controller preserves a con-
trolled DC link voltage at 400V, regardless of the changes in This work was supported by ANID, Chile FONDECYT Ini-
the injected PV power. In addition, the capacitors C1 and C2 ciacion 11230430, SERC-Chile ANID/FONDAP/1522A0006,
are kept controlled at VDC /3 as shown in the results and based AC3E (ANID/BASAL/FB0008), FONDECYT 1230250, and
on the switching table of the proposed inverter topology. ANID projects 1210208 and 1221293.
 IDC 50

0
0 0.2 0.4 0.6 0.8 1 1.2
20
io

0
-20
0 0.2 0.4 0.6 0.8 1 1.2
500
Vout

-500
0 0.2 0.4 0.6 0.8 1 1.2
Time (s)

Fig. 3: Results of proposed seven level DG inverter and MPC method (DC current, AC current, and inverter voltage,
respectively).

450
VDC

400

350
0 0.2 0.4 0.6 0.8 1 1.2
200
VC1

150

100
0 0.2 0.4 0.6 0.8 1 1.2
200
VC2

150

100
0 0.2 0.4 0.6 0.8 1 1.2
Time (s)

Fig. 4: Results of proposed seven level DG inverter and MPC method (DC voltage control, capacitor C1 voltage control, and
capacitor C2 voltage control, respectively).
 50
IDC

0
0.38 0.385 0.39 0.395 0.4 0.405 0.41 0.415 0.42
20
io

0
-20
0.38 0.385 0.39 0.395 0.4 0.405 0.41 0.415 0.42
500
Vout

-500
0.38 0.385 0.39 0.395 0.4 0.405 0.41 0.415 0.42
Time (s)
Fig. 5: Zoomed results at PV power increase.

50
IDC

0
0.78 0.785 0.79 0.795 0.8 0.805 0.81 0.815 0.82
20
io

0
-20
0.74 0.75 0.76 0.77 0.78 0.79 0.8 0.81 0.82
500
Vout

-500
0.78 0.785 0.79 0.795 0.8 0.805 0.81 0.815 0.82

Fig. 6: Zoomed results at PV power decrease.

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