Finite-States Model Predictive Control of a

Four-Level Diode-Clamped Inverter

P. Cortes(1) , J. Rodriguez(1) , S. Alepuz(2) , S. Busquets-Monge(2) , J. Bordonau(2)
(1) Depto. Electronica. Universidad Tecnica Federico Santa Maria.

Av. España, 1680, Valparaiso, Chile.

Tel:+56 32 2654761, Email: patricio.cortes@elo.utfsm.cl
(2) Dept. Electronic Engineering. Technical University of Catalonia.

Av. Diagonal 647, 08028 Barcelona, Spain.

Tel:+34 93 4016602, Email: alepuz@eupmt.es

Abstract— This paper presents a new and simple finite-
states model predictive control strategy for a four-level three-
phase diode-clamped inverter. This strategy allows for fast
load current control while keeping the balance of the dc-
link capacitor voltages. A discrete-time model of the load
and of the dc-link capacitors is used to predict the behavior
of the load current and the capacitor voltages for each
possible switching state. A cost function that considers the
load current error and the capacitor voltages error is used to
evaluate each prediction. The switching state that minimizes
the cost function is selected and applied during a whole
sampling period.
Simulation results are shown verifying the good perfor-
mance of the proposed predictive controller.
I. I NTRODUCTION
Multi-level converters are considered for medium volt-
age and high power applications, and also for other appli-
cations where high quality voltages and currents are re-
quired [1], [2]. These converters have several advantages
over the traditional converters: operation with voltages
over the switching devices rating, reduced common mode
voltages and smaller voltage changes (dv/dt). Increasing
attention on these kind of converters is reflected in a large
number of publications in the last years [3], [4].
One of the most popular multi-level topology is the
diode-clamped converter, specially the three-phase three-
level neutral point clamped converter. For the control
of these converters several modulation techniques have
been proposed. Most of this techniques are based on
Pulse Width Modulation (PWM) [5], [6] and Space Vector
Modulation [7]. Modifications of the PWM strategy has
been proposed in order to guarantee dc-link capacitor
voltage balance in a four-level diode clamped converter
under any operating condition [8].
Predictive control is a very wide class of controllers that
have found rather recent application in power converters,
a classification of them is proposed in [9]. A well known
type of predictive controller is the deadbeat controller,
which has been applied for current control in three-
phase inverters [10], [11], [12], rectifiers [13], [14], active
filters[15], [16], and uninterruptible power supplies (UPS)
[17].
Model Predictive Control (MPC) is a different approach
that considers a model of the system in order to predict
the future behavior of the system over a horizon in time.
A cost function represents the desired behavior of the
system. Finite-States MPC is a simple way to use MPC
for the control of power converters taking advantage of the
discrete nature of the power converters. These are systems
with a finite number of states given by the possible combi-
nations of the state of the switching devices. By this way,
the behavior of the system is predicted for each possible
state. Then, each prediction is evaluated using the cost
function and the state that minimizes it is selected. This
approach has been successfully applied for the current
control in a three-phase inverter [18], a three-level neutral
point clamped inverter [19] and a matrix converter [20],
power control in an active front end rectifier [21], [22],
and torque and flux control of an induction machine [23].
This strategy has been also applied for current control in
a four-level three-phase diode-clamped inverter [24], but
without considering balance of the dc-link voltages.
This work proposes the use of Finite-States MPC for a
four-level three-phase diode-clamped inverter considering
current control and balancing of the dc-link capacitor
voltages.
II. C ONVERTER MODEL
A diagram of the four-level three-phase diode clamped
inverter considered in this work is shown in Fig. 1. Each
output phase of the inverter can be connected to the points
0, 1, 2 or 3. The switching state of each leg of the inverter
will be represented by variables Sa , Sb and Sc , where
Sx ∈ {0, 1, 2, 3}, with x ∈ {a, b, c}.
The relationship between the switching state of one leg
Sa , the switching state of each switch of this leg, and the
output voltage in one phase is shown in the following
table:
Sx Sx1 Sx2 Sx3 vx0
0 0 0 0 0
1 0 0 1 vc1
2 0 1 1 vc1 + vc2
3 1 1 1 vc1 + vc2 + vc3

978-1-4244-1668-4/08/$25.00 ©2008 IEEE 2203

 idc i3
3
ic3 Sa1 Sb1 Sc1
+
vc3 C
Sa2 Sb2 Sc2
2 i2 2 2

ic2 Sa3 Sb3 Sc3

Vdc
+
vc2 C

1 i1 Sa1 1 Sb1 1 Sc1

ic1
+ Sa2 Sb2 Sc2
vc1 C

Sa3 Sb3 Sc3

i0
0

a ia b ib c ic

Fig. 1. Four-level three-phase diode-clamped inverter.

Imag(v) The load current dynamics are described by

di
v=L + Ri (3)
dt
where L and R are the load inductance and resistance.
Considering the variable names defined in Fig. 1,
the behavior of the dc-link capacitor voltages can be
Real (v)
described by
vc1
C = ic2 − i1 (4)
dt
vc2
C = ic3 − i2 (5)
dt
vc3
C = idc − i3 (6)
dt
where currents i1 , i2 and i3 are calculated as a function of
the load currents and the switching state of the converter.
Fig. 2. Possible voltage vectors generated by the four-level three-phase The expression to calculate these currents is the fol-
diode-clamped inverter. lowing:

i1 = (Sa == 1)ia + (Sb == 1)ib + (Sc == 1)ic (7)

The output voltage can be written in vectorial form as
i2 = (Sa == 2)ia + (Sb == 2)ib + (Sc == 2)ic (8)
2 Vdc 2
v= (Sa + aSb + a2 Sc ) = (va0 + avb0 + a2 vc0 ) i3 = (Sa == 3)ia + (Sb == 3)ib + (Sc == 3)ic (9)
3 3 3
(1)
j 2π
where a = e 3 . The 64 possible combinations of Sa , Sb A discrete time equation for the load current dynamics
and Sc generate the 37 different voltage vectors shown in can be obtained from (3) by approximating the derivative
Fig. 2. for a sampling time Ts
The load current vector is defined as  
RTs Ts
2 i(k + 1) = 1 − i(k) + v(k) (10)
i = (ia + aib + a2 ic ) (2) L L
3
and a resistive-inductive load is considered for this work. The discrete-time equations for the capacitor voltages

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 Predictive controller
4-Level Load
Vc*(k) Inverter
i*(k) i L R
Minimization S
i(k) i(k+1) of
g function
Predictive
model 64
vc1(k)
vc1(k+1)
vc2(k) vc2(k+1)
vc3(k)
vc3(k+1)

Fig. 3. Predictive control scheme for the four-level three-phase diode-clamped inverter.

are: IV. I MPLEMENTATION I SSUES

Ts
vc1 (k + 1) = vc1 (k) + (ic2 (k) − i1 (k))
C
Ts
vc2 (k + 1) = vc2 (k) + (ic3 (k) − i2 (k))
C
Ts
vc3 (k + 1) = vc3 (k) + (idc (k) − i3 (k))
C of currents and voltages for the 64 possible switching
where C is the dc link capacitor.
These equations are used by the controller to predict the
behavior of the output current and the capacitor voltages,
as will be explained in the next section.
III. C ONTROL S TRATEGY
Equations (10)-(13) are used to predict the behavior
of the output current and capacitor voltages for each one
of the 64 possible switching states. Each prediction is
evaluated using a cost function. The switching state that
minimizes the cost function is selected and applied during
a whole sampling period.
The cost function considers two terms, the first one
evaluates the load current error in orthogonal coordinates,
and the second term evaluates the error of the three
capacitor voltages.
g =(i∗α − îα )2 + (i∗β − îβ )2
+ A[(Vc∗ 2
− v̂c1 ) + (Vc∗ 2
− v̂c2 ) + (Vc∗
where the hat symbol (ˆ) denotes the predicted variables
at time k + 1, and A is a weighting factor that allows
to adjust the importance of different terms in the cost
function. The capacitor voltage reference is defined as
Vc∗ = Vdc /3.
A block diagram of the predictive controller is shown
in Fig. 3. Here, the measured values of the load currents
and the capacitor voltages are the inputs to the predictive
model block which calculates the predicted values of
these variables for all possible switching states. These 64
predictions are compared with their respective reference
values using the cost function. The switching state which
generates the minimum value of the cost function is
selected as the output of the controller and is applied in
the converter.
Implementation of the proposed predictive control must
(11) consider several important issues. The most important
ones will be briefly explained here.
(12) The proposed control scheme will require a large
amount of calculations, in order to predict the behavior
(13)
states. This will limit the minimum sampling time value.
As explained in [18], it takes less than 7μs to predict
the value of the load currents in a three-phase two-level
inverter, with 8 possible switching states. Considering
that the four-level inverter has 64 possible states, and the
addition of the capacitor voltages prediction, with some
optimization of the code a sampling time of 100μs is
feasible.
The calculation time will also introduce a delay be-
tween the instant in which the measurement are made and
the instant in which the new switching state is applied.
This delay must be considered in the model as explained
in [25], taking into account the one sample delay in the
model and predicting the behavior until time k + 2.
It is also important to mention that not all the vari-
ables used by the predictive model are available from
measurements. For the four-level inverter presented here
it is usual that only the load currents are measured. In
order to implement the proposed predictive controller, the
(14) capacitor voltages must be measured or estimated. In the
− v̂c3 )2 ] results shown below, it has been assumed that the load
currents and capacitor voltages are measured. However,
the case without capacitor voltages measurement is also
considered in the last results obtaining the values of the
voltages from a simple internal model of the converter
within the controller.
V. S IMULATION R ESULTS
The proposed control strategy has been verified by
simulation. The system parameters are the following:
Vdc = 200V , C = 470μF , load resistance and inductance
R = 16.5Ω and L = 15mH. The sampling period for the
control is Ts = 100μs. Unless explicitly mentioned, the
load currents and capacitor voltages are measured.
The load currents and the voltage in one phase are
shown in Fig. 4.(a), when only current control is consid-
ered in the cost function and the capacitor voltages are not

2205
 10 10

5 5
[A]

iload [A]
0 0
load
i

Ŧ5 Ŧ5

Ŧ10 Ŧ10
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

200 200

100 100
van [V]

van [V]
0 0

Ŧ100 Ŧ100

Ŧ200 Ŧ200
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time [s] Time [s]

(a) (a)

250 250

V V
200 dc 200 dc

150 v 150
c1
[V]

[V]
dc

dc
V

100 100

vc1 vc2 vc3

v
50 c2 50

v
c3

0 0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time [s] Time [s]

(b) (b)

Fig. 4. Results without capacitor voltage balancing (A = 0). (a) Load Fig. 5. Results with capacitor voltage balancing (A = 0.5). (a) Load
currents and load voltage. (b) Capacitor voltages. currents and load voltage. (b) Capacitor voltages.

controlled, i.e A = 0. The capacitor voltages are shown
in Fig. 4.(b). It can be noted that the current waveform is
deteriorated as the capacitor voltages are out of balance.
By changing the weighting factor to A = 0.5, the
capacitor voltages can be controlled, as shown in Fig.
5. The load currents present low harmonic distortion and
the capacitor voltages are completely balanced.
The behavior of the proposed controller for a step in the
amplitude of the reference load current is shown in Fig. 6.
The step change is followed with fast dynamic response
by the load currents while the capacitor voltages are kept
constant.
Results for the same reference step when the capacitor
voltages are not measured are shown in Fig. 7. Here the
capacitor voltages are estimated using an internal model
based on the load current measurements and the applied
switching state. It can be seen that the current control is
not affected, but some steady state error and unbalance
appears in the capacitor voltages. However, they are still
under control. This issue can be fixed using a better
voltage estimation, for example a state observer.
VI. C ONCLUSIONS
A new predictive control strategy for a four-level three-
phase diode-clamped inverter has been proposed. This
scheme considers load current control and balancing of
the dc link capacitor voltages.
The proposed strategy is simple and easy to implement.
It provides fast dynamic response for the load current
control and guarantees capacitor voltage balance by con-
sidering both, current and voltages, in the cost function.
It has been shown that capacitor voltage balance is kept
during transients as well as during steady state operation.
There is no need of modulators, the control signals for
the power switches are generated directly by the control.
Future work on the proposed predictive control includes
experimental results and controlling the capacitor voltages
without measuring them.
Finite-States Model Predictive Control presents a dif-
ferent and powerful approach for the control of power
converters.
ACKNOWLEDGEMENT
The authors gratefully acknowledge the financial sup-
port provided by the Chilean Research Fund CONICYT-

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 10 10

5 5
[A]

iload [A]
0 0
load
i

Ŧ5 Ŧ5

Ŧ10 Ŧ10
0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08

200 200

100 100
van [V]

[V]
0 0

an
v
Ŧ100 Ŧ100

Ŧ200 Ŧ200
0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08
Time [s] Time [s]

(a) (a)

250 250

V Vdc
200 dc 200

150 150
[V]

[V]
dc

dc
V
V

100 100

vc1 vc2 vc3 vc1 v v

c2 c3

50 50

0 0
0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08
Time [s] Time [s]

(b) (b)

Fig. 6. Results with capacitor voltage balancing during a step in the Fig. 7. Results with capacitor voltage balancing during a step in
amplitude of the reference current. (a) Load currents and load voltage. the amplitude of the reference current. The capacitor voltages are not
(b) Capacitor voltages. measured. (a) Load currents and load voltage. (b) Capacitor voltages.

FONDECYT (Grant 1080443), the Industrial Electronics
and Mechatronics Millennium Science Nucleus and by
Universidad Técnica Federico Santa Marı́a. This work
has been also supported by Grant TEC2005-08042-C02-
02/MIC, Ministerio de Educación y Ciencia, Spain.
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