IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO.

6, JUNE 2015 1463

Design of On-Chip Gate Drivers With Power-Efficient

High-Speed Level Shifting and Dynamic Timing
Control for High-Voltage Synchronous Switching
Power Converters
Zhidong Liu, Student Member, IEEE, Lin Cong, and Hoi Lee, Senior Member, IEEE

Abstract—Two integrated high-speed gate drivers to enable

high-frequency operation of synchronous rectifiers in high-voltage
switching power converters are presented in this paper. The first
synchronous gate driver for a CMOS power train consists of a
capacitively coupled level shifter (CCLS) that offers negligible
propagation delays and no static current consumption, and
requires only one off-chip capacitor to enable high-side power
pMOS driving capability without any external floating supply. The
second synchronous gate driver consists of a low-power high-speed
dynamically controlled level shifter (DCLS) with a reliability-en-
hanced error-suppression technique for driving a dual-nMOS Fig. 1. HV gate driver involving both HV and LV transistors in a generic syn-
power train. In addition, a dynamic timing control (DTC) is chronous HV buck converter to interface between a LV control signal and a HV
developed to generate proper dead time for power FETs in order power train.
to enable soft switching operation of the converter under different
input voltages for enhancing the converter reliability. The con-
verter power efficiency can be also improved by minimizing both
switching and short-circuit power losses under high-input-voltage high switching frequency so as to reduce the required values and
conditions. Implemented in a 0.5 µm 120 V CMOS process, both thus volumes of passive components. For improving the power
proposed CCLS and DCLS have demonstrated to shift up 5 V efficiency, the capability of using a synchronous rectifier in the
signal to 100 V and 40 V, respectively, improving the FoM by at HV power stage would be beneficial to the converter power ef-
least 10 times and 2.9 times compared to respective state-of-the-art
level shifters. The DTC circuit enables proper ZVS operation in
ficiency, because properly controlling both high-side and low-
a synchronous buck converter with the CCLS-based gate driver side power FETs in the synchronous design can realize zero-
over a wide input supply range from 40 V to 100 V, providing a voltage switching for minimizing the converter switching power
converter maximum power-efficiency improvement of 11.5%. loss [1], [2]. The lower on-resistance of the high-side power
Index Terms—Capacitively coupled level shifter, dynamic FET in the synchronous design would also result in smaller con-
timing control, dynamically controlled level shifter, high-voltage duction power loss of the converter compared to using a com-
synchronous power converters, on-chip gate drivers, zero-voltage mercial power Schottky diode as the high-side power switch
switching.
in the asynchronous design. Fig. 1 shows a generic HV buck
converter, which consists of a HV power train with a pair of
I. INTRODUCTION power FETs to form the synchronous rectifier; a low-voltage

I N RECENT years, the continuous growing markets in smart

electronic vehicles, renewable energy systems, high-bright-
ness LED lighting systems, etc. create a huge demand for ad-
(LV) control circuit to provide duty ratio information
output voltage regulation; and an on-chip HV synchronous gate
driver to bridge the LV signal and gate drive signals
for

vancing today's high-voltage (HV) power converters for cost
and energy savings. It is necessary to maximize the power den-
sity and the power efficiency of the HV power converters. For
enhancing the power density, the converter has to operate at a
Manuscript received September 16, 2014; revised January 12, 2015 and
March 30, 2015; accepted April 03, 2015. Date of publication May 04, 2015;
date of current version May 22, 2015. This paper was approved by Associate
Editor Woogeun Rhee. This work is supported by the U.S. National Science
Foundation CAREER program under the grant number NSF-ECCS-1056013.
The authors are with the Department of Electrical Engineering, University of
Texas at Dallas, Richardson, TX 75080 USA (e-mail: hoilee@utdallas.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2422075
,
for the synchronous rectifier. The design of an on-chip HV
synchronous gate driver is crucial because it would affect the
reliability, the switching frequency and various power losses of
the power converter under high-input-voltage condition.
To design a high-performance on-chip gate driver, under-
standing power FETs in the HV power train is essential. Power
FETs in this paper are thin-oxide HV MOSFETs that are
commonly used nowadays due to the advantages of signifi-
cantly lower on-resistance and threshold voltage compared to
those of thick-oxide counterparts. Although the rating
of the thin-oxide HV devices can sustain high voltages, its
maximum allowable rating is typically the same as LV
transistors and is about 5 V. This low rating creates the

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1464
Fig. 2. Structures of generic HV gate drivers for (a) CMOS and (b) dual-nMOS power trains.
challenge of driving the high-side thin-oxide HV device under
high-input-voltage condition because a gate control signal in
the range of 0–5 V needs to be referenced to its high-voltage
source terminal. Hence, a high-performance level-shifting tech-
nique is important in the gate driver for the high-side driving to
up-shift the gate control signal from low to high common-mode
voltage, while still keeping the signal swing within the safety
limit of the high-side thin-oxide device. Fig. 2(a) and (b) shows
generic structures of on-chip synchronous gate drivers for
CMOS and dual-nMOS power trains, respectively [3], and the
overall power dissipation, reliability and propagation delays
of both types of gate drivers are highly related to the design
of the level shifters. Regarding level shifters in the gate driver
for the CMOS power train, both power dissipation and the
propagation delays need to be minimized. Driving the high-side
power nMOS, since part of the level shifter in the gate driver
is referenced to voltage at the switching node as shown
in Fig. 2(b), the level shifter needs to possess good immunity
to fast slewing of for ensuring the reliability of
the gate driver in addition to both high-speed and low-power
requirements. Moreover, high-performance gate drivers need to
(i) have a floating DC supply to enable high-side circuitries like
logic circuitry and buffers using thin-oxide isolated low-voltage
devices for better speed and lower power dissipation consid-
erations; (ii) have appropriate dead-time control to minimize
shoot-through currents during switching transitions of power
FETs and even enable zero-voltage-switching (ZVS) operation
in the power converter for minimizing switching power loss
under high-voltage condition; and (iii) have digital buffers to
provide sufficient transient current to charge/discharge the gate
terminals of power FETs for reducing propagation delays of
the gate driver.
Different level shifters have been previously reported for
driving a high-side power pMOS [3]–[10] or a power nMOS
[11], [12]. All reported level shifters for high-side power
pMOS would dissipate considerable static power due to current
flowing from the high-voltage input supply to ground [3]–[9]
(or an intermediate-voltage node via connected diodes [10]).
The operation of some level shifters also requires an additional
floating bias voltage that is usually generated by two off-chip
components: a power diode and a capacitor [8], [9]. On the
other hand, those reported level shifters for high-side power
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015
Fig. 3. Structure of the proposed on-chip CCLS-based gate driver with dy-
namic timing control for the CMOS power train.
nMOS are lack of the capability of addressing issues associated
with high slewing at the switching node [11], [12].
Furthermore, ZVS was previously reported to minimize
both switching and short-circuit power losses of HV power
converters [1], [2]. To enable ZVS of both on-chip power
FETs in the synchronous power converters, different dead-time
control schemes were demonstrated in low-voltage buck con-
verters [13]–[16]. Some approaches require complicated circuit
implementations involving clocked sample-and-hold circuit
and V-to-I converter to generate dead-time for each power
transistor, thereby resulting in considerable static current con-
sumption for providing 10s of nanosecond dead-time [13]–[15].
Other approach demands for extra external components [16]
that would increase the form factor of the power converter. All
of these approaches are difficult to be extended to the high-side
gate driving in HV power converters.
To address the above issues associated with designing HV
gate drivers, this paper proposes two synchronous gate drivers
for CMOS and dual-nMOS power trains, respectively. The first
synchronous gate driver for the CMOS power train consists
of a capacitively coupled level shifter (CCLS) that provides
negligible input-to-output delay, consumes zero static current,
and uses only one off-chip capacitor as a built-in floating
supply for high-side gate driving. The second HV gate driver
for the dual-nMOS power train is enabled by a low-power and
high-speed dynamically controlled level shifter (DCLS) with
enhanced immunity. A dynamic timing control (DTC)
is also developed to enable ZVS operation of synchronous
converters under different input voltages. This paper is or-
ganized as follows. Sections II and III discuss the design of
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL 1465

Fig. 4. (a) Schematic and (b) operation waveforms of the proposed high-voltage capacitivelycoupled level shifter (CCLS).

CCLS- and DCLS-based HV gate drivers. Section IV details are turned off in the steady state without affecting the operation
the descriptions of the DTC scheme [17]. Sections V and of the level shifter. Note that the previously-reported symmet-
VI provide measurement results of the proposed gate drivers in rical capacitively-bootstrapped level shifter [10] is not used to
synchronous buck converters and conclusions, respectively. directly drive the high-side power pMOS transistor in a power
converter, and the proposed CCLS and [10] are different in cir-
II. PROPOSED HV GATE DRIVER FOR CMOS POWER TRAIN cuit structures, static power dissipation and start-up operation.
The structure of the proposed on-chip HV gate driver for the The asymmetric CCLS core (i.e., the sizes of and (the
CMOS power train in a synchronous buck converter is shown left branch) are much larger than those of and (the right
in Fig. 3. Both high-side and low-side power FETs are on-chip branch)) is designed by considering both strong driving capa-
thin-oxide HV CMOS devices in this design. With the use of bility and high area efficiency. Since the gate terminal of the
the high-side power pMOS, the high-side gate drive signal large-size high-side power pMOS is connected to the top
generated by the proposed gate driver would be referenced to plate of at node , the sizes of , and buffer transistors
the supply rail . Hence, the reliability of the proposed need to be much larger than those of , and inverter tran-
gate driver would not be influenced by any variation of . The sistors for providing sufficient transient current to charge/dis-
proposed gate driver consists of a capacitively coupled level charge the gate capacitance of . also acts as the built-in
shifter (CCLS)formed by two capacitors , to up-shift a floating supply and is the only off-chip component in the pro-
low-voltage gate control signal to a high-side gate drive posed gate driver for the CMOS power train. Smaller sizes
signal with the high common-mode voltage; a dynamic- and are realized on-chip to minimize the number of off-chip
timing control (DTC) block to provide appropriate dead-time components in the gate driver, while signals at nodes and
between two gate drive signals and for enabling ZVS are still kept complementary to those at nodes and , respec-
of both power FETs and ; and a pair of LV tapered tively.
buffers (Buf) to provide strong driving capability for ensuring In this CCLS, any signal variation at node (or ) will be di-
fast gate-voltage switching of and . Compared to the rectly coupled to node (or ) via (or ). The only delay
generic gate driver for the CMOS power train in Fig. 2(a), the element in the CCLS is the inverter between nodes and .
proposed gate driver reduces the circuit complexity to generate Hence, the delay from to is negligible and that from to
a supply voltage as the high-side ground terminal, and (or ) is about one gate delay of 0.5 ns. The proposed CCLS
enables using only LV transistors to realize a low-side tapered thus offers sub-nanosecond delay for translating voltage signal
buffer inside the CCLS for driving instead of forming the from low to high common-mode voltage. Moreover, due to the
high-side buffer with larger-size isolated transistors. It should presence of and , there is no static current consumption in
be noted that is 5 V and can be as high as 100 V the level shifter core. The simulated dynamic current consump-
in this design. The detailed design of the DTC will be discussed tion and the total current consumption of the CCLS are the same
in Section IV. as 0.25 A, which is from the low-side inverter in the CCLS.

A. High-Voltage Capacitively Coupled Level Shifter With B. Start-Up Operation of CCLS

Built-in Floating Supply Since the voltage swing at nodes , , and is only 5 V
Fig. 4(a) shows the schematic of the HV capacitively cou- in the proposed CCLS, both capacitors and need to sus-
pled level shifter (CCLS), which consists of HV charging cir- tain a high voltage of . Hence, proper charging
cuitries formed by transistors ; an asymmetrical level and from 0 to appropriate voltages before enabling the
shifting core realized by capacitors , and two pull-up iso- gate driver during initial start-up condition is crucial to the reli-
lated LV pMOS , ; the low-side buffer; and an inverter ability of the gate driver and the power converter. This start-up
[17]. The HV charging circuitries only provide charging current operation is carried out by the HV charging circuitries in the
for and in the start-up phase and transistors proposed CCLS.
1466 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 5. Simulated voltage waveforms of the CCLS during the power-up condition under slew rates of at (a) 8 s and (b) 10 V/ms. (Note that 10 V/ms
slew rate of is typical when the input of a HV power converter is loaded with a capacitor of 10s of F.)

The start-up mechanism of the CCLS is shown in Fig. 4(b).

When the supply rail is being powered up initially, an en-
able signal of the gate driver is set to logic “1” (i.e., )
to turn on transistors and for enabling the HV charging
circuitries formed by transistors . As ,
at node is charged by a current such that will
be increased linearly to follow the increase of . On the
other hand, as the size of is much smaller than that of ,
two diode-connected HV transistors , charge such
that reaches . The value of will turn on
in the level-shifting core to facilitate the charging process
of . Note that the size of is much larger than that of
, so the total transient current for charging is dominated
by the current of . This would reduce the parasitic capac-
itance at node and thus significantly decrease the required
value and implementation area of . The design consideration
of is discussed in Section II-C. During the start-up phase, Fig. 6. Operation of coupling capacitor as the floating supply and lev-
transistor is always turned off. The gate-to-source voltage elshifting undercharge transfer (a) from to and (b) from to .
of controls that of to allow operating in the triode
region. The size of is designed to control its on-resistance
such that can follow the ramp-up of and is always voltage than LV transistor for eliminating any undesirable
smaller than the minimum threshold voltage of (1.65 V) leakage current of in the steady state. High-side transistors
during the power-up condition. Power FET is thus turned , , and are LV transistors in isolated HV N-wells that
off during start-up. Fig. 5(a) and 5(b) shows that the simulated can handle high common-mode voltage relative to the chip sub-
can be always smaller than 1.65 V even with fast strate voltage potential (or ground). The HV N-well is a standard
and typical ramp-up slew rates of 8 s and 10 V/ms, feature of the HV CMOS process.
proving that would not be turned on to affect the start-up
operation. C. Steady-State Operation and Design Considerations of
When finally reaches the desired value, signal CCLS
is changed to logic “0” to disable the HV charging circuitries. Since the large-size high-side power pMOS is used to
The level-shifting core will be then enabled in the steady state. source current to the power converter, a large-value parasitic ca-
Transistors are turned off in the steady state to cut pacitor of is loaded at node (gate terminal of ).
down the quiescent current consumption and thus the power dis- Hence, the charge in would be redistributed between and
sipation of the gate driver. It should be noted that transistor during the switching transitions of power FETs and this de-
is turned on to pull down the voltage at the source terminal of termines the voltage at node . The operation of the charge
to ground for avoiding its uncertain floating state. Transistor redistribution is illustrated in Fig. 6.
is a HV device in the cascode current mirror to sustain high During the transition of changing from to 0 as
voltage stress, while HV transistor has a higher threshold shown in Fig. 6(a), transistor in the last stage of the tapered
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL 1467

Fig. 7. Structure of the proposed on-chip DCLS-based gate driver for the dual-nMOS power train.

buffer will be turned on to sink current from . Charge will III. PROPOSED HV GATE DRIVER FOR DUAL-NMOS
be thus transferred from to . Both voltages at nodes POWER TRAIN
and will drop instantaneously with the intention to turn on Since an nMOS offers higher mobility than a pMOS, using
power FET . It is crucial to design the value of such the nMOS as the high-side power FET would result in much
that voltage swing at node could be larger than the smaller converter implementation area for providing the same
threshold voltage of but within the maximum allowable on-resistance than the high-side power pMOS. However, when
gate-to-source voltage rating of HV pMOS for ensuring its driving the high-side power nMOS , the high-side driving
proper turn on with minimal on-resistance. The value of circuitries must be referenced to voltage at the switching
can be obtained as node of the converter as shown in Fig. 2(b). This type of the
gate driver would thus suffer from inherent reliability issue due
(1)
to high slewing of . Besides, the gate drive signal
must be larger than for properly turning on .
The voltage swing at node is . Due to the presence
These two issues cause the gate driver design for the dual-nMOS
of parasitic capacitance , (1) indicates that would be
power train to be a big challenge. The structure of the pro-
always smaller than and its value depends on
posed HV gate driver for a synchronous buck converter with
the relative sizes of and . The value of can be found as
dual-nMOS power train is shown in Fig. 7. It consists of a boot-
(2) strap circuit for generating the floating supply for high-side cir-
cuitries in the gate driver, a HV dynamically controlled level
A similar charge redistribution (i.e., charge is transferred shifter (DCLS) for up-shifting low-voltage control signal
from to ) as shown in Fig. 6(b) also occurs during the to the high-side signal with improved immunity,
transition of changing from 0 to for turning off two buffers for charging/discharging input capacitances of
, leading to the same equations of and in (1) and , and a dead-time generator for providing appropriate
and (2). From (2), if and , dead-time between two gate drive signals and .
should be at least 9 times larger than . In this design, is
about 500 pF, and thus an off-chip ceramic capacitor of 5 nF A. Bootstrap Circuit for Floating Supply
is selected as . Without loss of generality, (2) can be also As indicated in Fig. 2(b), a floating supply higher
used to design . An on-chip capacitor of 5 pF is chosen than is needed to power high-side circuitries in the HV
for obtaining at node , because the parasitic gate driver for the dual-nMOS power train. The bootstrap cir-
capacitance at node in Fig. 4(a) is much smaller than . cuit formed by an external diode and an external capacitor
The operation of the CCLS in the steady state can be un- can generate this floating supply [18] and is adopted in the
derstood with the timing waveforms in Fig. 4(b). When the proposed gate driver in Fig. 7. The operation of the bootstrap
low-side gate control signal is , voltages at nodes , circuit is shown in Fig. 8. The bootstrap capacitor needs
, and are equal to , , and , to be pre-charged before the switching operation of the power
respectively. Both and power FET are turned off, while converter. During the start-up phase, the low-side power FET
is on to connect the top plate of to such that the is turned on to provide a path for pre-charging as indi-
voltage across is . When is 0, voltages cated in Fig. 8(a). Voltage across is thus charged to
at nodes , , and are changed to 0, , and , where is the forward voltage drop of .
, respectively, and thus is turned off. The voltage of During the on-time of the high-side power FET as indicated
at node turns on both and , and in Fig. 8(b), works as the floating supply with
the voltage across is . Since high voltages to power high-side circuitries that con-
are developed across and in the steady state, pull-up tran- tain the high-side circuits of the DCLS and the tapered buffer for
sistors and , transistors in the tapered buffer and the in- driving . Since the voltage across would gradually de-
verter between nodes and in Fig. 4(a) can all be realized crease due to the power dissipation during the on-time of ,
by low-voltage devices in the proposed CCLS. the value of is chosen to be 0.1 F in this design to maintain
1468 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 8. Operation of the bootstrap circuit: (a) charging the bootstrap capacitor and (b) working as a floating supply for the high-side circuitries.

Fig. 9. (a) Schematic and (b) operational waveforms of the proposed high-voltage dynamically controlled level shifter (DCLS).

relatively constant during on-time of under different at for improving reliability of high-side LV transis-
duty ratios. Note that voltage gives the highest on-chip tors . When on-time of and is much shorter
common-mode voltage, so it needs to be within the safety rating than the on-time of , the average current consumption of the
of the HV CMOS process for reliability consideration. level-shifting core can be significantly reduced. The signal re-
covery circuitry then converts short pulses at nodes and to
B. Proposed Dynamically Controlled Level Shifter the output such that would have the same on-time
and frequency as the original input signal for driving the
Fig. 9(a) shows the schematic of the proposed DCLS, which high-side power nMOS via the buffer (Buf). Since only a
consists of (i) a short-pulse generator; (ii) a level-shifting core few stages of digital logics are used to implement the proposed
realized by a current source , a HV nMOS differential pair DCLS, high-speed input/output propagation delay in the order
, , and isolated LV pMOS transistors ; and (iii) of nanoseconds can be achieved, helping to minimize the prop-
the high-side recovery circuitries composed of inverters and a agation delay of the gate driver. Also, the power dissipation of
R-S latch. The proposed dynamic level shifting is realized in the level-shifting core determines the power dissipation of the
three steps—short-pulse generation, level shifting, and signal proposed DCLS. By just turning on the level-shifting core for
recovery. Firstly, as shown in Fig. 9(b), two short pulses only 40 ns (20 ns for each and ) instead of 1 s, the
and corresponding to the rising and falling edges of the average static current consumption of the proposed DCLS is re-
input signal are extracted and fed into the gate terminals duced from 200 A to 8 A with the 1-MHz input signal. The
of HV transistors and , respectively. Transistor (or simulated dynamic current consumption is 4.3 A due to the
) will be turned on during the short-pulse interval of low-side and high-side logic circuitries. Hence, the total current
(or ) in order to generate an inverted up-shifted short pulse consumption of the DCLS is 12.3 A.
at node (or ). The diode-connected transistors and
in the level-shifting core are used to determine the pulse am- C. Design Consideration for Reliability Enhancement
plitude at nodes and , while the cross-coupled transistors When transistor (or ) is turned on, controlling the am-
and latch up voltages at nodes and . Two pairs of plitude (or ) of the short-pulse at node (or
transistors and form two dynamic current ) is important to ensure the correct operation of the whole level
sources to eliminate voltage spikes at nodes and under high shifter and thus the gate driver. If it is too small to trigger the
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL 1469

Fig. 10. (a) Schematic of the proposed level shifting stage and (b) improved immunity by high-side dynamic currents and .

high-side signal recovery circuitry, it would cause the mal-func- to support high voltage, they need to be implemented by larger-
tion of the level shifter. On the other hand, if it is larger than area HV transistors rather than smaller-area LV counterparts.
the maximum allowable 5 V ratings of LV transis- Larger-area HV transistors would result in larger capacitances
tors, isolated LV transistors of high-side circuitries in the DCLS of and and thus larger amplitudes of voltage un-
would break down. Therefore, the short pulse amplitude at dershoots, giving rise to a serious reliability threat to the level
(or ) should be maintained as shifter. On the other hand, if of is negative, the value
of is suddenly decreased and both body diodes
(3) and are turned on to minimize the voltage overshoots at
nodes and . Hence, the maximum value of both
where is logic threshold voltage of the signal recovery and will not exceed (i.e., 5 V) and there is no
circuitry. impact on the transistors' reliability and level shifter's function.
The reliability enhancement by the proposed DCLS will be Consider there are no dynamic current sources, only increasing
explained from the perspective of the interference of high the current consumption of the level-shifting stage can help
of . In the HV gate driver for the dual-nMOS power train, reduce issue. However, the power dissipation of the level
the high-side circuitries that contain the signal recovery circuit shifter would be increased considerably due to the high input
of the level shifter and the digital buffer for driving power FET supply voltage of the level-shifting stage.
are fabricated in an isolated HV floating well to handle high Both dynamic current sources realized by in the
common-mode voltage with respect to the substrate potential. proposed DCLS only provide extra transient current to charge
Since supply voltage of the high-side circuitries and and under positive of , thereby minimizing
are voltages at top and bottom plates of the bootstrap capac- the voltage undershoots at nodes and . Hence, both reli-
itor , respectively, the of will couple to . ability of high-side LV pMOS transistors and cor-
Voltage is also connected to the HV floating well, all rect level shifter output can be guaranteed even under fast
high-side circuitries in the HV floating well would thus suffer slewing of . Note that the proposed dynamic current sources
from the interference from of . only take effect when experiences fast positive slewing tran-
As shown in Fig. 10(a), equivalent parasitic capacitors sients and they do not affect the operation of the level shifter nor
and at nodes and , respectively, and body diodes consume extra static current under the normal condition. There-
and associated with transistors and , respectively, fore, the proposed dynamic current sources offer a power-ef-
are used to explain the circuit operation of the level-shifting ficient way to address high reliability issue in the level
core under positive and negative slewing of . Under shifter. Fig. 11 shows the simulated waveforms of the proposed
high positive/negative , changes accordingly, but DCLS with (in red) and without (in blue) the dynamic current
and cannot response instantly due to the presence of sources . Voltage undershoots are significantly re-
and . If is positive at node , voltage un- duced with four additional on-chip transistors to
dershoots indicated in “blue” in Fig. 10(b) occur during these ensure proper operation of the DCLS under a fast of
switching transitions. The voltage undershoot at node could 40 V/1 ns of .
cause to be negative. In other words, gate-to-source Fig. 12 shows simulated waveforms of the DCLS and the cor-
voltages of and would be larger than 5 V, compromising responding gate driver. The rising- and falling-edge propagation
their device reliability. The voltage undershoot at node could delays of the proposed DCLS are 1.5 ns and 2 ns, respectively.
cause to be smaller than logic threshold of the signal With a 500-pF capacitor loaded at the output of the DCLS-based
recovery circuitry, leading to incorrect output of the level gate driver, both rising- and falling-edge propagation delays are
shifter. Generally, the amplitudes of the voltage undershoots due only 5 ns and 4.5 ns, respectively, due to sufficient transient cur-
to positive increase with the slope of the voltage change rents provided by the digital buffer. The fast propagation delays
and the capacitances of and . Since and have
1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 13. Structure and waveforms of QSW-ZVS operation in synchronous buck

converters.

Fig. 11. Simulated transient waveforms of the proposed level shifting stage
with and without high-side dynamic currents
power loss associated with discharging can be eliminated
and .
if is turned on after decreasing to 0, as is dis-
charged by the peak inductor current during this dead-time in-
terval. Similarly, a lossless low-to-high transition for at the
switching node can be also achieved by turning on after
increasing to , as is charged by the negative inductor
current during this dead-time interval. The ZVS of both power
FETs is thus achieved during switching transitions. However,
if only fixed dead-time is provided by the gate driver without
tracking the transition, it cannot guarantee the establish-
ment of ZVS when the input voltage changes. Hence, dynamic
dead-time control which can detect the status and thus match
the transition time (i.e., to provide sufficient dead-time) for both
power FETs is crucial in the gate driver to establish ZVS under
different input voltages.

B. Proposed Dynamic Timing Control and Its Operation

Fig. 12. Simulated propagation delays of the DCLS-based HV gate driver
when driving a 500 pF capacitive load. Dynamic timing control (DTC) is developed and is applied
to CCLS-based gate driver for enabling QSW-ZVS in the buck
converter with the CMOS power train. Fig. 14 shows the cir-
of the DCLS-based gate driver enable multi-MHz operation of cuit implementation and operation waveforms of the proposed
the buck converter under high input voltages. DTC that consists of a HV signal voltage divider formed by ,
IV. PROPOSED DYNAMIC TIMING CONTROL , and ; detection logic formed by , ; a gate-drive
timing control circuitry; and mode selection logic. In the DTC
A. Zero-Voltage-Switching of Synchronous Buck Converter circuit, voltage is scaled down via the divider to determine
Switching power loss due to charging/discharging the total the state of zero drain-source voltage of power switches. When
capacitance at the switching node occurs in traditional is increasing from 0 to , the scaled indicates
hard-switched HV synchronous power converters [1]. Since the zero drain-source voltage of if reaches the voltage of
switching power loss is proportional to the square of the input the logic threshold of the first inverter (i.e., signal will
voltage, the switching power loss is considerable under HV be then changed to logic “1”). In this design, is set to 1.2 V
condition. Converter short-circuit power loss due to substantial to ensure optimum dead-time at , where the op-
shoot-through current would also occur if insufficient dead-time timum dead-time implies is turned on at the instant when
is provided by the gate driver. Both switching and short-circuit reaches . The dead-time generated by the pro-
power losses could greatly degrade the power efficiency of HV posed DTC circuit is given as
power converters.
Quasi-square-wave zero-voltage switching (QSW-ZVS) was
previously reported to realize soft switching in synchronous (4)
power converters in order to minimize the switching loss and the
short-circuit power loss [2], [13]. The main inductance should where is the delay caused by the HV signal voltage
be designed to be smaller than the critical inductor value such divider and the -adjusted inverter. in (4) is
that the negative inductor current can be generated to charge controlled by the auto-adjustable delay element in which the
at node during switching transitions. Fig. 13 shows the size ratio between and is 2 in the DTC circuit and the
scheme and waveforms of the QSW-ZVS operation in buck con- logic threshold of the delay-element load is 2.5 V. In the de-
verters with either a CMOS or dual-nMOS power train. The sign phase, the for and is designed 8 ns larger
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL 1471

Fig. 14. Schematic and waveforms of the proposed dynamic timing control in gate drivers.

than the optimum at to guarantee ZVS

over process variations and device mismatches. Note that when
is turned on later than the optimum dead-time, the body
diode of the high-side power switch is turned on to result
in the body-diode conduction loss though ZVS is still achieved.
However, even with the worst case of a 25-ns delay offset from
the optimum dead-time under PVT variations and device mis-
matches, the largest inductor current ripple of 2 A in the buck
converter and the minimum load current of 50 mA, the body-
diode conduction loss is only 8.3 mW at the switching fre- Fig. 15. Simulated waveforms when the buck converter with CMOS power
quency of 500 kHz and is typically insignificant in HV buck train changes from hard switching to ZVS at .
converters. Hence, the appropriate dead-time (8 ns larger than
the optimum ) that establishes ZVS with negligible im-
pact of the body-diode turn-on loss on the converter power ef- wide input range from 40 V to 100 V to significantly improve
ficiency is provided by the DTC circuit for and at the converter power efficiency.
. This proposed DTC circuit also consists of a mode selection
From (4), the auto-adjustable delay element in the DTC cir- pin to enable the converter performing either hard switching
cuit can increase with and the range of is or soft switching . In the
from 25 ns to 80 ns for increasing from 40 V to 100 V. hard-switching mode, the gate control signals and are
This is because when is increased beyond 40 V, the bias synchronized with after adding dead-times, while in the soft-
currents of increase linearly to cause the reduction of switching mode, gate drive timing can be adjusted dynamically
bias current of and charging capacitor . Hence, the by the tunable delay and the combination of with to en-
rising edge of signal is postponed for increasing the dead- sure ZVS operation under different input voltages. The sim-
time between gate control signals and . Dead-times be- ulated result of the mode transition from the hard switching
tween power FETs and can be thus generated to en- mode to the soft switching mode at is given in
sure ZVS of under different input voltages. Note that for Fig. 15. Large current spikes of 3 A are generated at the turn-on
safety consideration of using all LV transistors in the DTC cir- instant for charging during the hard-switching mode. The
cuit, voltage is limited to 4 V,which corresponds to the max- soft switching enabled by the proposed DTC circuit to realize
imum 100 V by choosing . ZVS in both power FETs minimizes the current spikes. Both the
Similarly, when is decreasing from to 0 due to power efficiency and the reliability of the converters can be en-
discharging by the peak inductor current, its rate is much faster hanced. To verify the robustness of the proposed DTC circuit,
than that of changing from 0 to by the small nega- the Monte-Carlo simulation of 1000 samples is shown in
tive inductor current. A delay (i.e., dead-time between and Fig. 16(a). It indicates the average delay offset from the appro-
) is generated by the proposed DTC circuit when drops priate is 4.6 ns with a standard deviation of 2.4 ns. Since
to to cause signals and changing to logic “0”. This the appropriate with variation is always larger than the
dead-time is sufficient to ensure ZVS of for varying optimum , the establishment of ZVS at
between 40 V and 100 V. By adopting the proposed DTC cir- is guaranteed under process variations and device mismatches.
cuit into the proposed CCLS-based gate driver, QSW-ZVS of Fig. 16(b) further shows that the ZVS is established under dif-
both power FETs in the buck converter are guaranteed over the ferent corners and temperatures, while Fig. 16(c) depicts that
1472 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 16. (a) Monte-Carlo simulation result of the delay offset from the appropriate dead-time. (b) Simulated waveforms under different corners and tempera-
tures. (c) Simulated waveforms under different supply voltages.

Fig. 17. Micrographs of proposed (a) CCLS-based and (b) DCLS-based gate drivers with on-chip power FETs.

different values of are generated to establish ZVS when

the input supply varies from 40 V to 100 V. Due to the features
of easy implementation and high-voltage compatibility, the pro-
posed DTC circuit can be extended to other types of HV gate
drivers to enable ZVS in synchronous HV converters.

V. MEASUREMENT RESULTS AND DISCUSSIONS

In order to verify the performances of the proposed syn-
chronous HV gate drivers for CMOS and dual-nMOS power
trains, both gate drivers with on-chip power switches and
are fabricated in a 120 V 0.5 m CMOS process, in which Fig. 18. Measured voltage waveforms of the CCLS during the start-up phase
the typical threshold voltages of LV nMOS, LV pMOS, HV when is ramping up from 0 to 100 V and is loaded with a 22 F input
nMOS, and HV pMOS transistors are 0.70 V, 1 V, 2.65 V, capacitor.
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL 1473

Fig. 19. Measured input and output of the CCLS in the gate driver under (a) and (b) .

Fig. 20. Measured propagation delay of the CCLS-based gate driver from input to output under .

and 1.85 V, respectively. Both chip micrographs are shown

in Fig. 17. The total chip areas of these two designs including
bonding pads are 7.0 mm and 5.6 mm , respectively. Most
of total chip areas in both designs are occupied by power
FETs. Compared to using the high-side power pMOS, the
smaller required size of the high-side power nMOS mainly
results in the chip area difference of 1.4 mm . The areas
of proposed CCLS-based and DCLS-based gate drivers are
about 1.15 mm and 1.1 mm , respectively. A capacitor
of 5 pF that can support up to 120 V in the CCLS occupies
0.071 mm . In the design phase, the DTC circuit is adopted
in the synchronous buck converter with the CCLS-based gate
driver to enable soft-switching operation of the converter over
Fig. 21. Measured transient-state waveforms of the synchronous buck con-
a wide input range from 40 V to 100 V. The other synchronous verter changing from the hard-switching mode to the soft-switching mode by
buck converter with the DCLS-based gate driver operates in using Mode control bit.
the hard-switching mode with the maximum input voltage of
40 V. Both buck converters can deliver a maximum output
power of about 10 W. An input capacitor of 22 F is used at the output of the proposed CCLS. The voltage swing of
input supply for both buck converters with CCLS-based and is 4.5 V with reference to different values of after level
DCLS-based gate drivers. For closed-loop measurements of the shifting performed by the CCLS. Although the input capaci-
buck converter, an external voltage-mode PWM controller LM tance at the gate of power FET is 500 pF, both rising-
2737 [19] is used to generate signal at the input of the gate and falling-edge propagation delays from to , which
driver for providing a regulated output voltage. A waveform can be observed from the zoom-in waveforms in Fig. 19(b), are
generator is used to generate PWM signal at the gate driver negligible. Hence, it proves that the delay of the CCLS is only
input with different duty ratios and switching frequencies for the inverter delay between nodes and in Fig. 4(a) and is
the buck converter during open-loop measurements. about 0.5 ns. Fig. 20 shows that the measured rising-edge and
Fig. 18 shows the measured voltage waveforms during the falling-edge propagation delays of the proposed CCLS-based
start-up phase. The measured is about the same as , gate driver are 14 ns and 12 ns, respectively. These propaga-
proving the correct start-up operation of the CCLS due to the tion delays are dominated by the delay of the tapered buffer for
off-state of . Fig. 19 shows the measured input and driving large-size , and are sufficient fast to enable the power
1474 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 22. Measured waveforms of the synchronous buck converter with the CCLS-based gate driver performing ZVS operation under (a) and
(b) .

Fig. 23. Measured steady-state inductor current and switching node signal of the buck converter with the CCLS-based gate driver under (a) hard-switching
mode, , mA, and (b) soft-switching mode, , mA.

converter properly operating in the MHz range under high input

voltages.
Fig. 21 shows the measured waveforms of the synchronous
buck converter and verifies proper mode switching operation
of the converter changing from the hard-switching mode to
the soft-switching mode by the Mode signal status. Compared
to the hard-switching mode, of during switching
transitions is much slower in the soft-switching mode. With
the negative inductor current to charge during switching
transitions, is settled to to turn on
after reaches , proving zero-voltage switching
of in the soft-switching mode. Fig. 22 shows measured
low-side and high-side gate drive signals , and
switching node signal of the soft-switched buck converter.
Under both of 80 V (Fig. 22(a)) and 100 V (Fig. 22(b)),
is changed to V after settles to ,
Fig. 24. Measured power efficiency of the buck converter with CCLS-based
and is changed to 5 V after decreases to 0, proving gate driver under different switching modes and values of . The output
ZVS operation of power FETs and . voltage of the buck converter is 24 V.
Fig. 23 illustrates that the synchronous buck converter with
the CCLS-based gate driver functions properly under different
switching modes, supply rails , and output currents . under the soft-switching mode are always larger than those in
In Fig. 23(a) and (b), the worst-case valley negative inductor the hard-switching mode for the entire load range from 50 mA
current of 0.25 A passing through the DC resistance of the to 400 mA. In particular, the ZVS operation enables the con-
inductor has negligible impact on the converter power effi- verter achieving maximum 6.5% and 11.5% power efficiency
ciency. As shown in Fig. 24, the converter power efficiencies improvements under and 80 V, respectively, at
LIU et al.: DESIGN OF ON-CHIP GATE DRIVERS WITH POWER-EFFICIENT HIGH-SPEED LEVEL SHIFTING AND DYNAMIC TIMING CONTROL
Fig. 25. Measured gate drive signals , and switching node signal
(b) , MHz.
Fig. 26. Measured inductor current and switching node signal
, mA, kHz, and (b) , mA,
the minimum load condition, where the switching power loss
is dominant in the converter power efficiency. The peak power
efficiencies of the synchronous ZVS buck converter are 95%
and 91% under and 80 V, respectively. The
output voltage of the buck converter is 24 V.
Fig. 25 shows measured waveforms to verify the operation
of the proposed DCLS-based gate driver. The proposed DCLS-
based gate driver is able to up-shift LV gate control signal
to the HV domain as for driving high-
side power FET under different values of and dif-
ferent converter switching frequencies . Based on the mea-
sured waveforms in Fig. 26, the synchronous buck converter
with the proposed DCLS-based gate driver can operate prop-
erly up to MHz at .
Table I provides the performance comparison of proposed
CCLS and DCLS with prior arts. By taking input supply,
propagation delay and process technology into considerations,
the figure of merit (FoM) from [9] is adopted to gauge their
performances. The smaller the FoM is, the better the perfor-
mance of the level shifter would be. Compared with previous
state-of-the-art counterparts to drive high-side power pMOS
and nMOS, the proposed CCLS and DCLS offer at least 10
times and 2.9 times improvements in FoM, respectively. The
total current consumptions of the proposed CCLS and DCLS
are much smaller than their respective state-of-the-art counter-
parts for high-side power pMOS and nMOS.
1475
of the DCLS-based gate driver under (a) , kHz, and
of the synchronous buck converter with the DCLS-based gate driver under (a)
MHz.
The features of both proposed gate drivers are summarized in
Table II. The CCLS-based gate driver requires one less off-chip
component for realizing the floating supply and has lower chip
voltage, while the DCLS-based gate driver enables the use of
high-side power nMOS that would need much less chip area for
the power converter. Table III provides the performance com-
parisons of the proposed buck converter with state-of-the-art
counterparts having similar input voltage ranges [20]–[22]. The
soft-switched synchronous buck converter with the proposed
CCLS-based gate driver removes the converter switching power
loss and thus provides higher peak power efficiencies at high
input voltages as compared with other reported hard-switching
counterparts.
VI. CONCLUSION
Two on-chip HV synchronous gate drivers enabled by CCLS
and DCLS are presented in this paper. The proposed HV CCLS
achieves sub-nanosecond delay without consuming any static
current. It also provides a built-in high-side supply with only one
off-chip coupling capacitor to offer strong driving capability for
high-side power pMOS. The proposed low-power high-speed
HV DCLS enhances the gate driver reliability and robustness
with the dynamic current sources. Thanks to the proposed DTC
in gate drivers, zero-voltage-switching operation can be estab-
lished in synchronous rectifiers under different input voltages,
thereby minimizing the switching and the short-circuit power
1476 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

TABLE I
PERFORMANCE COMPARISONS OF STATE-OF-THE-ART LEVEL SHIFTERS

Simulation results.
Extracted from results in the publication.
TABLE II
SUMMARIES OF PROPOSED ON-CHIP HV GATE DRIVERS

Sizes of power switches are constructed to handle the same maximum load current in 120 V 0.5 m CMOS process.

TABLE III
PERFORMANCE COMPARISONS OF DIFFERENT WIDE-INPUT-RANGE BUCK CONVERTERS

The power loss of the controller is not included in the efficiency calculation. When the power loss of the external voltagemode PWM controller LM 2737 is
considered, the peak power efficiencies of the proposed buck regulator becomes 94.8% at and 90.9% at .

losses of HV synchronous power converters. These proposed
gate drivers with integrated power switches have been fabri-
cated and verified with silicon results, indicating that the perfor-
mances of HV synchronous power converters are significantly
enhanced by the proposed gate drivers.
ACKNOWLEDGMENT
The authors would like to thank the reviewers for their com-
ments that have helped improve the quality of this paper signif-
icantly.
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Zhidong Liu (S'13) received the B.S. degree (with
highest honors) in electrical engineering from Nankai
University, Tianjin, China, in 2007, and the M.S de-
gree in electrical engineering from Peking Univer-
sity, Beijing, China, in 2010. He was an IC designer
in Shanghai Research Institute of Microelectronics
of Peking University, China, from 2010 to 2011. He
is currently working toward the Ph.D. degree in the
Department of Electrical Engineering, University of
Texas at Dallas, Richardson, TX, USA.
In Fall 2014, he was an analog design intern
at Kilby Labs, Texas Instruments Inc., Dallas, where he focused on design
1477
of an isolated AC-DC Flyback switcher. His research interests include
low-power analog integrated circuits, high-voltage soft-switching converters,
and high-voltage integrated LED drivers for high-brightness solid-state lighting
applications.
Lin Cong (S'15) received the B.S. degree (with the
best undergraduate thesis) in electrical engineering
from Beijing University of Technology, Beijing,
China, in 2008, and the M.S. degree in electrical
engineering from Texas Tech University, Lubbock,
TX, USA, in 2010. He worked as a remote sensing
and image processing engineer at DTSGIS, Florida,
USA, in 2012. He joined the Integrated Power
Laboratory of the University of Texas at Dallas,
Richardson, TX, USA, in 2013, where he is currently
pursuing his Ph.D. degree.
His research interests include power management integrated circuits, iso-
lated and non-isolated high-voltage high-frequency switch mode converters,
and zero-voltage-switching techniques.
Hoi Lee (M'05–SM'09) received the B.Eng., M.Phil.,
and Ph.D. degrees in electrical and electronic engi-
neering from the Hong Kong University of Science
and Technology, Hong Kong, China, in 1998, 2000,
and 2004, respectively.
In January 2005, he joined the Department of
Electrical Engineering, University of Texas at
Dallas, Richardson, TX, USA, where he is an
Associate Professor. His current research interests
include power management integrated circuits for
energy harvesting platforms, portable devices, and
renewable energy systems; wireless power transfer for implantable microelec-
tronic devices, and low-voltage low-power analog and mixed-signal circuit
techniques.
Dr. Lee is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS II (TCAS-II) and serves on the Technical Program Committee of the
IEEE Custom Integrated Circuits Conference and the IEEE Circuits and Sys-
tems (CAS) Analog Signal Processing Committee. He formerly served on the
Technical Program Committee of the IEEE Asian Solid-State Circuits Confer-
ence and was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS II from 2007 to 2009. He has received many awards including 2011
National Science Foundation CAREER Award, co-recipients of Best in Session
Award in the 2013 SRC TECHCON conference and Best Student Paper Award
in the 2002 IEEE Custom Integrated Circuits Conference.