Lab Exercise2_ VLSI Design

An edge-triggered D-FF & to find delay, set up & Hold time by simulation.
Aim:
Implementation of an edge triggered flip-flop using level sensitive latches & to Examine the
Hold time and setup time

Design and Simulate the operation of the edge triggered flip-flop shown in figure .

One can use the same size D Flip flop developed in the Lab exercise 1
Determine Hold time and set up time
Use D-FF in Fig. and simulations to help support your clear descriptions.
Theory
Setup time is the least amount of time necessary for the data to be present prior to applied clock
signal in order to capture valid data input. Hold time is the least amount of time necessary for the
data to be present after clock signal in order to capture valid data.
The results are obtained by applying logic 1 to data input and decreasing delay of the clock
compared to data signal to the border point of getting invalid data.
Setup time is found to be -----------?.
Once setup time point is found, hold time is obtained by decreasing width of data pulse to the
border point of getting invalid data.
Hold time is found to be about ------?.
Also, from the figure we can estimate delay through flip flop at about -----?.

Mentioned below is the circuit for the source

Vin d 0 DC 0 PULSE 0 1 50p 1p 1p 44p 0.7n
Vclock clock 0 DC 0 PULSE 0 1 95p 1p 1p 0.2n 0.4n
Vclock_b clock_b 0 DC 0 PULSE 1 0 95p 1p 1p 0.2n 0.4n

The pulse size of Vin, Vclock, Vclock_b can be varied by hit and trial method to reach the
desired result.