STATIC TIMING ANALYSIS

A.B.M. Tafsirul Islam

Static Timing Analysis: Static timing analysis (STA) is a method of validating the timing
performance of a design by checking all possible paths for timing violations. These violations
depend on setup time and hold time analysis.

To have a clear concept about the setup time and hold time in static timing analysis, first have a
glimpse on rise time and fall time of the signal.

Fig.01

In Fig.01 we can see the low to high and high to low transition of the clock signal. This
happened in the ideal case but in the practical case it takes a certain time for high to low and low
to high transition. This is known as rise time and fall time.

Fig.02 Rise Time & Fall Time

Rise Time: The time for a signal that goes from the lower level to the higher level.
Fall Time: The time for a signal that goes from the higher level to the lower level.
Both this signal is measured between the 10% to 90% of the signal level. (Fig.02)
 Fig.03 Pulse Width

Pulse Width: The pulse width is a measure of the elapsed time between the leading and trailing
edges of a single pulse of energy.

Now let's jump into the setup time and hold time. Let's think about the D flip-flop. There is a
clock in D flip-flop and the change of the input of the flip-flop depends on the clock edge. We
know that the flip-flop is manipulated by the edge trigger. So there are two types of edge trigger,
positive edge trigger and negative edge trigger. For example here we will take the positive
edge trigger.

Fig.04 Clock Edge & D Flip-Flop

There is a certain area in the clock signal for which the input data remains always the same. It
means the data can’t change during this time frame in that certain area. That area consists of
setup time and hold time.

Fig.05 Area of Setup Time & Hold Time

Setup Time: Set up time is the time duration for which
the input should remain stable before the arrival of the
clock edge. In the following figure we can see that the
input remains stable before a certain time of the clock's
arrival. (Fig.06)

Fig.06 Setup Time

Hold Time: Hold time is the time duration for which the
input should remain stable after the arrival of the clock
edge. In Fig.07 we can see that the input remains stable
after a certain time of the clock's arrival.

Fig.07 Hold Time

If any of the signal changes between the state of setup time and hold time we will not get the
required output. From this concept here comes the term setup violation and hold violation.

Fig.08 Setup & Hold Violation

Setup Violation: The input signal should remain unchanged in the setup time region. When the
signal changes its state at the setup time region it is known as setup violation. (Fig.08)

Hold Violation: The input signal should remain unchanged in the hold time region too. When
the signal changes its state at the hold time region it is known as hold violation. (Fig.08)
Question: Why is this setup time and hold time required in the static timing analysis?
Answer: To realize the answer properly let's remember the circuit diagram of D Flip-Flop.

Fig.09 D Flip-Flop

Fig.09 is the circuit diagram of the D flip-flop. We can see that there are four NAND gates with
one Inverter along with lots of nets. The data takes some time to travel through those elements of
the flop. This is known as delay and more specifically propagation delay.

Fig.10

We can see from Fig.10 that the D Flip-Flop has a propagation delay of 2ns. Basically
propagation delay is liable for the setup time and hold time. It means the data will take 2ns to
travel from D(input) to Q(output). So they need to set a time for which the state of the data will
remain unchanged. If the state of the data changed during this time the output could be zero or
one or anything that could not be predictable. This situation is known as metastability. In the
figure there we can see that the state of the input signal is changed from zero to one before 1ns of
the positive edge clock. This violates the setup time. Same goes for hold time also. There is a
propagation delay of 1ns of the inverter. So the state of the inverter can’t be changed within 1ns
after the positive edge clock. If the state changes during this time it will meet the hold time
violation. Means the data have to stay the same for 1ns at the inverter.
Propagation delay: Propagation delay is the
time duration taken for a signal to reach its
destination. Such as the output of the following
figure changes from logic high to low after a
certain time (Tphl) not simultaneously with the
change of input from logic low to high.

Metastability: A metastable state is one in which the output of a Flip-Flop is unknown, or

non-deterministic. When a metastable condition occurs, there is no way to tell if the output of the
Flip-Flop is going to be a 1 or a 0. A metastable condition occurs when setup or hold times are
violated.

Fig.11 Metastable State

There are some issues which are related to setup time and hold time. All these things are
discussed below:

Clock Skew:
The difference in the arrival time of a clock signal at two different registers, which can be
caused by path length differences between two clock paths, or by using gated or rippled clocks.
due to:

● wire-interconnect length
● temperature variations
● capacitive coupling
● material imperfections and
● differences in input capacitance on the clock inputs

these factor became more critical for high frequency

Fig. Clock Skew

Clock Jitter: Clock jitter is a characteristic of the clock source and the clock signal environment.
It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically
caused by clock generator circuitry, noise, power supply variations, interference from nearby
circuitry etc.

Fig. Clock Jitter

Max Delay: The data that don't have enough time to pass from one register to another register
before the next clock edge arrives. Max delay violations occurred due to slow data path and for
so it is liable for setup violations means the data is changing during the setup time.

Min Delay: The data path is so short that it passes through several registers during the same
clock cycle. Min delay violations occur for short data paths and so it is liable for hold violations
means the data is changing during hold time.