Lab Exercise_1 VLSI Design;

Latch configuration
There are two latch circuits shown. One is a basic level sensitive latch circuit and other is better
performance level sensitive latch circuit. Compare the performance of both in terms of delay and
noise.
Basic Latch circuit
Result

Answer the following:

1. Why the lengths of feedback inverter I2 are made large?
2. What will be the output of NMOS pass gate?
3. What change is made in the I1 inverter and why?

A modified latch using TG

Result
Answer the following question:
1. Why is TG used on the input of the latch?
2. What disadvantage is associated with the circuit?
3. Why a TG is added in series with the feedback inverter?