VIVA

TASK 01:

1. What is the use of Parity generator and checker in digital logic design?

The use of Parity generator and checker in digital logic design is to detect the single bit errors in the
transmitted data word caused by noise or other disturbances. The sum of the parity bits and data bits
can be either even or odd.
TRUTH TABLE:
A\BC 00 01 11 10
0 1 0 1 0
1 0 1 0 1

TASK 04:

1. Why race condition occurs in SR-Latch and how to overcome it?

When the S and R inputs of an SR latch is at logical 1 and then the input is changed to any other
condition, then the output becomes unpredictable and this is called the race condition.

If the Clock On or High time is less than the propagation delay of the flip flop then racing can be avoided.
This is done by using edge triggering rather than level triggering. If the flip flop is made to toggle over
one clock period then racing can be avoided.

TRUTH TABLE:
CIK S R Q*
 0 * * Q
1 0 0 Q
1 0 1 0
1 1 0 1
1 1 1 *

TASK 05:
 1. Why use only NAND gates or only NOR gates?

We use only NAND gates or NOR gates due to their significance. By using the combination of these
gates, we can implement all other Boolean functions (AND, OR, NOT). This property is called functional
completeness.

TRUTH TABLE:
A B C Á Ć Á C AĆ AĆ + Á C+
B
0 0 0 1 1 0 0 0
0 0 1 1 0 1 0 1
0 1 0 1 1 0 0 1
0 1 1 1 0 1 0 1
1 0 0 0 1 0 1 1
1 0 1 0 0 0 0 0
1 1 0 0 1 0 1 1
1 1 1 0 0 0 0 1