Synchronous Control Strategy of Wafer and Reticle Stage of Step and

Scan Lithography
Li Lanlan1, 2 Hu Song1 Zhao Lixin1 Ma ping1
1 Institute of Optics and Electronics, the Chinese Academy of Sciences;
2 Graduate University of Chinese Academy of Sciences

ABSTRACT

For step and scan lithography systems, the synchronization of reticle stage and wafer stage during exposure is one of the
most important factors that decides the image quality. In this paper, their principle is analyzed through investigating the
structure of step and scan lithography systems. And the coarse and fine laminated model is built. Based on this model,
three different kinds of synchronous control structures containing parallel, series and cross-coupled are proposed. Then,
the reticle stage is used to compensate the error of the synchronous control system of wafer and reticle stage. Simulation
results demonstrate that this control strategy has good synchronization performance, and the synchronous error of wafer
stage and reticle stage is less than 0.5nm without disturbance.
Keywords：Step and scan; synchronous control; wafer stage; reticle stage; synchronous error

1. INTRODUCTION

Lithography has gone through five stages containing contact-mode lithography, proximity lithography, scanning
projection lithography, repeat step projection lithography and step and scan lithography. The step and scan lithography
which is now widely used. Three biggest lithography manufacturers (Nikon, Canon, ASML) have launched new products
of step and scan lithography machines. The lens of step and scan lithography have smaller size and lower cost, and are
easier to manufacture. So they are more suited to the needs of lithography which use big wafers [1, 2].
Different from the conventional repeat step lithography, the exposure quality of step and scan lithography not only
depends on the optical system, but also depends on the dynamic positioning and dynamic synchronous scanning of the
reticle stage and wafer stage. In addition to the action of ultra-precision stepping and positioning, the reticle stage and
wafer stage of step and scan lithography should also complete synchronous dynamic scanning. During the scanning
exposure process of step and scan lithography, strict synchronization is needed between the reticle stage and wafer stage.
If the stages can not meet the synchronous timing requirements, the exposure of wafer will fail, because it will produce a
synchronous error and that will lead to incompleteness of nonsocial synchronous precision. So, how to effectively
guarantee the synchronization of the reticle stage and wafer stage in the high-speed, high precision, large stroke
movement that is the sticking point in the design of the work stage of step and scan lithography [3, 4].
In section 2, a brief overview of the structure and principle of step and scan lithography is given. The coarse and fine
laminated model is presented in section 3. And three different kinds of synchronous control structures are proposed in
section4. Then carefully analysis and discussions of the performance of the synchronous control strategy in which the
reticle stage is selected to compensate the error of the synchronous control system of reticle and wafer stage in Section 5.
In section 6, a conclusion and some advice is given.

2. STRUCTURE AND PRINCIPLE OF STEP AND SCAN LITHOGRAPHY

Lithography is a high-precision and complex system. Figure 1 shows the structure of the step and scan lithography [5, 6].
Reticle stage and wafer stage are supported by air bearing, and arranged in the upper and lower levels of the base frame.
The isolation device between the base frame and ground is used to reduce the influence of external vibration of the motor
system. The lens system is isolated by isolation devices from motor systems to avoid the vibration. The reticle is carried

6th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Design, Manufacturing, and
Testing of Smart Structures, Micro- and Nano-Optical Devices, and Systems, edited by T. Ye, X. Luo, S. Hu, X. Bao, Y. Li,
Proc. of SPIE Vol. 8418, 84180M · © 2012 SPIE · CCC code: 0277-786/12/$18 · doi: 10.1117/12.971476

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 by reticle stage; the wafer to be exposed is carried by the wafer stage. During the process of scanning exposure, the
reticle stage and the wafer stage move precisely synchronously in the scanning direction.
Light
Reticle
Balance
Mass Fine Stage
Reticle
Stage
Coarse Stage

Air mount Air mount

Lens

Wafer
Balance
Mass Fine Stage
Wafer
Stage
Coarse Stage

Base Frame

Figure 1: The structure of step and scan lithography

The exposure process of step and scan lithography is shown in Figure 2. A bunch of Narrow beam which has been
expanded, shaped and uniformed by the optical system pass through the reticle and the projection lens, then the graphics
on the reticle are projected on surface of the wafer coated with photoresist. The reticle stage and wafer stage scan
synchronously, so that the graphics are exposed on the surface of the wafer. The exposure of one exposure field is
completed during each scanning movement, and then the wafer step to the scanning starting position of the next exposure
field to repeat the scanning movement, until all the fields on the wafer are exposed. The ratio of the reticle size and wafer
size is 4:1, and the wafer stage and reticle stage should scan synchronously in opposite directions.
Light
Photomask Exposed Field

Lens 300mm

Wafer

8mm
26mm

Field being
33mm scanned

Figure 2: The exposure principle of step and scan lithography

Graphic exposure is completed during the synchronous scanning process. In order to ensure the quality of wafer
exposure, the two stages must maintain the synchronization of their relative position at each mount during the scanning
process. Actually, due to external disturbance and the dynamic performance, the reticle and wafer stage can not maintain
the synchronization in real-time; there is a certain relative error. In addition, the wafer stage is four times heavier than the
reticle stage, and the response speed is different, which adds difficulty to the synchronization control system.

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 3. MODEL OF COARSE AND FINE LAMINATED STAGE

For the lithography of wafers whose diameter is 300mm, the travel range of wafer stage is greater than 300mm, and the
scanning speed of it is 120mm/s or faster; the travel range of reticle stage is greater than 130mm, and the scanning speed
of it is 4 times as the wafer stage. Also, during the scanning process, high tracking accuracy and synchronization
accuracy are asked. In order to ensure the travel range, the high-speed and the high precision, the coarse and fine
laminated structure is used for reticle stage and wafer stage. Therefore, study on the coarse and fine laminated mode is
the foundation of synchronous control of reticle stage and wafer stage.
Coarse and fine laminated structures are prevalent in the system of optical disk drive and precision workbench. The dual
structure of the stages includes a coarse stage and a fine one. The simplified and equivalent model of this structure can be
represented as in Figure 3 [7].

Figure 3: Model of coarse and fine laminated stage of reticle stage and wafer stage
In Figure 3, M c is the mass of coarse stage, M f is the mass of fine stage, U c is the driving force of coarse stage,
and U f is the driving force of fine stage. K and B denote coupling elasticity coefficient and coupling viscosity constant
due to the characteristics of mechanical system and the closed loop controller.
The state space representation of the system is expressed as:
.
x = Ax + B1u (1)
y = Cx + Du
Where x = [x1 , x 2 , x 3 , x 4 ] , u = [u c , u f ] , y = [y c , yf ]T ,
T T

⎡ 0 1 0 0 ⎤ ⎡ 0 0 ⎤
⎢ K B K B ⎥ ⎢ 1 1 ⎥⎥ ⎡1 0⎤
T
⎢- - ⎥ ⎢ − ⎢0
⎢ M Mc Mc Mc ⎥ ⎢ Mc Mc ⎥ 0 ⎥⎥
A= ⎢ c ⎥ , B1 = ⎢ ⎥ , C = ⎢⎢ , D=0.
⎢ 0 0 0 1 ⎥ ⎢ 0 0 ⎥ 0 1⎥
⎢ K ⎢ ⎥
B K B ⎥ ⎢ 1 ⎥ ⎣0 0⎦
⎢ − - ⎥ ⎢ 0 ⎥
⎣ M2 M2 M2 M2 ⎦ ⎣ Mf ⎦
x1 , x 2 , x 3 , and x 4 in equation (1) represent position of coarse stage, speed of coarse stage, position of fine stage, and
speed of fine stage. The system transfer matrix is then derived as
⎛ M e (M f s 2 + Bs + K) Me − Mf ⎞
⎜ ⎟
⎛ Yc ⎞ ⎜ M c M f (M es 2 + Bs + K) M f (M es + Bs + K) ⎟ ⎛ U c ⎞
2

⎜ ⎟= ⎟ ⎝⎜ U f ⎠⎟
(2)
⎝ Yf ⎠ ⎜ M e (Bs + K) Me
⎜ ⎟
⎝ M c M f s (M es + Bs + K) M f (M es 2 + Bs + K) ⎠
2 2

McMf
Where M e = .
Mc + Mf

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 The output position of fine stage is affected by the driving force of coarse stage and the external interference which have
effect on fine stage through the coarse and fine laminated structure and control systems. With the model in Figure 3 and
the above derivation, we can obtain the transfer function from the driving force of coarse stage to the position of fine
stage:
Yf M（e Bs+K）
G fc = = (3)
U c M c M（
f M eS +Bs+K）
2

Therefore, in order to reduce the coupling effect of driving force of coarse stage on the output of the fine stage, we can
reduce either elasticity or viscosity of the system.

4. STRUCTURE OF SYNCHRONOUS CONTROL

The reticle stage and wafer stage of step and scan lithography scan synchronously, so that the graphics are printed on the
wafer continuously. Based on the coarse and fine laminated model three kinds of synchronous control structure
containing parallel, series and cross-coupled are proposed [8].
4.1 Parallel mode synchronous control
The simplest method for two work stages to move synchronously is to input the same command at the same time, and the
structure of this method is called parallel mode synchronous control which is shown in Figure 4.
For the parallel mode synchronous control, each stage has a separate close-loop control. The controllers of the two stages
receive trajectory command from the trajectory planner respectively and travel following the command. The position
difference of the two stages is called the synchronization error.

blau

Figure 4: Block diagram of parallel mode synchronous control

In Figure 4, P1 and P2 represent the models of two stage; C1 and C 2 represent the controllers of the stages;
e syn represents the synchronization error of the stages.
With the parallel mode synchronized control, the control loop of one stage receives no information about the other one.
Any following error of one stage caused by the disturbance is only corrected by its own control loop, while the other one
carries on as before. Thus, a synchronization error will be caused by the following error of one stage directly.
Corresponding to the decreasing of following error of individual stage, the synchronization error decreases.
4.2 Series mode synchronous control
Series mode synchronous control is a traditional control structure, and the block diagram of it is showed in Figure 5. The
system is divided into two parts, the host system and the slave system.
Zzs]ecfc

Figure 5: Block diagram of series mode synchronous control

In Figure 5, P1 denotes the model of the host work stage, and C1 is the controller of it; P2 stands for the model of
the slave work stage, and C 2 is the controller of it; e syn represents the synchronization error of the stages. The input

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 of slave system is the output of host system. According to the differences in mechanism or servo bandwidth, the
proportional gain of the system is adjusted. However, this method can easily cause tracking error due to servo behind.
Therefore, it can be applied to the system which has mechanical coupling, if the maximum of synchronization error is
within tolerance.
4.3 Cross-coupling mode synchronous control
The block diagram of cross-coupling synchronization control system block diagram shown in Figure 6:

ZxslscFo

Figure 6: Block diagram of cross-coupling synchronous control

In Figure 6, P1 and P2 indicate the models of two stage; C1 and C 2 represent the controllers of the stages; e syn stands
for the synchronization error of the stages; G cc denote the cross-coupling controller. The cross-coupling controller G cc
calculates the compensate value and feed to the controller of individual close-loop. By this means, both the individual
following error and synchronization error are corrected by the close-loop, thus the individual travel performance may be
affected by the other stage. The cross-coupling controller should be designed appropriately to keep system stable.

5. DISCUSSION

Compared with the wafer stage in step and scan lithography, the reticle stage possesses the qualities of simpler structure,
lighter weight, smaller load and more flexible movement. Moreover, the system bandwidth decreases with the increasing
of the lord of the wafer stage. Therefore, based on the synchronous control structures discussed above, the reticle stage is
selected to compensate the synchronization error[9].

2o2.oa
Pio

PID Controller

bt

oPe

Un,orn Random
Numberl 16 8

PID .,,:ñ;°PO.,
PID Controller

Figure 7: Synchronous control system of reticle stage and wafer stage

Figure 7 shows the simulation diagram of the synchronous control system which uses reticle stage to compensate the
synchronization error in MTLAB.

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 0

0. 005 i i

0. 01 4

0. 015 J

0. 02

0.025

-0.03
2 3 4 5 6 7 8 9 10

Figure 8: Waveform of the synchronization error of the reticle stage and wafer stage
Figure 8 represents waveform of the synchronization error of the reticle stage and wafer stage. The synchronous error of
wafer stage and reticle stage is less than 0.5nm without disturbance.

6. CONCLUSION

Based on the coarse and fine laminated model, three kinds of synchronous control structure were discussed. The
synchronization error of the parallel mode control structure will be caused by the following error of one stage directly.
Corresponding to the decreasing of following error of individual stage, the synchronization error decreases. The series
mode synchronous control structure can be applied to the system which has mechanical coupling, if the maximum of
synchronization error is within tolerance. The cross-coupling controller of cross-coupling mode synchronous control
should be designed appropriately to keep system stable. The reticle stage is used to compensate the error of the
synchronous control system of wafer and reticle stage. Simulation results demonstrate that this control strategy has good
synchronization performance, and the synchronous error of wafer stage and reticle stage is less than 0.5nm without
disturbance.

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