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Qsys PDF
Qsys PDF
❑ Lab CLO’s
❑ Objectives of Lab
❑ Nios II System
❑ Qsys
❑ Advantages of using Qsys
❑ Development Processes
Lab CLO’s
❑ To design the digital systems based on HDL modelling techniques using the knowledge of VHDL.
(PLO3-C5)
❑ To manipulate the basic building blocks of a Nios II based embedded systems using Software and
Hardware Platforms. (PLO5-P5)
❑ To explain and write effective lab reports of experiments performed during lab. (PLO10-A3)
Objectives of Lab
❑ The Nios II processor can be used with a variety of other components to form a
complete system.
Qsys
Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II
package, to configure and generate a Nios system.
Defining and Generating the System in Qsys
The design you build in this lab is a small NIOS II system consist of the
following components.
❑ On-chip memory
❑ JTAG UART
❑ ALTPLL
❑ System ID peripheral
System ID Peripheral
❑ System ID is for systems involving multiple processors.
❑ System ID also prevents you from having a mismatch between your hardware and software configurations.
When you compile the software, it stores the system ID of the SOPC Builder/QSYS project at the time of
the compile.
In case of any query email at muhammadmoin@cuilahore.edu.pk