Professional Documents
Culture Documents
VIN 2 VIN 1
BOOT
4.5V to 23V CIN CBOOT L
10µF RT8292B 100nF 3.6µH
VOUT
SW 3
3.3V/2A
REN 100k 7 EN R1
75k
8 SS COUT
FB 5 22µF x 2
C SS CC RC
0.82nF 32k R2
0.1µF 4, 9 (Exposed Pad) 6 24k
GND COMP
CP
Open
VIN
Internal
Regulator Oscillator
Current Sense
Shutdown Slope Comp Amplifier
Comparator VA VCC + VA
Foldback
1.2V + Control -
-
0.4V + BOOT
Lockout -
Comparator UV S Q 130mΩ
5k Comparator SW
EN - +
R Q 130mΩ
2.7V + -
3V Current GND
Comparator
VCC
6µA
0.8V +
SS +EA
-
FB COMP
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Shutdown Supply Current VEN = 0V -- 0.5 3 µA
Supply Current VEN = 3V, VFB = 0.9V -- 0.8 1.2 mA
Feedback Voltage VFB 4.5V ≤ VIN ≤ 23V 0.788 0.8 0.812 V
Error Amplifier
GEA ∆IC = ±10µA -- 940 -- µA/V
Transconductance
High Side Switch
RDS(ON)1 -- 130 -- mΩ
On-Resistance
Low Side Switch
RDS(ON)2 -- 130 -- mΩ
On-Resistance
High Side Switch Leakage
VEN = 0V, VSW = 0V -- 0 10 µA
Current
Upper Switch Current Limit Min. Duty Cycle, V BOOT − VSW = 4.8V -- 4.3 -- A
Lower Switch Current Limit From Drain to Source -- 1.3 -- A
COMP to Current Sense
GCS -- 4 -- A/V
Transconductance
Oscillation Frequency fOSC1 1 1.2 1.4 MHz
Short Circuit Oscillation
fOSC2 VFB = 0V -- 270 -- kHz
Frequency
Maximum Duty Cycle DMAX VFB = 0.7V -- 75 -- %
Minimum On Time tON -- 100 -- ns
To be continued
www.richtek.com DS8292B-03 March 2011
4
RT8292B
Parameter Symbol Test Conditions Min Typ Max Unit
EN Input Threshold Logic-High V IH 2.7 -- 5.5
V
Voltage Logic-Low V IL -- -- 0.4
Input Under Voltage Lockout Threshold V UVLO VIN Rising 3.8 4.2 4.5 V
Input Under Voltage Lockout Hysteresis V UVLO -- 320 -- mV
Soft-Start Current ISS VSS = 0V -- 6 -- µA
Soft-Start Period tSS CSS = 0.1µF -- 13.5 -- ms
Thermal Shutdown TSD -- 150 -- °C
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at T A = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
90 0.815
80
40 0.795
30
0.790
20
0.785
10
VOUT = 3.3V
0 0.780
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 4 6 8 10 12 14 16 18 20 22 24
Output Current (A) Input Voltage (V)
0.815 3.33
Reference Voltage (V)
0.810 3.32
Output Voltage (V)
0.805 3.31
0.800 3.30
VIN = 23V
0.795 3.29 VIN = 12V
0.790 3.28
0.785 3.27
VOUT = 3.3V
0.780 3.26
-50 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Temperature (°C) Output Current (A)
1.26 1.30
1.24 1.25
1.22 1.20
1.20 1.15
1.18 1.10
1.16 1.05
1.14 1.00
1.12 0.95
VOUT = 3.3V, IOUT = 0A VIN = 12V, VOUT = 3.3V, IOUT = 0A
1.10 0.90
4 6 8 10 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)
4.5 4.75
VOUT VOUT
(50mV/Div) (50mV/Div)
IOUT IOUT
(1A/Div) (1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A
Switching Switching
VOUT VOUT
(10mV/Div) (10mV/Div)
IL IL
(1A/Div) (1A/Div)
VSW VSW
(10V/Div) (10V/Div)
VIN VIN
(5V/Div) (5V/Div)
VOUT
(2V/Div) VOUT
(2V/Div)
IL IL
(2A/Div) (2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
VEN VEN
(5V/Div) (5V/Div)
VOUT VOUT
(2V/Div) (2V/Div)
IL IL
(2A/Div) (2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
The output ripple will be highest at the maximum input Checking Transient Response
voltage since ∆IL increases with input voltage. Multiple The regulator loop response can be checked by looking
capacitors placed in parallel may be needed to meet the at the load transient response. Switching regulators take
ESR and RMS current handling requirement. Dry tantalum, several cycles to respond to a step in load current. When
special polymer, aluminum electrolytic and ceramic a load step occurs, VOUT immediately shifts by an amount
capacitors are all av ai labl e in surf ace mount equal to ∆ILOAD (ESR) and COUT also begins to be charged
packages.Special polymer capacitors offer very low ESR or discharged to generate a feedback error signal for the
value. However, it provides lower capacitance density than regulator to return VOUT to its steady-state value. During
other types. Although Tantalum capacitors have the highest this recovery time, VOUT can be monitored for overshoot or
capacitance density, it is important to only use types that ringing that would indicate a stability problem.
pass the surge test for use in switching power supplies.
EMI Consideration
Aluminum electrolytic capacitors have significantly higher
ESR. However, it can be used in cost-sensitive applications Since parasitic inductance and capacitance effects in PCB
for ripple current rating and long term reliability circuitry would cause a spike voltage on SW pin when
considerations. Ceramic capacitors have excellent low high side MOSFET is turned-on/off, this spike voltage on
ESR characteristics but can have a high voltage coefficient SW may impact on EMI performance in the system. In
and audible piezoelectric effects. The high Q of ceramic order to enhance EMI performance, there are two methods
capacitors with trace inductance can also lead to significant to suppress the spike voltage. One way is by placing an
ringing. R-C snubber between SW and GND and locating them as
close as possible to the SW pin (see Figure 5). Another
Higher values, lower cost ceramic capacitors are now
method is by adding a resistor in series with the bootstrap
becoming available in smaller case sizes. Their high ripple
capacitor, CBOOT , but this method will decrease the driving
current, high voltage rating and low ESR make them ideal
capability to the high side MOSFET. It is strongly
for switching regulator applications. However, care must
recommended to reserve the R-C snubber during PCB
be taken when these capacitors are used at input and
layout for EMI improvement. Moreover, reducing the SW
output. When a ceramic capacitor is used at the input
trace area and keeping the main power in a small loop will
and the power is supplied by a wall adapter through long
be helpful on EMI performance. For detailed PCB layout
wires, a load step at the output can induce ringing at the
guide, please refer to the section Layout Considerations.
input, VIN. At best, this ringing can couple to the output
RBOOT*
VIN 2 VIN 1
BOOT
4.5V to 23V CIN CBOOT
RT8292B L
REN* 10µF 100nF 3.6µH VOUT
Chip Enable SW 3
7 EN 3.3V/2A
RS*
CEN* R1 COUT
CS* 75k 22µFx2
8 SS
FB 5
CSS 4, CC
0.1µF 9 (Exposed Pad) RC R2
0.82nF 32k
GND 6 24k
COMP
CP
* : Optional NC
Figure 5. Reference Circuit with Snubber and Enable Timing Control
DS8292B-03 March 2011 www.richtek.com
11
RT8292B
Thermal Considerations resistance θJA. For RT8292B packages, the derating curves
For continuous operation, do not exceed the maximum in Figure 7 allows the designer to see the effect of rising
operation junction temperature 125°C. The maximum ambient temperature on the maximum power dissipation .
power dissipation depends on the thermal resistance of 2.2
Four-Layer PCB
IC package, PCB layout, the rate of surroundings airflow 2.0
The junction to ambient thermal resistance θJA is layout Ambient Temperature (°C)
dependent. For SOP-8 (Exposed Pad) package, the Figure 7. Derating Curves for RT8292B Package
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P D(MAX) = (125°C − 25°C) / (49°C/W ) = 2.04W
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
(70mm2copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(b) Copper Area = 10mm2, θJA = 64°C/W
(Exposed Pad) package.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. W hen mount ed to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e) (c) Copper Area = 30mm2 , θJA = 54°C/W
reduces the θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
(d) Copper Area = 50mm2 , θJA = 51°C/W (e) Copper Area = 70mm2 , θJA = 49°C/W
Layout Considerations
For best performance of the RT8292B, the following layout guidelines must be strictly followed.
} Input capacitor must be placed as close to the IC as possible.
} SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace.
} The feedback components must be connected as close to the device as possible
C
I
D
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.