Digital VLSI Design

The Verilog Language :

▪ Originally a modeling language for a very efficient event-driven digital logic
simulator
▪ Later pushed into use as a specification language for logic synthesis
▪ Now, one of the two most commonly-used languages in digital hardware
design (VHDL is the other)
▪ Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these
two languages
▪ Combines structural and behavioral modeling styles
Reg and Wire :
Wire:

Wires are used for connecting different elements. They can be treated as physical
wires. They can be read or assigned. No values get stored in them. They need to be
driven by either continuous assign statement or from a port of a module.

Reg:-

Contrary to their name, regs don't necessarily correspond to physical registers. They
represent data storage elements in Verilog. They retain their value till next value is
assigned to them (not through assign statement). They can be synthesized to FF,
latch or combinatorial circuit.
Blocking Vs Non-blocking :
Blocking statements allow you to block this procedural barrier, hence, you can
use the flow of statements like C language in which statements are executed one
after the other.

On the other hand, when we talk about Non- blocking statements, it essentially
enables the power of Verilog. What is does is, it imitates register like behavior.
Hence, all the non blocking statements execute at an instant (parallel execution);
i.e in a single clock cycle the execution of each statement in that particular
non-blocking scope will start its execution. However, depending on the instructions
some statements may take longer to finish whilst other could complete in a jiffy.
1) Write a verilog code to swap contents of two registers with and without a
temporary register?
Initial Block :

● Not synthesizable

● Can’t be converted into a hardware

schematic with digital elements

● These blocks are primarily used to

initialize variables and drive design
ports with specific values
If there is delay element -
Always block :
● The always block is executed at some
particular event defined by sensitivity list
.

● Sensitivity list is the expression that

defines when the always block should be
executed .

If there is no sensitivity list , the always blocks repeats continuously throughout the duration of simulation
Example :

2:1 MUX

➔ Using assign statement

➔ Using if statement

➔ Using case statement

Using assign statement :
module mux_using_assign(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
wire mux_out;
//-------------Code Start-----------------
assign mux_out = (sel) ? din_1 : din_0;

endmodule //End Of Module mux

Using IF statement :
module mux_using_if(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end

endmodule //End Of Module mux

Using CASE statement :
module mux_using_case(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
case(sel )
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
end

endmodule //End Of Module mux