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FPGA Design
李明哲
Lec. 3
Feb. 20, 2023
Modules
Verilog is both a behavioral and a structural
language
Internals of each module can be defined at four
levels of abstraction, depending on the needs of the
design
The module behaves identically with the external
environment irrespective of the level of abstraction
at which the module is described
Thus, the level of abstraction to describe a module
can be changed without any change in the
environment
Binary
Binary operators shall appear between their
operands ( 運算元 )
ternary or conditional
Conditional operators have two separate
operators that separate three operands