1

Advanced Miccroelectronic
Design (M2R Systèmes
embarqués )
Part I

Prof. Bilal BEYDOUN

Lebanese University
Faculty of Sciences

B.BEYDOUN (2020_2021)
 2

Outline

Introduction to Semiconductor Design

Planar technology

Components design

Circuit design
VLSI design
 Materials
•  Single crystal silicon – SCS
–  Anisotropic crystal
–  Semiconductor, great heat conductor
•  Polycrystalline silicon – polysilicon
–  Mostly isotropic material
–  Semiconductor
•  Silicon dioxide – SiO2
–  Excellent thermal and electrical insulator
–  Thermal oxide, LTO, PSG: different names for different deposition
conditions and methods
•  Silicon nitride – Si3N4
–  Excellent electrical insulator
•  Aluminum – Al
–  Metal – excellent thermal and electrical conductor
Band structure of Semiconductors
 Doping semiconductors

•  Two different types of conduction

–  Electrons (negative, N-type)
–  Holes (positive, P-type)
 INCREASED INTEGRATED CIRCUIT COMPLEXITY

130nm 90nm 45nm 32nm 22nm 5nm

100M 250M 500M 2G 7G 150 G

2004 2006 2008 2010 2012 2020

Core+ Core Dual core Quad Core ?
DSP Dual DSP Quad DSP
DSPs
1 Mb RF 3D Image Proc
10 Mb Crypto processor
Mem Graphic
Mem Process. Reconf FPGA,
100 Mb Mem Multi RF
Sensors 1 Gb Memories
Multi-sensors
 CONTEXT

SMALLER PATTERNS
Gate Dielectric High voltage
Thickness (nm) MOS (double
gate oxide)
10nm
0.25µm
0.18µm
0.13 µm
90nm
65nm 45nm
32nm
1nm
Low voltage
MOS (minimum 22nm 18nm
11nm Down to
gate oxide)
which
HighK (εr=7-20)
SiON (εr=4.2-6.5)
limit ?
0.1nm
SiO2 (ε r=3.9)
Year

1995 2000 2005 2010 2015

 CONTEXT

TECHNOLOGY LIFE CYCLE

22nm
32nm
Production 45nm
65nm
90nm
Price x 1.5
130nm
Why
0.25µm
0.18µm
smaller
devices?
0.35 µm
0. 5 µm

Year
1995 2000 2005 2010 2015
 CONTEXT

THE ELECTRONIC MARKET GROWTH

30%
Individuals

Companies PC at home MP3 HDTV 3DTV

Internet DVD 3G 4G
20% PC in companies GSM

Flat screens Society

Audio CD
Defense
Automotive Local Energy
Security
Medical
10%

Recession Recession Bank 7 % 2013

-10% crash 4% 2014
Telecom 0.2%
crash 2012

83 86 89 92 95 98 01 04 07 10 13 16

Year
Adapted from Electronique International Mai 21, 2009
 CONTEXT
World
MOBILE SUBSCRIBERS population

7000
6000
5 B - Aug
10
5000
4 B – Dec
4000 09

3500 3 B – Oct 08
3000
2500 Global mobile-phone
3G
subscribers hit 2B (Oct 05) 1.2 Billion
2000 3G
More mobiles than 900
1500 fixed phones in Million
France (Oct 01) 1000 3G
400 Million
1000
400
500

2000 2003 2005 3G

2007 2009 2011 4G
100 M
100 Million
 CONTEXT
Tri-Gate for
increasing drive
High K Metal Gate current and
INCREASED SWITCHING to increase field reducing leakage
PERFORMANCES effect

Strain to increase
Current mobility
drive (mA/
µm)
2.0

1.5
Gate
material

1.0
Strain

0.5
Intrinsic
performances
0.0
130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 17 nm
Technology node
 CONTEXT

DECREASED VOLTAGES AND NOISE MARGIN

500 mV 100 mV
Supply (V)
margin margin
5.0

3.3 I/O supply

2.5 Core supply

1.8
1.2
1.0

0.5µ 0.35µ 0.18µ 130n 90n 65n 45n 32n 22n 17n
Technology Adapted from ITRS roadmap for semiconductors, 2011
14
November 20
 ZOOM AT INTEGRATED DEVICES

SYSTEM TO INTEGRATED CIRCUITS

10 mm
100 mm

15
November 20
Integrated
Circuits…

1mm 10µm

100 nm
1 µm 17
November 20
© Intel Xeon
P Transistor Structure Review

Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected

to VDD

p transistor
 Building a computer from off-the-shelf
parts
Needs: System to write
documents, spreadsheets
and communicate
Technology Integration

Computer

Design: Integrated
Assemble from standard, system requirements
off-the-shelf parts
Technology Base

Dell, IBM, HP, Hard drive Processors Op. System

Toshiba
Sound card Chassis Software Parts
from any vendor;
open source software
 Building a computer from
off-the-shelf parts

Technology Base

Dell, IBM, HP, Hard drive Motherboard Op. System

Toshiba Devices
Sound card Chassis Software from any vendor;
open source software

Knowledge base
Fundamental knowledge interdependencies Parts/devices/chasses
to build basic computer requirements
components
Knowledge Base

Other technologies: Silicon wafer High-level lang. Characterization

cell phone
Independent devices Standard connections
Foundational
science and
applied research
A View of the Cleanroom

AMD’s Dresden Fab - Source: AMD Corporation www.amd.com

Semiconductor Manufacturing:
Planar Technology
 Crystal Growth

•  Reduction Process
SiO2 + 2C → Si + 2CO↑ (at 1800°C)
Result: Metallurgical grade Si:
Purity:99.99%; Impurities: Fe, Al, C…
•  Purification Process
Si + 3HCl → SiHCl3 + H2↑ (Distillation)
2 SiHCl3 + 2H2 → 2Si + 6HCl↑
Electronic grade Si: 99.999999999%
 Creating the Silicon Wafers

•  Wafer growing process

–  Similar to elementary science class (string in sugar
water)
•  A seed crystal of silicon is immersed in a bath of molten silicon,
and slowly pulled out.
–  Crystal growth occurs uniformly in all directions
•  This pulling process lasts for around 24 hours
–  Creating ingot with diameter larger than desired.
–  Ingot is ground down to required diameter and the end is cut off
•  The ingot is then sliced into very thin wafers
–  These wafers must be finely polished to meet surface flatness and
thickness specifications.
 Creating Wafers - Czochralski Method

•  Start with crucible of

molten silicon (≈1425oC)
•  Insert crystal seed in melt
•  Slowly rotate / raise seed
to form single crystal
boule
Molten
•  After cooling, slice boule Silicon
Crucible
into wafers & polish
Silicon wafer fabrication
Semiconductor fabrication (1)

2
 Silicon wafer fabrication – slicing and polishing

•  Taken from www.egg.or.jp/MSIL/english/index-

e.html
Silicon Ingots (12” and 16”)
Silicon Wafer
 Wafer Structure

•  Current production: 200mm (10”)

•  Newest technology: 300mm (12”)

Die - Single IC chip

300mm wafer
Image Source: Intel Corporation
www.intel.com
 Processing Wafers
•  All dice on wafer processed simultaneously
•  Each mask has one image for each die
•  The basic approach:
–  Add & selectively remove materials
•  Metal - wires
•  Polysilicon - gates
•  Oxide
–  Selectively diffuse impurities
•  Photolithography is the key
Patterning on Si
 The Mask-Making Process

•  Composite of Mask
–  Film of chromium on a pure quartz glass plate.
–  Finished plates are called Reticles
•  Design of Mask
–  Reticles are manufactured by very sophisticated and expensive
pattern generation equipment driven by the chip design database.
–  As more components are placed on
each chip
•  More complex patterns are drawn
•  Which adds to the time to write the mask
–  Driven by new product acceleration.
•  Each new design or die shrink requires
New mask tooling


 Epitaxy

•  Epitaxial Growth
–  Process of depositing a thin layer
•  0.5 to 20 microns of single crystal material onto wafer
–  Must be ultra pure
•  In order to create best possible quality of silicon
•  Contaminant free for the construction of transistors
–  Called the epi-layer
•  Usually 3% or less of original wafer thickness.
 Oxidation & Exposure
•  Once Lithography has spun on photoresist
–  Baked to create harder surface
–  Then expose to reticle step by step creating
pattern on wafer.
–  Implant process would destroy photoresist
so next process is to move photoresist to tougher
oxide layer.

 Photolithography
•  How photolithography works
–  Process of transferring a pattern from mask to surface of a
silicon wafer.
•  Current Method
–  Wafer is coated with photoresist material
–  Reticle(Mask) is exposed by laser through lens system onto
the wafer one die or a few at a time. Until entire wafer has
been exposed
–  Similar to creating a photograph by
means of a very sophisticated
photographic negative.
 Etch & Strip

•  Etch Process can be wet or dry

–  Wet eats away but is not easily manageable.
•  Once on, beyond control could eat away at sides.
–  Dry controllable costly
•  Uses gas excited by radio freq generates plasma
state.
–  Remove oxide layer
•  Were photoresist patter is not present.
•  Stripping Process
–  Photoresist has served its purpose and must be removed
•  Photoresist must be entirely removed since it consists of organic materials which
if left on wafer surface will cause defects
•  Use both wet and dry techniques to strip this layer away from wafer.
 Diffusion & Implant
•  Classic approach to creating electrical
pockets
–  Deposit material such as Boron on surface
•  Drive into surface of silicon by exposing to
controlled
periods of high temperature. Causes side
ways diffusion
•  Device geometries are becoming smaller
diffusion
harder to deal with

•  Improved approach
–  Ion implantation process
•  Material is implanted vertically into surface
by high energy ion beams penetrating silicon
vertically without any side ways diffusion
 Deposition
•  Removal and regrowth of oxide layer
–  Repeat lithography, etch and strip processes with different mask to
create a window opening in the oxide were the transistor gate is built.
–  The gate is a conductive layer which is separated from the silicon by a
thin gate oxide.
–  Positive electrical charge on the gate will create an opposite negative
field in the surface of the silicon
–  This creates a conductive channel between the source and the drain,
letting current flow between them.
–  Gate must be thin to allow electrical field to transfer across insulator
usually made by depositing silicon nitride film
 Oxidation
•  Oxides are grown or deposited
–  Used to insulate or protect formed transistors
–  Also used to insulate from its adjacent transistors
–  Dielectric isolation oxides
•  Used to insulate transistors from interconnection layers which will
be built above
–  Passive oxides
•  Deposited on top of competed wafers to protect the surface from
damage.
 Interconnect Vias

•  Photolithography again
–  Used to create holes etched down to the three
transistor regions which will be connected to
other components on the chip
–  Holes (Vias) are essentially chemically drilled
holes which expose the contacts to the three
terminals of the transistor.
Interconnect – Metallization

•  A layer of aluminum is deposited on the surface

and down into the via holes
–  Excess aluminum is etched away after another
photolithography process
•  Another layer of dielectric oxide
–  Insulate the first layer of aluminum
from the next one
•  Problems
–  Contours create obstacles or steps which make
it difficult to lay down next metal layer. It is highly
desirable to smooth the surface between steps.
–  Chemical Mechanical Planariazaion
•  Used to smooth surface circular sanding action
polishes the
surface of the wafer smooth
 Interconnect – Cont

•  After Chemical Mechanical

Planarization
–  Another set of Via holes etched in the
oxide
–  Contact plugs are deposited
•  Usually made from tungsten or
titanium
•  Allows connection between two layers
of aluminum
–  After plug is in next layer of aluminum
is deposited
•  This process can be repeated up to 6
layers for very complex logic chips
Memory chips usually on have 2
 Inspection & Measurement

•  Inspection and Measurement is Critical

–  Chip making deals with so many state-of-the-art materials,
and methods with small features and precision, that the
ability to measure and monitor the process is vital.
–  Inspection deals with tools that deal with sub-micron
levels, scanning electron microscopes must be used.
–  As Geometries get size down to .2 micros the ability to
observe these defects becomes more challenging and
expensive.
 Infrastructure - Yield

•  Defects kill yield and drive up cost

–  Inspection is vital in Fabrication.
•  What a defect causes
–  Cause electrical short circuits
–  Open circuits or breaks in aluminum traces
•  Causes of Defects
–  Atmosphere in the Fabrication process
•  Must have ultra clean room requirement
–  Materials Used or tools that were used
–  The smaller the die the larger the population of die per wafer and
the lower the statistical impact of the defects
 Assembly & Packaging

•  Assimilation of Die
–  Wafer arrives with reject die marked with ink
–  Saw between each die in both directions separating the
good die out
–  Die’s are die bonded or attached onto the frame of a
package either epoxy or with silicon metal eutectic bond
–  Then each die pin is connected using thin gold or
aluminum wire
–  Bonded die and frame are sealed either by a molded
plastic compound or by attachment of a sealed lid
–  Depending on the package type, the pins or leads may
have to be trimmed and formed to desired shape or use
in applications.
 IC Fabrication and Micromachines

•  IC Fabrication Technology
–  Introduction – the task at hand
–  Doping
–  Oxidation
–  Thin-film deposition
–  Lithography
–  Etch
–  Lithography trends
–  Plasma processing
–  Chemical mechanical polishing
Semiconductor Fabrication (2)

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 Semiconductor Fabrication (3)

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Semiconductor Fabrication (4)
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END